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8029101: PPC64 (part 211): ordering of Independent Reads of Independent Writes

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Reviewed-by: dholmes, kvn
This commit is contained in:
Martin Doerr 2014-01-16 14:25:51 +01:00 • committed by Goetz Lindenmaier
parent 06b9210700
commit 0306737032
8 changed files with 57 additions and 7 deletions
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11
hotspot/src/share/vm/utilities/globalDefinitions.hpp
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@ -398,6 +398,17 @@ const uint64_t KlassEncodingMetaspaceMax = (uint64_t(max_juint) + 1) << LogKlass
#define PLATFORM_NATIVE_STACK_WALKING_SUPPORTED 1
#endif
// To assure the IRIW property on processors that are not multiple copy
// atomic, sync instructions must be issued between volatile reads to
// assure their ordering, instead of after volatile stores.
// (See "A Tutorial Introduction to the ARM and POWER Relaxed Memory Models"
// by Luc Maranget, Susmit Sarkar and Peter Sewell, INRIA/Cambridge)
#ifdef CPU_NOT_MULTIPLE_COPY_ATOMIC
const bool support_IRIW_for_not_multiple_copy_atomic_cpu = true;
#else
const bool support_IRIW_for_not_multiple_copy_atomic_cpu = false;
#endif
// The byte alignment to be used by Arena::Amalloc. See bugid 4169348.
// Note: this value must be a power of 2