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8214751: X86: Support for VNNI Instructions
Co-authored-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com> Reviewed-by: kvn
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18 changed files with 491 additions and 4 deletions
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@ -3966,6 +3966,34 @@ void Assembler::vpmovzxwd(XMMRegister dst, XMMRegister src, int vector_len) {
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emit_int8((unsigned char)(0xC0 | encode));
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}
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void Assembler::pmaddwd(XMMRegister dst, XMMRegister src) {
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NOT_LP64(assert(VM_Version::supports_sse2(), ""));
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InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
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int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
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emit_int8((unsigned char)0xF5);
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emit_int8((unsigned char)(0xC0 | encode));
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}
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void Assembler::vpmaddwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
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assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
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(vector_len == AVX_256bit ? VM_Version::supports_avx2() :
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(vector_len == AVX_512bit ? VM_Version::supports_evex() : 0)), "");
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InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
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int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
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emit_int8((unsigned char)0xF5);
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emit_int8((unsigned char)(0xC0 | encode));
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}
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void Assembler::evpdpwssd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
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assert(VM_Version::supports_evex(), "");
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assert(VM_Version::supports_vnni(), "must support vnni");
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InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
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attributes.set_is_evex_instruction();
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int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
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emit_int8(0x52);
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emit_int8((unsigned char)(0xC0 | encode));
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}
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// generic
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void Assembler::pop(Register dst) {
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int encode = prefix_and_encode(dst->encoding());
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