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6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
There is very much duplicated code in vm_version_x86_{32,64}.{cpp,hpp}. Refactoring these would help maintainability.
Reviewed-by: kvn, never
This commit is contained in:
Christian Thalinger
parent
dc3008a513
commit
0723dab28b
7 changed files with 126 additions and 927 deletions
514
hotspot/src/cpu/x86/vm/vm_version_x86.cpp
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514
hotspot/src/cpu/x86/vm/vm_version_x86.cpp
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/*
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* Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
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* CA 95054 USA or visit www.sun.com if you need additional information or
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* have any questions.
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*
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*/
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# include "incls/_precompiled.incl"
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# include "incls/_vm_version_x86.cpp.incl"
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int VM_Version::_cpu;
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int VM_Version::_model;
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int VM_Version::_stepping;
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int VM_Version::_cpuFeatures;
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const char* VM_Version::_features_str = "";
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VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
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static BufferBlob* stub_blob;
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static const int stub_size = 300;
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extern "C" {
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typedef void (*getPsrInfo_stub_t)(void*);
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}
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static getPsrInfo_stub_t getPsrInfo_stub = NULL;
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class VM_Version_StubGenerator: public StubCodeGenerator {
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public:
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VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
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address generate_getPsrInfo() {
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// Flags to test CPU type.
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const uint32_t EFL_AC = 0x40000;
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const uint32_t EFL_ID = 0x200000;
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// Values for when we don't have a CPUID instruction.
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const int CPU_FAMILY_SHIFT = 8;
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const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT);
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const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT);
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Label detect_486, cpu486, detect_586, std_cpuid1;
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Label ext_cpuid1, ext_cpuid5, done;
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StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub");
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# define __ _masm->
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address start = __ pc();
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//
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// void getPsrInfo(VM_Version::CpuidInfo* cpuid_info);
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//
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// LP64: rcx and rdx are first and second argument registers on windows
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__ push(rbp);
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#ifdef _LP64
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__ mov(rbp, c_rarg0); // cpuid_info address
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#else
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__ movptr(rbp, Address(rsp, 8)); // cpuid_info address
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#endif
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__ push(rbx);
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__ push(rsi);
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__ pushf(); // preserve rbx, and flags
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__ pop(rax);
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__ push(rax);
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__ mov(rcx, rax);
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//
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// if we are unable to change the AC flag, we have a 386
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//
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__ xorl(rax, EFL_AC);
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__ push(rax);
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__ popf();
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__ pushf();
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__ pop(rax);
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__ cmpptr(rax, rcx);
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__ jccb(Assembler::notEqual, detect_486);
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__ movl(rax, CPU_FAMILY_386);
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__ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
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__ jmp(done);
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//
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// If we are unable to change the ID flag, we have a 486 which does
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// not support the "cpuid" instruction.
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//
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__ bind(detect_486);
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__ mov(rax, rcx);
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__ xorl(rax, EFL_ID);
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__ push(rax);
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__ popf();
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__ pushf();
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__ pop(rax);
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__ cmpptr(rcx, rax);
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__ jccb(Assembler::notEqual, detect_586);
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__ bind(cpu486);
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__ movl(rax, CPU_FAMILY_486);
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__ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
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__ jmp(done);
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//
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// At this point, we have a chip which supports the "cpuid" instruction
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//
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__ bind(detect_586);
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__ xorl(rax, rax);
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__ cpuid();
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__ orl(rax, rax);
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__ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input
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// value of at least 1, we give up and
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// assume a 486
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__ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
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__ movl(Address(rsi, 0), rax);
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__ movl(Address(rsi, 4), rbx);
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__ movl(Address(rsi, 8), rcx);
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__ movl(Address(rsi,12), rdx);
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__ cmpl(rax, 3); // Is cpuid(0x4) supported?
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__ jccb(Assembler::belowEqual, std_cpuid1);
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//
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// cpuid(0x4) Deterministic cache params
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//
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__ movl(rax, 4);
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__ xorl(rcx, rcx); // L1 cache
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__ cpuid();
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__ push(rax);
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__ andl(rax, 0x1f); // Determine if valid cache parameters used
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__ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache
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__ pop(rax);
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__ jccb(Assembler::equal, std_cpuid1);
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__ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
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__ movl(Address(rsi, 0), rax);
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__ movl(Address(rsi, 4), rbx);
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__ movl(Address(rsi, 8), rcx);
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__ movl(Address(rsi,12), rdx);
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//
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// Standard cpuid(0x1)
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//
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__ bind(std_cpuid1);
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__ movl(rax, 1);
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__ cpuid();
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__ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
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__ movl(Address(rsi, 0), rax);
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__ movl(Address(rsi, 4), rbx);
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__ movl(Address(rsi, 8), rcx);
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__ movl(Address(rsi,12), rdx);
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__ movl(rax, 0x80000000);
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__ cpuid();
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__ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported?
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__ jcc(Assembler::belowEqual, done);
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__ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported?
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__ jccb(Assembler::belowEqual, ext_cpuid1);
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__ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported?
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__ jccb(Assembler::belowEqual, ext_cpuid5);
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//
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// Extended cpuid(0x80000008)
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//
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__ movl(rax, 0x80000008);
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__ cpuid();
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__ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
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__ movl(Address(rsi, 0), rax);
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__ movl(Address(rsi, 4), rbx);
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__ movl(Address(rsi, 8), rcx);
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__ movl(Address(rsi,12), rdx);
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//
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// Extended cpuid(0x80000005)
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//
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__ bind(ext_cpuid5);
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__ movl(rax, 0x80000005);
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__ cpuid();
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__ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
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__ movl(Address(rsi, 0), rax);
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__ movl(Address(rsi, 4), rbx);
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__ movl(Address(rsi, 8), rcx);
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__ movl(Address(rsi,12), rdx);
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//
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// Extended cpuid(0x80000001)
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//
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__ bind(ext_cpuid1);
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__ movl(rax, 0x80000001);
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__ cpuid();
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__ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
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__ movl(Address(rsi, 0), rax);
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__ movl(Address(rsi, 4), rbx);
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__ movl(Address(rsi, 8), rcx);
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__ movl(Address(rsi,12), rdx);
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//
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// return
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//
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__ bind(done);
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__ popf();
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__ pop(rsi);
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__ pop(rbx);
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__ pop(rbp);
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__ ret(0);
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# undef __
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return start;
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};
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};
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void VM_Version::get_processor_features() {
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_cpu = 4; // 486 by default
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_model = 0;
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_stepping = 0;
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_cpuFeatures = 0;
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_logical_processors_per_package = 1;
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if (!Use486InstrsOnly) {
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// Get raw processor info
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getPsrInfo_stub(&_cpuid_info);
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assert_is_initialized();
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_cpu = extended_cpu_family();
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_model = extended_cpu_model();
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_stepping = cpu_stepping();
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if (cpu_family() > 4) { // it supports CPUID
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_cpuFeatures = feature_flags();
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// Logical processors are only available on P4s and above,
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// and only if hyperthreading is available.
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_logical_processors_per_package = logical_processor_count();
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}
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}
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_supports_cx8 = supports_cmpxchg8();
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#ifdef _LP64
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// OS should support SSE for x64 and hardware should support at least SSE2.
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if (!VM_Version::supports_sse2()) {
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vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
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}
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#endif
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// If the OS doesn't support SSE, we can't use this feature even if the HW does
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if (!os::supports_sse())
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_cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2);
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if (UseSSE < 4) {
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_cpuFeatures &= ~CPU_SSE4_1;
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_cpuFeatures &= ~CPU_SSE4_2;
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}
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if (UseSSE < 3) {
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_cpuFeatures &= ~CPU_SSE3;
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_cpuFeatures &= ~CPU_SSSE3;
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_cpuFeatures &= ~CPU_SSE4A;
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}
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if (UseSSE < 2)
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_cpuFeatures &= ~CPU_SSE2;
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if (UseSSE < 1)
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_cpuFeatures &= ~CPU_SSE;
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if (logical_processors_per_package() == 1) {
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// HT processor could be installed on a system which doesn't support HT.
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_cpuFeatures &= ~CPU_HT;
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}
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char buf[256];
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jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
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cores_per_cpu(), threads_per_core(),
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cpu_family(), _model, _stepping,
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(supports_cmov() ? ", cmov" : ""),
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(supports_cmpxchg8() ? ", cx8" : ""),
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(supports_fxsr() ? ", fxsr" : ""),
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(supports_mmx() ? ", mmx" : ""),
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(supports_sse() ? ", sse" : ""),
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(supports_sse2() ? ", sse2" : ""),
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(supports_sse3() ? ", sse3" : ""),
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(supports_ssse3()? ", ssse3": ""),
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(supports_sse4_1() ? ", sse4.1" : ""),
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(supports_sse4_2() ? ", sse4.2" : ""),
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(supports_mmx_ext() ? ", mmxext" : ""),
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(supports_3dnow() ? ", 3dnow" : ""),
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(supports_3dnow2() ? ", 3dnowext" : ""),
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(supports_sse4a() ? ", sse4a": ""),
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(supports_ht() ? ", ht": ""));
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_features_str = strdup(buf);
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// UseSSE is set to the smaller of what hardware supports and what
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// the command line requires. I.e., you cannot set UseSSE to 2 on
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// older Pentiums which do not support it.
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if( UseSSE > 4 ) UseSSE=4;
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if( UseSSE < 0 ) UseSSE=0;
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if( !supports_sse4_1() ) // Drop to 3 if no SSE4 support
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UseSSE = MIN2((intx)3,UseSSE);
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if( !supports_sse3() ) // Drop to 2 if no SSE3 support
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UseSSE = MIN2((intx)2,UseSSE);
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if( !supports_sse2() ) // Drop to 1 if no SSE2 support
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UseSSE = MIN2((intx)1,UseSSE);
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if( !supports_sse () ) // Drop to 0 if no SSE support
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UseSSE = 0;
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// On new cpus instructions which update whole XMM register should be used
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// to prevent partial register stall due to dependencies on high half.
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//
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// UseXmmLoadAndClearUpper == true --> movsd(xmm, mem)
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// UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
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// UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm).
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// UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm).
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if( is_amd() ) { // AMD cpus specific settings
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if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
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// Use it on new AMD cpus starting from Opteron.
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UseAddressNop = true;
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}
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if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) {
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// Use it on new AMD cpus starting from Opteron.
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UseNewLongLShift = true;
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}
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if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
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if( supports_sse4a() ) {
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UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
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} else {
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UseXmmLoadAndClearUpper = false;
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}
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}
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if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
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if( supports_sse4a() ) {
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UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
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} else {
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UseXmmRegToRegMoveAll = false;
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}
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}
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if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
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if( supports_sse4a() ) {
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UseXmmI2F = true;
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} else {
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UseXmmI2F = false;
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}
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}
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if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
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if( supports_sse4a() ) {
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UseXmmI2D = true;
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} else {
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UseXmmI2D = false;
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}
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}
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}
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if( is_intel() ) { // Intel cpus specific settings
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if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
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UseStoreImmI16 = false; // don't use it on Intel cpus
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}
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if( cpu_family() == 6 || cpu_family() == 15 ) {
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if( FLAG_IS_DEFAULT(UseAddressNop) ) {
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// Use it on all Intel cpus starting from PentiumPro
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UseAddressNop = true;
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}
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}
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if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
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UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
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}
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if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
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if( supports_sse3() ) {
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UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
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} else {
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UseXmmRegToRegMoveAll = false;
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}
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}
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if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
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#ifdef COMPILER2
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if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
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// For new Intel cpus do the next optimization:
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// don't align the beginning of a loop if there are enough instructions
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// left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
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// in current fetch line (OptoLoopAlignment) or the padding
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// is big (> MaxLoopPad).
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// Set MaxLoopPad to 11 for new Intel cpus to reduce number of
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// generated NOP instructions. 11 is the largest size of one
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// address NOP instruction '0F 1F' (see Assembler::nop(i)).
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MaxLoopPad = 11;
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}
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#endif // COMPILER2
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if( FLAG_IS_DEFAULT(UseXMMForArrayCopy) ) {
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UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
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}
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if( supports_sse4_2() && supports_ht() ) { // Newest Intel cpus
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if( FLAG_IS_DEFAULT(UseUnalignedLoadStores) && UseXMMForArrayCopy ) {
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UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
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}
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}
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}
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}
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assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value");
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assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value");
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// set valid Prefetch instruction
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if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0;
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if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3;
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if( ReadPrefetchInstr == 3 && !supports_3dnow() ) ReadPrefetchInstr = 0;
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if( !supports_sse() && supports_3dnow() ) ReadPrefetchInstr = 3;
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|
||||
if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
|
||||
if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3;
|
||||
if( AllocatePrefetchInstr == 3 && !supports_3dnow() ) AllocatePrefetchInstr=0;
|
||||
if( !supports_sse() && supports_3dnow() ) AllocatePrefetchInstr = 3;
|
||||
|
||||
// Allocation prefetch settings
|
||||
intx cache_line_size = L1_data_cache_line_size();
|
||||
if( cache_line_size > AllocatePrefetchStepSize )
|
||||
AllocatePrefetchStepSize = cache_line_size;
|
||||
if( FLAG_IS_DEFAULT(AllocatePrefetchLines) )
|
||||
AllocatePrefetchLines = 3; // Optimistic value
|
||||
assert(AllocatePrefetchLines > 0, "invalid value");
|
||||
if( AllocatePrefetchLines < 1 ) // set valid value in product VM
|
||||
AllocatePrefetchLines = 1; // Conservative value
|
||||
|
||||
AllocatePrefetchDistance = allocate_prefetch_distance();
|
||||
AllocatePrefetchStyle = allocate_prefetch_style();
|
||||
|
||||
if( AllocatePrefetchStyle == 2 && is_intel() &&
|
||||
cpu_family() == 6 && supports_sse3() ) { // watermark prefetching on Core
|
||||
#ifdef _LP64
|
||||
AllocatePrefetchDistance = 384;
|
||||
#else
|
||||
AllocatePrefetchDistance = 320;
|
||||
#endif
|
||||
}
|
||||
assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value");
|
||||
|
||||
#ifdef _LP64
|
||||
// Prefetch settings
|
||||
PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
|
||||
PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
|
||||
PrefetchFieldsAhead = prefetch_fields_ahead();
|
||||
#endif
|
||||
|
||||
#ifndef PRODUCT
|
||||
if (PrintMiscellaneous && Verbose) {
|
||||
tty->print_cr("Logical CPUs per core: %u",
|
||||
logical_processors_per_package());
|
||||
tty->print_cr("UseSSE=%d",UseSSE);
|
||||
tty->print("Allocation: ");
|
||||
if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow()) {
|
||||
tty->print_cr("no prefetching");
|
||||
} else {
|
||||
if (UseSSE == 0 && supports_3dnow()) {
|
||||
tty->print("PREFETCHW");
|
||||
} else if (UseSSE >= 1) {
|
||||
if (AllocatePrefetchInstr == 0) {
|
||||
tty->print("PREFETCHNTA");
|
||||
} else if (AllocatePrefetchInstr == 1) {
|
||||
tty->print("PREFETCHT0");
|
||||
} else if (AllocatePrefetchInstr == 2) {
|
||||
tty->print("PREFETCHT2");
|
||||
} else if (AllocatePrefetchInstr == 3) {
|
||||
tty->print("PREFETCHW");
|
||||
}
|
||||
}
|
||||
if (AllocatePrefetchLines > 1) {
|
||||
tty->print_cr(" %d, %d lines with step %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize);
|
||||
} else {
|
||||
tty->print_cr(" %d, one line", AllocatePrefetchDistance);
|
||||
}
|
||||
}
|
||||
|
||||
if (PrefetchCopyIntervalInBytes > 0) {
|
||||
tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes);
|
||||
}
|
||||
if (PrefetchScanIntervalInBytes > 0) {
|
||||
tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes);
|
||||
}
|
||||
if (PrefetchFieldsAhead > 0) {
|
||||
tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead);
|
||||
}
|
||||
}
|
||||
#endif // !PRODUCT
|
||||
}
|
||||
|
||||
void VM_Version::initialize() {
|
||||
ResourceMark rm;
|
||||
// Making this stub must be FIRST use of assembler
|
||||
|
||||
stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size);
|
||||
if (stub_blob == NULL) {
|
||||
vm_exit_during_initialization("Unable to allocate getPsrInfo_stub");
|
||||
}
|
||||
CodeBuffer c(stub_blob->instructions_begin(),
|
||||
stub_blob->instructions_size());
|
||||
VM_Version_StubGenerator g(&c);
|
||||
getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t,
|
||||
g.generate_getPsrInfo());
|
||||
|
||||
get_processor_features();
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue