8138583: aarch64: add support for vectorizing fabs/fneg

Reviewed-by: aph, roland
This commit is contained in:
Felix Yang 2015-09-30 04:35:39 -04:00 committed by Ed Nevill
parent 1380ff2e93
commit 12cba200a3
9 changed files with 340 additions and 2 deletions

View file

@ -1858,8 +1858,8 @@ void SuperWord::output() {
vn = VectorNode::make(opc, in1, in2, vlen, velt_basic_type(n));
vlen_in_bytes = vn->as_Vector()->length_in_bytes();
}
} else if (opc == Op_SqrtD) {
// Promote operand to vector (Sqrt is a 2 address instruction)
} else if (opc == Op_SqrtD || opc == Op_AbsF || opc == Op_AbsD || opc == Op_NegF || opc == Op_NegD) {
// Promote operand to vector (Sqrt/Abs/Neg are 2 address instructions)
Node* in = vector_opd(p, 1);
vn = VectorNode::make(opc, in, NULL, vlen, velt_basic_type(n));
vlen_in_bytes = vn->as_Vector()->length_in_bytes();