archive/jdk
1
0
Fork 0
mirror of https://github.com/openjdk/jdk.git synced 2025-09-20 11:04:34 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions

8076968: PICL based initialization of L2 cache line size on some SPARC systems is incorrect

Browse source 
Chcek both l2-dcache-line-size and l2-cache-line-size properties to determine the size of the line

Reviewed-by: kvn
This commit is contained in:
Igor Veresov 2015-04-06 20:20:17 -07:00
parent b72eca85b5
commit 1b5090da9e
3 changed files with 26 additions and 13 deletions
Download patch file Download diff file Expand all files Collapse all files

4
hotspot/src/cpu/sparc/vm/vm_version_sparc.cpp
View file

@ -32,7 +32,7 @@
int VM_Version::_features = VM_Version::unknown_m;
const char* VM_Version::_features_str = "";
unsigned int VM_Version::_L2_cache_line_size = 0;
unsigned int VM_Version::_L2_data_cache_line_size = 0;
void VM_Version::initialize() {
_features = determine_features();
@ -366,7 +366,7 @@ void VM_Version::initialize() {
#ifndef PRODUCT
if (PrintMiscellaneous && Verbose) {
tty->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
tty->print_cr("L2 cache line size: %u", L2_cache_line_size());
tty->print_cr("L2 data cache line size: %u", L2_data_cache_line_size());
tty->print("Allocation");
if (AllocatePrefetchStyle <= 0) {
tty->print_cr(": no prefetching");