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8302908: RISC-V: Support masked vector arithmetic instructions for Vector API

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Co-authored-by: zifeihan <caogui@iscas.ac.cn>
Reviewed-by: fyang, fjiang, yzhu
This commit is contained in:
Dingli Zhang 2023-04-26 02:24:49 +00:00 • committed by Fei Yang
parent adf62febe6
commit 1c1a73f715
7 changed files with 993 additions and 138 deletions
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41
src/hotspot/cpu/riscv/macroAssembler_riscv.hpp
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@ -1264,7 +1264,7 @@ public:
vmnand_mm(vd, vs, vs);
}
inline void vncvt_x_x_w(VectorRegister vd, VectorRegister vs, VectorMask vm) {
inline void vncvt_x_x_w(VectorRegister vd, VectorRegister vs, VectorMask vm = unmasked) {
vnsrl_wx(vd, vs, x0, vm);
}
@ -1276,6 +1276,45 @@ public:
vfsgnjn_vv(vd, vs, vs);
}
inline void vmsgt_vv(VectorRegister vd, VectorRegister vs2, VectorRegister vs1, VectorMask vm = unmasked) {
vmslt_vv(vd, vs1, vs2, vm);
}
inline void vmsgtu_vv(VectorRegister vd, VectorRegister vs2, VectorRegister vs1, VectorMask vm = unmasked) {
vmsltu_vv(vd, vs1, vs2, vm);
}
inline void vmsge_vv(VectorRegister vd, VectorRegister vs2, VectorRegister vs1, VectorMask vm = unmasked) {
vmsle_vv(vd, vs1, vs2, vm);
}
inline void vmsgeu_vv(VectorRegister vd, VectorRegister vs2, VectorRegister vs1, VectorMask vm = unmasked) {
vmsleu_vv(vd, vs1, vs2, vm);
}
inline void vmfgt_vv(VectorRegister vd, VectorRegister vs2, VectorRegister vs1, VectorMask vm = unmasked) {
vmflt_vv(vd, vs1, vs2, vm);
}
inline void vmfge_vv(VectorRegister vd, VectorRegister vs2, VectorRegister vs1, VectorMask vm = unmasked) {
vmfle_vv(vd, vs1, vs2, vm);
}
// Copy mask register
inline void vmmv_m(VectorRegister vd, VectorRegister vs) {
vmand_mm(vd, vs, vs);
}
// Clear mask register
inline void vmclr_m(VectorRegister vd) {
vmxor_mm(vd, vd, vd);
}
// Set mask register
inline void vmset_m(VectorRegister vd) {
vmxnor_mm(vd, vd, vd);
}
static const int zero_words_block_size;
void cast_primitive_type(BasicType type, Register Rt) {