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8239008: C2: Simplify Replicate support for sub-word types on x86
Reviewed-by: kvn
This commit is contained in:
Vladimir Ivanov
parent
072cfd2e48
commit
1dcd3d2c50
2 changed files with 49 additions and 158 deletions
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@ -7160,7 +7160,7 @@ void Assembler::evbroadcasti64x2(XMMRegister dst, Address src, int vector_len) {
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// duplicate single precision data from src into programmed locations in dest : requires AVX512VL
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void Assembler::vbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) {
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assert(VM_Version::supports_avx(), "");
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assert(VM_Version::supports_avx2(), "");
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InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
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int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
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emit_int8(0x18);
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@ -7181,7 +7181,8 @@ void Assembler::vbroadcastss(XMMRegister dst, Address src, int vector_len) {
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// duplicate double precision data from src into programmed locations in dest : requires AVX512VL
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void Assembler::vbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) {
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assert(VM_Version::supports_avx(), "");
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assert(VM_Version::supports_avx2(), "");
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assert(vector_len == AVX_256bit || vector_len == AVX_512bit, "");
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InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
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attributes.set_rex_vex_w_reverted();
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int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
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@ -7191,6 +7192,7 @@ void Assembler::vbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) {
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void Assembler::vbroadcastsd(XMMRegister dst, Address src, int vector_len) {
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assert(VM_Version::supports_avx(), "");
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assert(vector_len == AVX_256bit || vector_len == AVX_512bit, "");
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assert(dst != xnoreg, "sanity");
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InstructionMark im(this);
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InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
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@ -3124,14 +3124,12 @@ instruct storeV(memory mem, vec src) %{
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// Replicate byte scalar to be vector
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instruct ReplB_reg(vec dst, rRegI src) %{
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predicate((n->as_Vector()->length() <= 32) ||
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(n->as_Vector()->length() == 64 && VM_Version::supports_avx512bw())); // AVX512BW for 512bit byte instructions
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match(Set dst (ReplicateB src));
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format %{ "replicateB $dst,$src" %}
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ins_encode %{
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uint vlen = vector_length(this);
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if (vlen == 64 || VM_Version::supports_avx512vlbw()) { // AVX512VL for <512bit operands
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assert(VM_Version::supports_avx512bw(), "required");
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assert(VM_Version::supports_avx512bw(), "required"); // 512-bit byte vectors assume AVX512BW
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int vlen_enc = vector_length_encoding(this);
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__ evpbroadcastb($dst$$XMMRegister, $src$$Register, vlen_enc);
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} else {
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@ -3141,7 +3139,7 @@ instruct ReplB_reg(vec dst, rRegI src) %{
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if (vlen >= 16) {
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__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
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if (vlen >= 32) {
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assert(vlen == 32, "sanity"); // vlen == 64 && !AVX512BW is covered by ReplB_reg_leg
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assert(vlen == 32, "sanity");
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__ vinserti128_high($dst$$XMMRegister, $dst$$XMMRegister);
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}
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}
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@ -3150,29 +3148,11 @@ instruct ReplB_reg(vec dst, rRegI src) %{
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ins_pipe( pipe_slow );
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%}
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instruct ReplB_reg_leg(legVec dst, rRegI src) %{
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predicate(n->as_Vector()->length() == 64 && !VM_Version::supports_avx512bw()); // AVX512BW for 512bit byte instructions
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match(Set dst (ReplicateB src));
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format %{ "replicateB $dst,$src" %}
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ins_encode %{
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assert(UseAVX > 2, "required");
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__ movdl($dst$$XMMRegister, $src$$Register);
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__ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister);
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__ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
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__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
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__ vinserti128_high($dst$$XMMRegister, $dst$$XMMRegister);
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__ vinserti64x4($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, 0x1);
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%}
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ins_pipe( pipe_slow );
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%}
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instruct ReplB_mem(vec dst, memory mem) %{
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predicate((n->as_Vector()->length() <= 32 && VM_Version::supports_avx512vlbw()) || // AVX512VL for <512bit operands
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(n->as_Vector()->length() == 64 && VM_Version::supports_avx512bw())); // AVX512BW for 512bit byte instructions
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predicate(VM_Version::supports_avx2());
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match(Set dst (ReplicateB (LoadB mem)));
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format %{ "replicateB $dst,$mem" %}
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ins_encode %{
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assert(UseAVX > 2, "required");
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int vector_len = vector_length_encoding(this);
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__ vpbroadcastb($dst$$XMMRegister, $mem$$Address, vector_len);
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%}
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@ -3180,8 +3160,6 @@ instruct ReplB_mem(vec dst, memory mem) %{
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%}
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instruct ReplB_imm(vec dst, immI con) %{
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predicate((n->as_Vector()->length() <= 32) ||
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(n->as_Vector()->length() == 64 && VM_Version::supports_avx512bw())); // AVX512BW for 512bit byte instructions
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match(Set dst (ReplicateB con));
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format %{ "replicateB $dst,$con" %}
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ins_encode %{
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@ -3192,31 +3170,15 @@ instruct ReplB_imm(vec dst, immI con) %{
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} else {
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__ movq($dst$$XMMRegister, const_addr);
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if (vlen >= 16) {
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if (vlen == 64 || VM_Version::supports_avx512vlbw()) { // AVX512VL for <512bit operands
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if (VM_Version::supports_avx2()) {
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int vlen_enc = vector_length_encoding(this);
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__ vpbroadcastb($dst$$XMMRegister, $dst$$XMMRegister, vlen_enc);
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__ vpbroadcastq($dst$$XMMRegister, $dst$$XMMRegister, vlen_enc);
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} else {
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assert(vlen == 16, "sanity");
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__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
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if (vlen >= 32) {
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assert(vlen == 32, "sanity");// vlen == 64 && !AVX512BW is covered by ReplB_imm_leg
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__ vinserti128_high($dst$$XMMRegister, $dst$$XMMRegister);
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}
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}
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}
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}
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%}
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ins_pipe( pipe_slow );
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%}
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instruct ReplB_imm_leg(legVec dst, immI con) %{
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predicate(n->as_Vector()->length() == 64 && !VM_Version::supports_avx512bw());
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match(Set dst (ReplicateB con));
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format %{ "replicateB $dst,$con" %}
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ins_encode %{
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__ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 1)));
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__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
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__ vinserti128_high($dst$$XMMRegister, $dst$$XMMRegister);
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__ vinserti64x4($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, 0x1);
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%}
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ins_pipe( pipe_slow );
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%}
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@ -3241,14 +3203,12 @@ instruct ReplB_zero(vec dst, immI0 zero) %{
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// ====================ReplicateS=======================================
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instruct ReplS_reg(vec dst, rRegI src) %{
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predicate((n->as_Vector()->length() <= 16) ||
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(n->as_Vector()->length() == 32 && VM_Version::supports_avx512bw())); // AVX512BW for 512bit instructions on shorts
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match(Set dst (ReplicateS src));
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format %{ "replicateS $dst,$src" %}
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ins_encode %{
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uint vlen = vector_length(this);
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if (vlen == 32 || VM_Version::supports_avx512vlbw()) { // AVX512VL for <512bit operands
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assert(VM_Version::supports_avx512bw(), "required");
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assert(VM_Version::supports_avx512bw(), "required"); // 512-bit short vectors assume AVX512BW
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int vlen_enc = vector_length_encoding(this);
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__ evpbroadcastw($dst$$XMMRegister, $src$$Register, vlen_enc);
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} else {
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@ -3257,7 +3217,7 @@ instruct ReplS_reg(vec dst, rRegI src) %{
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if (vlen >= 8) {
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__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
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if (vlen >= 16) {
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assert(vlen == 16, "sanity"); // vlen == 32 && !AVX512BW is covered by ReplS_reg_leg
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assert(vlen == 16, "sanity");
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__ vinserti128_high($dst$$XMMRegister, $dst$$XMMRegister);
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}
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}
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@ -3266,81 +3226,43 @@ instruct ReplS_reg(vec dst, rRegI src) %{
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ins_pipe( pipe_slow );
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%}
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instruct ReplS_reg_leg(legVec dst, rRegI src) %{
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predicate(n->as_Vector()->length() == 32 && !VM_Version::supports_avx512bw());
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match(Set dst (ReplicateS src));
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format %{ "replicateS $dst,$src" %}
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ins_encode %{
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__ movdl($dst$$XMMRegister, $src$$Register);
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__ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00);
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__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
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__ vinserti128_high($dst$$XMMRegister, $dst$$XMMRegister);
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__ vinserti64x4($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, 0x1);
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%}
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ins_pipe( pipe_slow );
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%}
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instruct ReplS_mem(vec dst, memory mem) %{
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predicate((n->as_Vector()->length() >= 4 &&
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n->as_Vector()->length() <= 16 && VM_Version::supports_avx()) ||
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(n->as_Vector()->length() == 32 && VM_Version::supports_avx512bw())); // AVX512BW for 512bit instructions on shorts
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predicate(VM_Version::supports_avx()); // use VEX-encoded pshuflw to relax 16-byte alignment restriction on the source
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match(Set dst (ReplicateS (LoadS mem)));
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format %{ "replicateS $dst,$mem" %}
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ins_encode %{
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uint vlen = vector_length(this);
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if (vlen == 32 || VM_Version::supports_avx512vlbw()) { // AVX512VL for <512bit operands
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assert(VM_Version::supports_avx512bw(), "required");
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if (VM_Version::supports_avx2()) {
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int vlen_enc = vector_length_encoding(this);
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__ vpbroadcastw($dst$$XMMRegister, $mem$$Address, vlen_enc);
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} else {
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__ pshuflw($dst$$XMMRegister, $mem$$Address, 0x00);
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if (vlen >= 8) {
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assert(vlen == 8, "sanity");
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__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
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if (vlen >= 16) {
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assert(vlen == 16, "sanity"); // vlen == 32 && !AVX512BW is covered by ReplS_mem_leg
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__ vinserti128_high($dst$$XMMRegister, $dst$$XMMRegister);
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}
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}
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}
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%}
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ins_pipe( pipe_slow );
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%}
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instruct ReplS_mem_leg(legVec dst, memory mem) %{
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predicate(n->as_Vector()->length() == 32 && !VM_Version::supports_avx512bw());
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match(Set dst (ReplicateS (LoadS mem)));
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format %{ "replicateS $dst,$mem" %}
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ins_encode %{
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__ pshuflw($dst$$XMMRegister, $mem$$Address, 0x00);
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__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
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__ vinserti128_high($dst$$XMMRegister, $dst$$XMMRegister);
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__ vinserti64x4($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, 0x1);
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%}
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ins_pipe( pipe_slow );
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%}
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instruct ReplS_imm(vec dst, immI con) %{
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predicate((n->as_Vector()->length() <= 16) ||
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(n->as_Vector()->length() == 32 && VM_Version::supports_avx512bw())); // AVX512BW for 512bit instructions on shorts
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match(Set dst (ReplicateS con));
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format %{ "replicateS $dst,$con" %}
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ins_encode %{
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uint vlen = vector_length(this);
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InternalAddress constaddr = $constantaddress(replicate8_imm($con$$constant, 2));
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InternalAddress const_addr = $constantaddress(replicate8_imm($con$$constant, 2));
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if (vlen == 2) {
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__ movdl($dst$$XMMRegister, constaddr);
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__ movdl($dst$$XMMRegister, const_addr);
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} else {
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__ movq($dst$$XMMRegister, constaddr);
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if (vlen == 32 || VM_Version::supports_avx512vlbw() ) { // AVX512VL for <512bit operands
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assert(VM_Version::supports_avx512bw(), "required");
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__ movq($dst$$XMMRegister, const_addr);
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if (vlen >= 8) {
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if (VM_Version::supports_avx2()) {
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int vlen_enc = vector_length_encoding(this);
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__ vpbroadcastw($dst$$XMMRegister, $dst$$XMMRegister, vlen_enc);
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} else {
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__ movq($dst$$XMMRegister, constaddr);
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assert(vlen == 8, "sanity");
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__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
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if (vlen >= 16) {
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assert(vlen == 16, "sanity"); // vlen == 32 && !AVX512BW is covered by ReplS_imm_leg
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__ vinserti128_high($dst$$XMMRegister, $dst$$XMMRegister);
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}
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}
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}
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@ -3348,19 +3270,6 @@ instruct ReplS_imm(vec dst, immI con) %{
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ins_pipe( fpu_reg_reg );
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%}
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instruct ReplS_imm_leg(legVec dst, immI con) %{
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predicate(n->as_Vector()->length() == 32 && !VM_Version::supports_avx512bw());
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match(Set dst (ReplicateS con));
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format %{ "replicateS $dst,$con" %}
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ins_encode %{
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__ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 2)));
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__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
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__ vinserti128_high($dst$$XMMRegister, $dst$$XMMRegister);
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__ vinserti64x4($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, 0x1);
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%}
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ins_pipe( pipe_slow );
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%}
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instruct ReplS_zero(vec dst, immI0 zero) %{
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match(Set dst (ReplicateS zero));
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format %{ "replicateS $dst,$zero" %}
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@ -3406,13 +3315,10 @@ instruct ReplI_mem(vec dst, memory mem) %{
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uint vlen = vector_length(this);
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if (vlen <= 4) {
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__ pshufd($dst$$XMMRegister, $mem$$Address, 0x00);
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} else if (vlen == 16 || VM_Version::supports_avx512vl()) { // AVX512VL for <512bit operands
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} else {
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assert(VM_Version::supports_avx2(), "sanity");
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int vector_len = vector_length_encoding(this);
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__ vpbroadcastd($dst$$XMMRegister, $mem$$Address, vector_len);
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} else {
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assert(vlen == 8, "sanity");
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__ pshufd($dst$$XMMRegister, $mem$$Address, 0x00);
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__ vinserti128_high($dst$$XMMRegister, $dst$$XMMRegister);
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}
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%}
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ins_pipe( pipe_slow );
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@ -3423,20 +3329,17 @@ instruct ReplI_imm(vec dst, immI con) %{
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format %{ "replicateI $dst,$con" %}
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ins_encode %{
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uint vlen = vector_length(this);
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InternalAddress constaddr = $constantaddress(replicate8_imm($con$$constant, 4));
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if (vlen == 2) {
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__ movq($dst$$XMMRegister, constaddr);
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} else if (vlen == 16 || VM_Version::supports_avx512vl()) { // AVX512VL for <512bit operands
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int vector_len = vector_length_encoding(this);
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__ movq($dst$$XMMRegister, constaddr);
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__ vpbroadcastd($dst$$XMMRegister, $dst$$XMMRegister, vector_len);
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} else {
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__ movq($dst$$XMMRegister, constaddr);
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InternalAddress const_addr = $constantaddress(replicate8_imm($con$$constant, 4));
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if (vlen <= 4) {
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__ movq($dst$$XMMRegister, const_addr);
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if (vlen == 4) {
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__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
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if (vlen >= 8) {
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assert(vlen == 8, "sanity");
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__ vinserti128_high($dst$$XMMRegister, $dst$$XMMRegister);
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}
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} else {
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assert(VM_Version::supports_avx2(), "sanity");
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int vector_len = vector_length_encoding(this);
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__ movq($dst$$XMMRegister, const_addr);
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__ vpbroadcastd($dst$$XMMRegister, $dst$$XMMRegister, vector_len);
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}
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%}
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ins_pipe( pipe_slow );
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@ -3546,14 +3449,10 @@ instruct ReplL_mem(vec dst, memory mem) %{
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if (vlen == 2) {
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__ movq($dst$$XMMRegister, $mem$$Address);
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__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
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} else if (vlen == 8 || VM_Version::supports_avx512vl()) { // AVX512VL for <512bit operands
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} else {
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assert(VM_Version::supports_avx2(), "sanity");
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int vlen_enc = vector_length_encoding(this);
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__ vpbroadcastq($dst$$XMMRegister, $mem$$Address, vlen_enc);
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} else {
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assert(vlen == 4, "sanity");
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__ movq($dst$$XMMRegister, $mem$$Address);
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__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
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__ vinserti128_high($dst$$XMMRegister, $dst$$XMMRegister);
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}
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%}
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ins_pipe( pipe_slow );
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@ -3569,15 +3468,11 @@ instruct ReplL_imm(vec dst, immL con) %{
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if (vlen == 2) {
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__ movq($dst$$XMMRegister, const_addr);
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__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
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} else if (vlen == 8 || VM_Version::supports_avx512vl()) { // AVX512VL for <512bit operands
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} else {
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assert(VM_Version::supports_avx2(), "sanity");
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int vlen_enc = vector_length_encoding(this);
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__ movq($dst$$XMMRegister, const_addr);
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__ vpbroadcastq($dst$$XMMRegister, $dst$$XMMRegister, vlen_enc);
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} else {
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assert(vlen == 4, "sanity");
|
||||
__ movq($dst$$XMMRegister, const_addr);
|
||||
__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister);
|
||||
__ vinserti128_high($dst$$XMMRegister, $dst$$XMMRegister);
|
||||
}
|
||||
%}
|
||||
ins_pipe( pipe_slow );
|
||||
|
|
@ -3607,9 +3502,9 @@ instruct ReplF_reg(vec dst, vlRegF src) %{
|
|||
uint vlen = vector_length(this);
|
||||
if (vlen <= 4) {
|
||||
__ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x00);
|
||||
} else if (vlen == 16 || VM_Version::supports_avx512vl()) { // AVX512VL for <512bit operands
|
||||
} else if (VM_Version::supports_avx2()) {
|
||||
int vector_len = vector_length_encoding(this);
|
||||
__ vbroadcastss($dst$$XMMRegister, $src$$XMMRegister, vector_len);
|
||||
__ vbroadcastss($dst$$XMMRegister, $src$$XMMRegister, vector_len); // reg-to-reg variant requires AVX2
|
||||
} else {
|
||||
assert(vlen == 8, "sanity");
|
||||
__ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x00);
|
||||
|
|
@ -3627,13 +3522,10 @@ instruct ReplF_mem(vec dst, memory mem) %{
|
|||
uint vlen = vector_length(this);
|
||||
if (vlen <= 4) {
|
||||
__ pshufd($dst$$XMMRegister, $mem$$Address, 0x00);
|
||||
} else if (vlen == 16 || VM_Version::supports_avx512vl()) { // AVX512VL for <512bit operands
|
||||
} else {
|
||||
assert(VM_Version::supports_avx(), "sanity");
|
||||
int vector_len = vector_length_encoding(this);
|
||||
__ vbroadcastss($dst$$XMMRegister, $mem$$Address, vector_len);
|
||||
} else {
|
||||
assert(vlen == 8, "sanity");
|
||||
__ pshufd($dst$$XMMRegister, $mem$$Address, 0x00);
|
||||
__ vinsertf128_high($dst$$XMMRegister, $dst$$XMMRegister);
|
||||
}
|
||||
%}
|
||||
ins_pipe( pipe_slow );
|
||||
|
|
@ -3664,9 +3556,9 @@ instruct ReplD_reg(vec dst, vlRegD src) %{
|
|||
uint vlen = vector_length(this);
|
||||
if (vlen == 2) {
|
||||
__ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x44);
|
||||
} else if (vlen == 8 || VM_Version::supports_avx512vl()) { // AVX512VL for <512bit operands
|
||||
} else if (VM_Version::supports_avx2()) {
|
||||
int vector_len = vector_length_encoding(this);
|
||||
__ vbroadcastsd($dst$$XMMRegister, $src$$XMMRegister, vector_len);
|
||||
__ vbroadcastsd($dst$$XMMRegister, $src$$XMMRegister, vector_len); // reg-to-reg variant requires AVX2
|
||||
} else {
|
||||
assert(vlen == 4, "sanity");
|
||||
__ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x44);
|
||||
|
|
@ -3684,13 +3576,10 @@ instruct ReplD_mem(vec dst, memory mem) %{
|
|||
uint vlen = vector_length(this);
|
||||
if (vlen == 2) {
|
||||
__ pshufd($dst$$XMMRegister, $mem$$Address, 0x44);
|
||||
} else if (vlen == 8 || VM_Version::supports_avx512vl()) { // AVX512VL for <512bit operands
|
||||
} else {
|
||||
assert(VM_Version::supports_avx(), "sanity");
|
||||
int vector_len = vector_length_encoding(this);
|
||||
__ vbroadcastsd($dst$$XMMRegister, $mem$$Address, vector_len);
|
||||
} else {
|
||||
assert(vlen == 4, "sanity");
|
||||
__ pshufd($dst$$XMMRegister, $mem$$Address, 0x44);
|
||||
__ vinsertf128_high($dst$$XMMRegister, $dst$$XMMRegister);
|
||||
}
|
||||
%}
|
||||
ins_pipe( pipe_slow );
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue