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7059034: Use movxtod/movdtox on T4
Use new VIS3 mov instructions on T4 for move data between general and float registers. Reviewed-by: never, twisti
This commit is contained in:
Vladimir Kozlov
parent
9120c1e85c
commit
20a26c54cd
4 changed files with 407 additions and 216 deletions
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@ -716,6 +716,8 @@ class Assembler : public AbstractAssembler {
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casa_op3 = 0x3c,
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casxa_op3 = 0x3e,
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mftoi_op3 = 0x36,
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alt_bit_op3 = 0x10,
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cc_bit_op3 = 0x10
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};
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@ -750,7 +752,13 @@ class Assembler : public AbstractAssembler {
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fitod_opf = 0xc8,
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fstod_opf = 0xc9,
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fstoi_opf = 0xd1,
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fdtoi_opf = 0xd2
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fdtoi_opf = 0xd2,
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mdtox_opf = 0x110,
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mstouw_opf = 0x111,
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mstosw_opf = 0x113,
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mxtod_opf = 0x118,
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mwtos_opf = 0x119
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};
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enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7 };
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@ -1061,6 +1069,9 @@ class Assembler : public AbstractAssembler {
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return x & ((1 << 10) - 1);
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}
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// instruction only in VIS3
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static void vis3_only() { assert( VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); }
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// instruction only in v9
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static void v9_only() { assert( VM_Version::v9_instructions_work(), "This instruction only works on SPARC V9"); }
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@ -1247,8 +1258,8 @@ public:
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// pp 159
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void ftox( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w) | fs2(s, w)); }
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void ftoi( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xd0 + w) | fs2(s, w)); }
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void ftox( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(fpop1_op3) | opf(0x80 + w) | fs2(s, w)); }
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void ftoi( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(fpop1_op3) | opf(0xd0 + w) | fs2(s, w)); }
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// pp 160
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@ -1256,8 +1267,8 @@ public:
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// pp 161
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void fxtof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w*4) | fs2(s, w)); }
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void fitof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xc0 + w*4) | fs2(s, w)); }
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void fxtof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w*4) | fs2(s, FloatRegisterImpl::D)); }
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void fitof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xc0 + w*4) | fs2(s, FloatRegisterImpl::S)); }
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// pp 162
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@ -1709,6 +1720,19 @@ public:
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inline void wrasi( Register d) { v9_only(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25)); }
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inline void wrfprs( Register d) { v9_only(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); }
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// VIS3 instructions
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void movstosw( FloatRegister s, Register d ) { vis3_only(); emit_long( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstosw_opf) | fs2(s, FloatRegisterImpl::S)); }
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void movstouw( FloatRegister s, Register d ) { vis3_only(); emit_long( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstouw_opf) | fs2(s, FloatRegisterImpl::S)); }
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void movdtox( FloatRegister s, Register d ) { vis3_only(); emit_long( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mdtox_opf) | fs2(s, FloatRegisterImpl::D)); }
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void movwtos( Register s, FloatRegister d ) { vis3_only(); emit_long( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(mftoi_op3) | opf(mwtos_opf) | rs2(s)); }
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void movxtod( Register s, FloatRegister d ) { vis3_only(); emit_long( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(mftoi_op3) | opf(mxtod_opf) | rs2(s)); }
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// For a given register condition, return the appropriate condition code
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// Condition (the one you would use to get the same effect after "tst" on
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// the target register.)
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@ -425,7 +425,7 @@ reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R
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// but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
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// This class is usable for mis-aligned loads as happen in I2C adapters.
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reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
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R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31 );
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R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
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%}
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//----------DEFINITION BLOCK---------------------------------------------------
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@ -1326,17 +1326,17 @@ uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
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// --------------------------------------
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// Check for float->int copy; requires a trip through memory
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if( src_first_rc == rc_float && dst_first_rc == rc_int ) {
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if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
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int offset = frame::register_save_words*wordSize;
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if( cbuf ) {
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if (cbuf) {
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emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
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impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
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impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
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emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
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}
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#ifndef PRODUCT
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else if( !do_size ) {
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if( size != 0 ) st->print("\n\t");
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else if (!do_size) {
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if (size != 0) st->print("\n\t");
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st->print( "SUB R_SP,16,R_SP\n");
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impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
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impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
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@ -1346,6 +1346,21 @@ uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
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size += 16;
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}
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// Check for float->int copy on T4
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if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
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// Further check for aligned-adjacent pair, so we can use a double move
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if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
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return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st);
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size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st);
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}
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// Check for int->float copy on T4
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if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
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// Further check for aligned-adjacent pair, so we can use a double move
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if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
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return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st);
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size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st);
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}
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// --------------------------------------
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// In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
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// In such cases, I have to do the big-endian swap. For aligned targets, the
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@ -8164,215 +8179,58 @@ instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
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ins_pipe( cadd_cmpltmask );
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%}
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//----------Arithmetic Conversion Instructions---------------------------------
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// The conversions operations are all Alpha sorted. Please keep it that way!
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instruct convD2F_reg(regF dst, regD src) %{
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match(Set dst (ConvD2F src));
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size(4);
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format %{ "FDTOS $src,$dst" %}
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opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
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ins_encode(form3_opf_rs2D_rdF(src, dst));
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ins_pipe(fcvtD2F);
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%}
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//-----------------------------------------------------------------
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// Direct raw moves between float and general registers using VIS3.
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// ins_pipe(faddF_reg);
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instruct MoveF2I_reg_reg(iRegI dst, regF src) %{
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predicate(UseVIS >= 3);
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match(Set dst (MoveF2I src));
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// Convert a double to an int in a float register.
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// If the double is a NAN, stuff a zero in instead.
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instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
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effect(DEF dst, USE src, KILL fcc0);
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format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
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"FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
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"FDTOI $src,$dst\t! convert in delay slot\n\t"
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"FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
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"FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
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"skip:" %}
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ins_encode(form_d2i_helper(src,dst));
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ins_pipe(fcvtD2I);
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%}
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instruct convD2I_reg(stackSlotI dst, regD src) %{
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match(Set dst (ConvD2I src));
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ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
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expand %{
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regF tmp;
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convD2I_helper(tmp, src);
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regF_to_stkI(dst, tmp);
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format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %}
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ins_encode %{
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__ movstouw($src$$FloatRegister, $dst$$Register);
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%}
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%}
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// Convert a double to a long in a double register.
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// If the double is a NAN, stuff a zero in instead.
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instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
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effect(DEF dst, USE src, KILL fcc0);
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format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
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"FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
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"FDTOX $src,$dst\t! convert in delay slot\n\t"
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"FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
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"FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
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"skip:" %}
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ins_encode(form_d2l_helper(src,dst));
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ins_pipe(fcvtD2L);
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%}
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// Double to Long conversion
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instruct convD2L_reg(stackSlotL dst, regD src) %{
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match(Set dst (ConvD2L src));
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ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
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expand %{
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regD tmp;
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convD2L_helper(tmp, src);
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regD_to_stkL(dst, tmp);
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%}
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%}
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instruct convF2D_reg(regD dst, regF src) %{
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match(Set dst (ConvF2D src));
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format %{ "FSTOD $src,$dst" %}
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opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
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ins_encode(form3_opf_rs2F_rdD(src, dst));
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ins_pipe(fcvtF2D);
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%}
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instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
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effect(DEF dst, USE src, KILL fcc0);
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format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
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"FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
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"FSTOI $src,$dst\t! convert in delay slot\n\t"
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"FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
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"FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
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"skip:" %}
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ins_encode(form_f2i_helper(src,dst));
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ins_pipe(fcvtF2I);
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%}
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instruct convF2I_reg(stackSlotI dst, regF src) %{
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match(Set dst (ConvF2I src));
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ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
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expand %{
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regF tmp;
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convF2I_helper(tmp, src);
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regF_to_stkI(dst, tmp);
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%}
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%}
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instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
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effect(DEF dst, USE src, KILL fcc0);
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format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
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"FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
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"FSTOX $src,$dst\t! convert in delay slot\n\t"
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"FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
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"FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
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"skip:" %}
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ins_encode(form_f2l_helper(src,dst));
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ins_pipe(fcvtF2L);
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%}
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// Float to Long conversion
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instruct convF2L_reg(stackSlotL dst, regF src) %{
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match(Set dst (ConvF2L src));
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ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
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expand %{
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regD tmp;
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convF2L_helper(tmp, src);
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regD_to_stkL(dst, tmp);
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%}
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%}
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instruct convI2D_helper(regD dst, regF tmp) %{
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effect(USE tmp, DEF dst);
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format %{ "FITOD $tmp,$dst" %}
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opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
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ins_encode(form3_opf_rs2F_rdD(tmp, dst));
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ins_pipe(fcvtI2D);
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%}
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instruct convI2D_reg(stackSlotI src, regD dst) %{
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match(Set dst (ConvI2D src));
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ins_cost(DEFAULT_COST + MEMORY_REF_COST);
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expand %{
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regF tmp;
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stkI_to_regF( tmp, src);
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convI2D_helper( dst, tmp);
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%}
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%}
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instruct convI2D_mem( regD_low dst, memory mem ) %{
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match(Set dst (ConvI2D (LoadI mem)));
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ins_cost(DEFAULT_COST + MEMORY_REF_COST);
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size(8);
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format %{ "LDF $mem,$dst\n\t"
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"FITOD $dst,$dst" %}
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opcode(Assembler::ldf_op3, Assembler::fitod_opf);
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ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
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ins_pipe(floadF_mem);
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%}
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instruct convI2F_helper(regF dst, regF tmp) %{
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effect(DEF dst, USE tmp);
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format %{ "FITOS $tmp,$dst" %}
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opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
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ins_encode(form3_opf_rs2F_rdF(tmp, dst));
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ins_pipe(fcvtI2F);
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%}
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instruct convI2F_reg( regF dst, stackSlotI src ) %{
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match(Set dst (ConvI2F src));
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ins_cost(DEFAULT_COST + MEMORY_REF_COST);
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expand %{
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regF tmp;
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stkI_to_regF(tmp,src);
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convI2F_helper(dst, tmp);
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%}
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%}
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instruct convI2F_mem( regF dst, memory mem ) %{
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match(Set dst (ConvI2F (LoadI mem)));
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ins_cost(DEFAULT_COST + MEMORY_REF_COST);
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size(8);
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format %{ "LDF $mem,$dst\n\t"
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"FITOS $dst,$dst" %}
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opcode(Assembler::ldf_op3, Assembler::fitos_opf);
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ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
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ins_pipe(floadF_mem);
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%}
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instruct convI2L_reg(iRegL dst, iRegI src) %{
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match(Set dst (ConvI2L src));
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size(4);
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format %{ "SRA $src,0,$dst\t! int->long" %}
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opcode(Assembler::sra_op3, Assembler::arith_op);
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ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
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ins_pipe(ialu_reg_reg);
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%}
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||||
|
||||
// Zero-extend convert int to long
|
||||
instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
|
||||
match(Set dst (AndL (ConvI2L src) mask) );
|
||||
size(4);
|
||||
format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
|
||||
opcode(Assembler::srl_op3, Assembler::arith_op);
|
||||
ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
|
||||
instruct MoveI2F_reg_reg(regF dst, iRegI src) %{
|
||||
predicate(UseVIS >= 3);
|
||||
match(Set dst (MoveI2F src));
|
||||
|
||||
format %{ "MOVWTOS $src,$dst\t! MoveI2F" %}
|
||||
ins_encode %{
|
||||
__ movwtos($src$$Register, $dst$$FloatRegister);
|
||||
%}
|
||||
ins_pipe(ialu_reg_reg);
|
||||
%}
|
||||
|
||||
// Zero-extend long
|
||||
instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
|
||||
match(Set dst (AndL src mask) );
|
||||
size(4);
|
||||
format %{ "SRL $src,0,$dst\t! zero-extend long" %}
|
||||
opcode(Assembler::srl_op3, Assembler::arith_op);
|
||||
ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
|
||||
instruct MoveD2L_reg_reg(iRegL dst, regD src) %{
|
||||
predicate(UseVIS >= 3);
|
||||
match(Set dst (MoveD2L src));
|
||||
|
||||
format %{ "MOVDTOX $src,$dst\t! MoveD2L" %}
|
||||
ins_encode %{
|
||||
__ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register);
|
||||
%}
|
||||
ins_pipe(ialu_reg_reg);
|
||||
%}
|
||||
|
||||
instruct MoveL2D_reg_reg(regD dst, iRegL src) %{
|
||||
predicate(UseVIS >= 3);
|
||||
match(Set dst (MoveL2D src));
|
||||
|
||||
format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
|
||||
ins_encode %{
|
||||
__ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
|
||||
%}
|
||||
ins_pipe(ialu_reg_reg);
|
||||
%}
|
||||
|
||||
|
||||
// Raw moves between float and general registers using stack.
|
||||
|
||||
instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
|
||||
match(Set dst (MoveF2I src));
|
||||
effect(DEF dst, USE src);
|
||||
|
|
@ -8427,7 +8285,7 @@ instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
|
|||
ins_cost(MEMORY_REF_COST);
|
||||
|
||||
size(4);
|
||||
format %{ "STF $src,$dst\t!MoveF2I" %}
|
||||
format %{ "STF $src,$dst\t! MoveF2I" %}
|
||||
opcode(Assembler::stf_op3);
|
||||
ins_encode(simple_form3_mem_reg(dst, src));
|
||||
ins_pipe(fstoreF_stk_reg);
|
||||
|
|
@ -8439,7 +8297,7 @@ instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
|
|||
ins_cost(MEMORY_REF_COST);
|
||||
|
||||
size(4);
|
||||
format %{ "STW $src,$dst\t!MoveI2F" %}
|
||||
format %{ "STW $src,$dst\t! MoveI2F" %}
|
||||
opcode(Assembler::stw_op3);
|
||||
ins_encode(simple_form3_mem_reg( dst, src ) );
|
||||
ins_pipe(istore_mem_reg);
|
||||
|
|
@ -8451,7 +8309,7 @@ instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
|
|||
ins_cost(MEMORY_REF_COST);
|
||||
|
||||
size(4);
|
||||
format %{ "STDF $src,$dst\t!MoveD2L" %}
|
||||
format %{ "STDF $src,$dst\t! MoveD2L" %}
|
||||
opcode(Assembler::stdf_op3);
|
||||
ins_encode(simple_form3_mem_reg(dst, src));
|
||||
ins_pipe(fstoreD_stk_reg);
|
||||
|
|
@ -8463,13 +8321,290 @@ instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
|
|||
ins_cost(MEMORY_REF_COST);
|
||||
|
||||
size(4);
|
||||
format %{ "STX $src,$dst\t!MoveL2D" %}
|
||||
format %{ "STX $src,$dst\t! MoveL2D" %}
|
||||
opcode(Assembler::stx_op3);
|
||||
ins_encode(simple_form3_mem_reg( dst, src ) );
|
||||
ins_pipe(istore_mem_reg);
|
||||
%}
|
||||
|
||||
|
||||
//----------Arithmetic Conversion Instructions---------------------------------
|
||||
// The conversions operations are all Alpha sorted. Please keep it that way!
|
||||
|
||||
instruct convD2F_reg(regF dst, regD src) %{
|
||||
match(Set dst (ConvD2F src));
|
||||
size(4);
|
||||
format %{ "FDTOS $src,$dst" %}
|
||||
opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
|
||||
ins_encode(form3_opf_rs2D_rdF(src, dst));
|
||||
ins_pipe(fcvtD2F);
|
||||
%}
|
||||
|
||||
|
||||
// Convert a double to an int in a float register.
|
||||
// If the double is a NAN, stuff a zero in instead.
|
||||
instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
|
||||
effect(DEF dst, USE src, KILL fcc0);
|
||||
format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
|
||||
"FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
|
||||
"FDTOI $src,$dst\t! convert in delay slot\n\t"
|
||||
"FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
|
||||
"FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
|
||||
"skip:" %}
|
||||
ins_encode(form_d2i_helper(src,dst));
|
||||
ins_pipe(fcvtD2I);
|
||||
%}
|
||||
|
||||
instruct convD2I_stk(stackSlotI dst, regD src) %{
|
||||
match(Set dst (ConvD2I src));
|
||||
ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
|
||||
expand %{
|
||||
regF tmp;
|
||||
convD2I_helper(tmp, src);
|
||||
regF_to_stkI(dst, tmp);
|
||||
%}
|
||||
%}
|
||||
|
||||
instruct convD2I_reg(iRegI dst, regD src) %{
|
||||
predicate(UseVIS >= 3);
|
||||
match(Set dst (ConvD2I src));
|
||||
ins_cost(DEFAULT_COST*2 + BRANCH_COST);
|
||||
expand %{
|
||||
regF tmp;
|
||||
convD2I_helper(tmp, src);
|
||||
MoveF2I_reg_reg(dst, tmp);
|
||||
%}
|
||||
%}
|
||||
|
||||
|
||||
// Convert a double to a long in a double register.
|
||||
// If the double is a NAN, stuff a zero in instead.
|
||||
instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
|
||||
effect(DEF dst, USE src, KILL fcc0);
|
||||
format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
|
||||
"FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
|
||||
"FDTOX $src,$dst\t! convert in delay slot\n\t"
|
||||
"FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
|
||||
"FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
|
||||
"skip:" %}
|
||||
ins_encode(form_d2l_helper(src,dst));
|
||||
ins_pipe(fcvtD2L);
|
||||
%}
|
||||
|
||||
instruct convD2L_stk(stackSlotL dst, regD src) %{
|
||||
match(Set dst (ConvD2L src));
|
||||
ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
|
||||
expand %{
|
||||
regD tmp;
|
||||
convD2L_helper(tmp, src);
|
||||
regD_to_stkL(dst, tmp);
|
||||
%}
|
||||
%}
|
||||
|
||||
instruct convD2L_reg(iRegL dst, regD src) %{
|
||||
predicate(UseVIS >= 3);
|
||||
match(Set dst (ConvD2L src));
|
||||
ins_cost(DEFAULT_COST*2 + BRANCH_COST);
|
||||
expand %{
|
||||
regD tmp;
|
||||
convD2L_helper(tmp, src);
|
||||
MoveD2L_reg_reg(dst, tmp);
|
||||
%}
|
||||
%}
|
||||
|
||||
|
||||
instruct convF2D_reg(regD dst, regF src) %{
|
||||
match(Set dst (ConvF2D src));
|
||||
format %{ "FSTOD $src,$dst" %}
|
||||
opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
|
||||
ins_encode(form3_opf_rs2F_rdD(src, dst));
|
||||
ins_pipe(fcvtF2D);
|
||||
%}
|
||||
|
||||
|
||||
// Convert a float to an int in a float register.
|
||||
// If the float is a NAN, stuff a zero in instead.
|
||||
instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
|
||||
effect(DEF dst, USE src, KILL fcc0);
|
||||
format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
|
||||
"FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
|
||||
"FSTOI $src,$dst\t! convert in delay slot\n\t"
|
||||
"FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
|
||||
"FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
|
||||
"skip:" %}
|
||||
ins_encode(form_f2i_helper(src,dst));
|
||||
ins_pipe(fcvtF2I);
|
||||
%}
|
||||
|
||||
instruct convF2I_stk(stackSlotI dst, regF src) %{
|
||||
match(Set dst (ConvF2I src));
|
||||
ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
|
||||
expand %{
|
||||
regF tmp;
|
||||
convF2I_helper(tmp, src);
|
||||
regF_to_stkI(dst, tmp);
|
||||
%}
|
||||
%}
|
||||
|
||||
instruct convF2I_reg(iRegI dst, regF src) %{
|
||||
predicate(UseVIS >= 3);
|
||||
match(Set dst (ConvF2I src));
|
||||
ins_cost(DEFAULT_COST*2 + BRANCH_COST);
|
||||
expand %{
|
||||
regF tmp;
|
||||
convF2I_helper(tmp, src);
|
||||
MoveF2I_reg_reg(dst, tmp);
|
||||
%}
|
||||
%}
|
||||
|
||||
|
||||
// Convert a float to a long in a float register.
|
||||
// If the float is a NAN, stuff a zero in instead.
|
||||
instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
|
||||
effect(DEF dst, USE src, KILL fcc0);
|
||||
format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
|
||||
"FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
|
||||
"FSTOX $src,$dst\t! convert in delay slot\n\t"
|
||||
"FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
|
||||
"FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
|
||||
"skip:" %}
|
||||
ins_encode(form_f2l_helper(src,dst));
|
||||
ins_pipe(fcvtF2L);
|
||||
%}
|
||||
|
||||
instruct convF2L_stk(stackSlotL dst, regF src) %{
|
||||
match(Set dst (ConvF2L src));
|
||||
ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
|
||||
expand %{
|
||||
regD tmp;
|
||||
convF2L_helper(tmp, src);
|
||||
regD_to_stkL(dst, tmp);
|
||||
%}
|
||||
%}
|
||||
|
||||
instruct convF2L_reg(iRegL dst, regF src) %{
|
||||
predicate(UseVIS >= 3);
|
||||
match(Set dst (ConvF2L src));
|
||||
ins_cost(DEFAULT_COST*2 + BRANCH_COST);
|
||||
expand %{
|
||||
regD tmp;
|
||||
convF2L_helper(tmp, src);
|
||||
MoveD2L_reg_reg(dst, tmp);
|
||||
%}
|
||||
%}
|
||||
|
||||
|
||||
instruct convI2D_helper(regD dst, regF tmp) %{
|
||||
effect(USE tmp, DEF dst);
|
||||
format %{ "FITOD $tmp,$dst" %}
|
||||
opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
|
||||
ins_encode(form3_opf_rs2F_rdD(tmp, dst));
|
||||
ins_pipe(fcvtI2D);
|
||||
%}
|
||||
|
||||
instruct convI2D_stk(stackSlotI src, regD dst) %{
|
||||
match(Set dst (ConvI2D src));
|
||||
ins_cost(DEFAULT_COST + MEMORY_REF_COST);
|
||||
expand %{
|
||||
regF tmp;
|
||||
stkI_to_regF(tmp, src);
|
||||
convI2D_helper(dst, tmp);
|
||||
%}
|
||||
%}
|
||||
|
||||
instruct convI2D_reg(regD_low dst, iRegI src) %{
|
||||
predicate(UseVIS >= 3);
|
||||
match(Set dst (ConvI2D src));
|
||||
expand %{
|
||||
regF tmp;
|
||||
MoveI2F_reg_reg(tmp, src);
|
||||
convI2D_helper(dst, tmp);
|
||||
%}
|
||||
%}
|
||||
|
||||
instruct convI2D_mem(regD_low dst, memory mem) %{
|
||||
match(Set dst (ConvI2D (LoadI mem)));
|
||||
ins_cost(DEFAULT_COST + MEMORY_REF_COST);
|
||||
size(8);
|
||||
format %{ "LDF $mem,$dst\n\t"
|
||||
"FITOD $dst,$dst" %}
|
||||
opcode(Assembler::ldf_op3, Assembler::fitod_opf);
|
||||
ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
|
||||
ins_pipe(floadF_mem);
|
||||
%}
|
||||
|
||||
|
||||
instruct convI2F_helper(regF dst, regF tmp) %{
|
||||
effect(DEF dst, USE tmp);
|
||||
format %{ "FITOS $tmp,$dst" %}
|
||||
opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
|
||||
ins_encode(form3_opf_rs2F_rdF(tmp, dst));
|
||||
ins_pipe(fcvtI2F);
|
||||
%}
|
||||
|
||||
instruct convI2F_stk(regF dst, stackSlotI src) %{
|
||||
match(Set dst (ConvI2F src));
|
||||
ins_cost(DEFAULT_COST + MEMORY_REF_COST);
|
||||
expand %{
|
||||
regF tmp;
|
||||
stkI_to_regF(tmp,src);
|
||||
convI2F_helper(dst, tmp);
|
||||
%}
|
||||
%}
|
||||
|
||||
instruct convI2F_reg(regF dst, iRegI src) %{
|
||||
predicate(UseVIS >= 3);
|
||||
match(Set dst (ConvI2F src));
|
||||
ins_cost(DEFAULT_COST);
|
||||
expand %{
|
||||
regF tmp;
|
||||
MoveI2F_reg_reg(tmp, src);
|
||||
convI2F_helper(dst, tmp);
|
||||
%}
|
||||
%}
|
||||
|
||||
instruct convI2F_mem( regF dst, memory mem ) %{
|
||||
match(Set dst (ConvI2F (LoadI mem)));
|
||||
ins_cost(DEFAULT_COST + MEMORY_REF_COST);
|
||||
size(8);
|
||||
format %{ "LDF $mem,$dst\n\t"
|
||||
"FITOS $dst,$dst" %}
|
||||
opcode(Assembler::ldf_op3, Assembler::fitos_opf);
|
||||
ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
|
||||
ins_pipe(floadF_mem);
|
||||
%}
|
||||
|
||||
|
||||
instruct convI2L_reg(iRegL dst, iRegI src) %{
|
||||
match(Set dst (ConvI2L src));
|
||||
size(4);
|
||||
format %{ "SRA $src,0,$dst\t! int->long" %}
|
||||
opcode(Assembler::sra_op3, Assembler::arith_op);
|
||||
ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
|
||||
ins_pipe(ialu_reg_reg);
|
||||
%}
|
||||
|
||||
// Zero-extend convert int to long
|
||||
instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
|
||||
match(Set dst (AndL (ConvI2L src) mask) );
|
||||
size(4);
|
||||
format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
|
||||
opcode(Assembler::srl_op3, Assembler::arith_op);
|
||||
ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
|
||||
ins_pipe(ialu_reg_reg);
|
||||
%}
|
||||
|
||||
// Zero-extend long
|
||||
instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
|
||||
match(Set dst (AndL src mask) );
|
||||
size(4);
|
||||
format %{ "SRL $src,0,$dst\t! zero-extend long" %}
|
||||
opcode(Assembler::srl_op3, Assembler::arith_op);
|
||||
ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
|
||||
ins_pipe(ialu_reg_reg);
|
||||
%}
|
||||
|
||||
|
||||
//-----------
|
||||
// Long to Double conversion using V8 opcodes.
|
||||
// Still useful because cheetah traps and becomes
|
||||
|
|
@ -8589,7 +8724,7 @@ instruct convL2D_helper(regD dst, regD tmp) %{
|
|||
ins_pipe(fcvtL2D);
|
||||
%}
|
||||
|
||||
instruct convL2D_reg_fast_fxtof(regD dst, stackSlotL src) %{
|
||||
instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{
|
||||
predicate(VM_Version::has_fast_fxtof());
|
||||
match(Set dst (ConvL2D src));
|
||||
ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
|
||||
|
|
@ -8600,10 +8735,15 @@ instruct convL2D_reg_fast_fxtof(regD dst, stackSlotL src) %{
|
|||
%}
|
||||
%}
|
||||
|
||||
//-----------
|
||||
// Long to Float conversion using V8 opcodes.
|
||||
// Still useful because cheetah traps and becomes
|
||||
// amazingly slow for some common numbers.
|
||||
instruct convL2D_reg(regD dst, iRegL src) %{
|
||||
predicate(UseVIS >= 3);
|
||||
match(Set dst (ConvL2D src));
|
||||
expand %{
|
||||
regD tmp;
|
||||
MoveL2D_reg_reg(tmp, src);
|
||||
convL2D_helper(dst, tmp);
|
||||
%}
|
||||
%}
|
||||
|
||||
// Long to Float conversion using fast fxtof
|
||||
instruct convL2F_helper(regF dst, regD tmp) %{
|
||||
|
|
@ -8615,7 +8755,7 @@ instruct convL2F_helper(regF dst, regD tmp) %{
|
|||
ins_pipe(fcvtL2F);
|
||||
%}
|
||||
|
||||
instruct convL2F_reg_fast_fxtof(regF dst, stackSlotL src) %{
|
||||
instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{
|
||||
match(Set dst (ConvL2F src));
|
||||
ins_cost(DEFAULT_COST + MEMORY_REF_COST);
|
||||
expand %{
|
||||
|
|
@ -8624,6 +8764,18 @@ instruct convL2F_reg_fast_fxtof(regF dst, stackSlotL src) %{
|
|||
convL2F_helper(dst, tmp);
|
||||
%}
|
||||
%}
|
||||
|
||||
instruct convL2F_reg(regF dst, iRegL src) %{
|
||||
predicate(UseVIS >= 3);
|
||||
match(Set dst (ConvL2F src));
|
||||
ins_cost(DEFAULT_COST);
|
||||
expand %{
|
||||
regD tmp;
|
||||
MoveL2D_reg_reg(tmp, src);
|
||||
convL2F_helper(dst, tmp);
|
||||
%}
|
||||
%}
|
||||
|
||||
//-----------
|
||||
|
||||
instruct convL2I_reg(iRegI dst, iRegL src) %{
|
||||
|
|
|
|||
|
|
@ -144,6 +144,18 @@ void VM_Version::initialize() {
|
|||
// buf is started with ", " or is empty
|
||||
_features_str = strdup(strlen(buf) > 2 ? buf + 2 : buf);
|
||||
|
||||
// UseVIS is set to the smallest of what hardware supports and what
|
||||
// the command line requires. I.e., you cannot set UseVIS to 3 on
|
||||
// older UltraSparc which do not support it.
|
||||
if (UseVIS > 3) UseVIS=3;
|
||||
if (UseVIS < 0) UseVIS=0;
|
||||
if (!has_vis3()) // Drop to 2 if no VIS3 support
|
||||
UseVIS = MIN2((intx)2,UseVIS);
|
||||
if (!has_vis2()) // Drop to 1 if no VIS2 support
|
||||
UseVIS = MIN2((intx)1,UseVIS);
|
||||
if (!has_vis1()) // Drop to 0 if no VIS1 support
|
||||
UseVIS = 0;
|
||||
|
||||
#ifndef PRODUCT
|
||||
if (PrintMiscellaneous && Verbose) {
|
||||
tty->print("Allocation: ");
|
||||
|
|
|
|||
|
|
@ -492,6 +492,9 @@ class CommandLineFlags {
|
|||
product(intx, UseSSE, 99, \
|
||||
"Highest supported SSE instructions set on x86/x64") \
|
||||
\
|
||||
product(intx, UseVIS, 99, \
|
||||
"Highest supported VIS instructions set on Sparc") \
|
||||
\
|
||||
product(uintx, LargePageSizeInBytes, 0, \
|
||||
"Large page size (0 to let VM choose the page size") \
|
||||
\
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue