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5108146: Merge i486 and amd64 cpu directories
6459804: Want client (c1) compiler for x86_64 (amd64) for faster start-up Reviewed-by: kvn
This commit is contained in:
Tom Rodriguez
parent
2697216f3a
commit
26c780da72
85 changed files with 18308 additions and 15496 deletions
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@ -80,7 +80,7 @@ LinearScan::LinearScan(IR* ir, LIRGenerator* gen, FrameMap* frame_map)
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, _scope_value_cache(0) // initialized later with correct length
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, _interval_in_loop(0, 0) // initialized later with correct length
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, _cached_blocks(*ir->linear_scan_order())
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#ifdef IA32
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#ifdef X86
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, _fpu_stack_allocator(NULL)
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#endif
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{
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@ -116,7 +116,7 @@ int LinearScan::reg_num(LIR_Opr opr) {
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return opr->cpu_regnr();
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} else if (opr->is_double_cpu()) {
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return opr->cpu_regnrLo();
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#ifdef IA32
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#ifdef X86
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} else if (opr->is_single_xmm()) {
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return opr->fpu_regnr() + pd_first_xmm_reg;
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} else if (opr->is_double_xmm()) {
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@ -128,6 +128,7 @@ int LinearScan::reg_num(LIR_Opr opr) {
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return opr->fpu_regnrLo() + pd_first_fpu_reg;
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} else {
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ShouldNotReachHere();
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return -1;
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}
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}
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@ -140,7 +141,7 @@ int LinearScan::reg_numHi(LIR_Opr opr) {
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return -1;
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} else if (opr->is_double_cpu()) {
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return opr->cpu_regnrHi();
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#ifdef IA32
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#ifdef X86
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} else if (opr->is_single_xmm()) {
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return -1;
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} else if (opr->is_double_xmm()) {
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@ -152,6 +153,7 @@ int LinearScan::reg_numHi(LIR_Opr opr) {
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return opr->fpu_regnrHi() + pd_first_fpu_reg;
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} else {
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ShouldNotReachHere();
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return -1;
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}
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}
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@ -1063,7 +1065,7 @@ IntervalUseKind LinearScan::use_kind_of_input_operand(LIR_Op* op, LIR_Opr opr) {
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}
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#ifdef IA32
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#ifdef X86
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if (op->code() == lir_cmove) {
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// conditional moves can handle stack operands
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assert(op->result_opr()->is_register(), "result must always be in a register");
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@ -1128,7 +1130,7 @@ IntervalUseKind LinearScan::use_kind_of_input_operand(LIR_Op* op, LIR_Opr opr) {
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}
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}
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}
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#endif // IA32
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#endif // X86
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// all other operands require a register
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return mustHaveRegister;
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@ -1261,7 +1263,7 @@ void LinearScan::build_intervals() {
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// virtual fpu operands. Otherwise no allocation for fpu registers is
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// perfomed and so the temp ranges would be useless
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if (has_fpu_registers()) {
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#ifdef IA32
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#ifdef X86
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if (UseSSE < 2) {
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#endif
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for (i = 0; i < FrameMap::nof_caller_save_fpu_regs; i++) {
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@ -1270,7 +1272,7 @@ void LinearScan::build_intervals() {
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assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
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caller_save_registers[num_caller_save_registers++] = reg_num(opr);
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}
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#ifdef IA32
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#ifdef X86
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}
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if (UseSSE > 0) {
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for (i = 0; i < FrameMap::nof_caller_save_xmm_regs; i++) {
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@ -1299,8 +1301,8 @@ void LinearScan::build_intervals() {
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// Update intervals for registers live at the end of this block;
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BitMap live = block->live_out();
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int size = live.size();
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for (int number = live.get_next_one_offset(0, size); number < size; number = live.get_next_one_offset(number + 1, size)) {
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int size = (int)live.size();
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for (int number = (int)live.get_next_one_offset(0, size); number < size; number = (int)live.get_next_one_offset(number + 1, size)) {
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assert(live.at(number), "should not stop here otherwise");
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assert(number >= LIR_OprDesc::vreg_base, "fixed intervals must not be live on block bounds");
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TRACE_LINEAR_SCAN(2, tty->print_cr("live in %d to %d", number, block_to + 2));
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@ -1654,7 +1656,7 @@ void LinearScan::resolve_collect_mappings(BlockBegin* from_block, BlockBegin* to
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const BitMap live_at_edge = to_block->live_in();
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// visit all registers where the live_at_edge bit is set
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for (int r = live_at_edge.get_next_one_offset(0, size); r < size; r = live_at_edge.get_next_one_offset(r + 1, size)) {
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for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) {
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assert(r < num_regs, "live information set for not exisiting interval");
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assert(from_block->live_out().at(r) && to_block->live_in().at(r), "interval not live at this edge");
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@ -1824,7 +1826,7 @@ void LinearScan::resolve_exception_entry(BlockBegin* block, MoveResolver &move_r
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// visit all registers where the live_in bit is set
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int size = live_set_size();
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for (int r = block->live_in().get_next_one_offset(0, size); r < size; r = block->live_in().get_next_one_offset(r + 1, size)) {
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for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) {
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resolve_exception_entry(block, r, move_resolver);
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}
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@ -1898,7 +1900,7 @@ void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, M
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// visit all registers where the live_in bit is set
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BlockBegin* block = handler->entry_block();
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int size = live_set_size();
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for (int r = block->live_in().get_next_one_offset(0, size); r < size; r = block->live_in().get_next_one_offset(r + 1, size)) {
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for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) {
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resolve_exception_edge(handler, throwing_op_id, r, NULL, move_resolver);
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}
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@ -2032,19 +2034,19 @@ LIR_Opr LinearScan::calc_operand_for_interval(const Interval* interval) {
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assert(assigned_reg % 2 == 0 && assigned_reg + 1 == assigned_regHi, "must be sequential and even");
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}
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#ifdef SPARC
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#ifdef _LP64
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return LIR_OprFact::double_cpu(assigned_reg, assigned_reg);
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#else
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#ifdef SPARC
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return LIR_OprFact::double_cpu(assigned_regHi, assigned_reg);
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#endif
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#else
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return LIR_OprFact::double_cpu(assigned_reg, assigned_regHi);
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#endif
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#endif // SPARC
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#endif // LP64
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}
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case T_FLOAT: {
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#ifdef IA32
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#ifdef X86
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if (UseSSE >= 1) {
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assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= pd_last_xmm_reg, "no xmm register");
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assert(interval->assigned_regHi() == any_reg, "must not have hi register");
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@ -2058,7 +2060,7 @@ LIR_Opr LinearScan::calc_operand_for_interval(const Interval* interval) {
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}
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case T_DOUBLE: {
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#ifdef IA32
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#ifdef X86
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if (UseSSE >= 2) {
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assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= pd_last_xmm_reg, "no xmm register");
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assert(interval->assigned_regHi() == any_reg, "must not have hi register (double xmm values are stored in one register)");
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@ -2122,7 +2124,7 @@ LIR_Opr LinearScan::color_lir_opr(LIR_Opr opr, int op_id, LIR_OpVisitState::OprM
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LIR_Opr res = operand_for_interval(interval);
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#ifdef IA32
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#ifdef X86
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// new semantic for is_last_use: not only set on definite end of interval,
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// but also before hole
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// This may still miss some cases (e.g. for dead values), but it is not necessary that the
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@ -2475,6 +2477,7 @@ int LinearScan::append_scope_value_for_constant(LIR_Opr opr, GrowableArray<Scope
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default:
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ShouldNotReachHere();
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return -1;
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}
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}
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@ -2515,7 +2518,7 @@ int LinearScan::append_scope_value_for_operand(LIR_Opr opr, GrowableArray<ScopeV
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scope_values->append(sv);
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return 1;
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#ifdef IA32
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#ifdef X86
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} else if (opr->is_single_xmm()) {
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VMReg rname = opr->as_xmm_float_reg()->as_VMReg();
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LocationValue* sv = new LocationValue(Location::new_reg_loc(Location::normal, rname));
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@ -2525,7 +2528,7 @@ int LinearScan::append_scope_value_for_operand(LIR_Opr opr, GrowableArray<ScopeV
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#endif
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} else if (opr->is_single_fpu()) {
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#ifdef IA32
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#ifdef X86
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// the exact location of fpu stack values is only known
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// during fpu stack allocation, so the stack allocator object
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// must be present
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@ -2548,12 +2551,23 @@ int LinearScan::append_scope_value_for_operand(LIR_Opr opr, GrowableArray<ScopeV
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ScopeValue* second;
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if (opr->is_double_stack()) {
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#ifdef _LP64
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Location loc1;
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Location::Type loc_type = opr->type() == T_LONG ? Location::lng : Location::dbl;
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if (!frame_map()->locations_for_slot(opr->double_stack_ix(), loc_type, &loc1, NULL)) {
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bailout("too large frame");
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}
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// Does this reverse on x86 vs. sparc?
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first = new LocationValue(loc1);
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second = &_int_0_scope_value;
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#else
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Location loc1, loc2;
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if (!frame_map()->locations_for_slot(opr->double_stack_ix(), Location::normal, &loc1, &loc2)) {
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bailout("too large frame");
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}
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first = new LocationValue(loc1);
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second = new LocationValue(loc2);
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#endif // _LP64
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} else if (opr->is_double_cpu()) {
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#ifdef _LP64
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@ -2573,9 +2587,10 @@ int LinearScan::append_scope_value_for_operand(LIR_Opr opr, GrowableArray<ScopeV
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first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
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second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
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#endif
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#endif //_LP64
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#ifdef IA32
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#ifdef X86
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} else if (opr->is_double_xmm()) {
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assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation");
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VMReg rname_first = opr->as_xmm_double_reg()->as_VMReg();
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@ -2589,13 +2604,13 @@ int LinearScan::append_scope_value_for_operand(LIR_Opr opr, GrowableArray<ScopeV
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} else if (opr->is_double_fpu()) {
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// On SPARC, fpu_regnrLo/fpu_regnrHi represents the two halves of
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// the double as float registers in the native ordering. On IA32,
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// the double as float registers in the native ordering. On X86,
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// fpu_regnrLo is a FPU stack slot whose VMReg represents
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// the low-order word of the double and fpu_regnrLo + 1 is the
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// name for the other half. *first and *second must represent the
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// least and most significant words, respectively.
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#ifdef IA32
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#ifdef X86
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// the exact location of fpu stack values is only known
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// during fpu stack allocation, so the stack allocator object
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// must be present
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@ -2865,7 +2880,6 @@ void LinearScan::assign_reg_num(LIR_OpList* instructions, IntervalWalker* iw) {
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op->verify();
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#endif
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#ifndef _LP64
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// remove useless moves
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if (op->code() == lir_move) {
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assert(op->as_Op1() != NULL, "move must be LIR_Op1");
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@ -2879,7 +2893,6 @@ void LinearScan::assign_reg_num(LIR_OpList* instructions, IntervalWalker* iw) {
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has_dead = true;
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}
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}
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#endif
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}
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if (has_dead) {
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@ -3192,7 +3205,7 @@ void LinearScan::verify_constants() {
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BitMap live_at_edge = block->live_in();
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// visit all registers where the live_at_edge bit is set
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for (int r = live_at_edge.get_next_one_offset(0, size); r < size; r = live_at_edge.get_next_one_offset(r + 1, size)) {
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for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) {
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TRACE_LINEAR_SCAN(4, tty->print("checking interval %d of block B%d", r, block->block_id()));
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Value value = gen()->instruction_for_vreg(r);
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@ -3438,7 +3451,7 @@ void RegisterVerifier::process_operations(LIR_List* ops, IntervalList* input_sta
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state_put(input_state, reg_num(FrameMap::caller_save_fpu_reg_at(j)), NULL);
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}
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#ifdef IA32
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#ifdef X86
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for (j = 0; j < FrameMap::nof_caller_save_xmm_regs; j++) {
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state_put(input_state, reg_num(FrameMap::caller_save_xmm_reg_at(j)), NULL);
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}
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@ -4357,7 +4370,7 @@ void Interval::print(outputStream* out) const {
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opr = LIR_OprFact::single_cpu(assigned_reg());
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} else if (assigned_reg() >= pd_first_fpu_reg && assigned_reg() <= pd_last_fpu_reg) {
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opr = LIR_OprFact::single_fpu(assigned_reg() - pd_first_fpu_reg);
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#ifdef IA32
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#ifdef X86
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} else if (assigned_reg() >= pd_first_xmm_reg && assigned_reg() <= pd_last_xmm_reg) {
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opr = LIR_OprFact::single_xmm(assigned_reg() - pd_first_xmm_reg);
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#endif
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@ -5435,7 +5448,7 @@ void LinearScanWalker::alloc_locked_reg(Interval* cur) {
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}
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bool LinearScanWalker::no_allocation_possible(Interval* cur) {
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#ifdef IA32
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#ifdef X86
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// fast calculation of intervals that can never get a register because the
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// the next instruction is a call that blocks all registers
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// Note: this does not work if callee-saved registers are available (e.g. on Sparc)
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