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8295968: RISC-V: Rename some assembler intrinsic functions for RVV 1.0

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Reviewed-by: fyang
This commit is contained in:
Dingli Zhang 2022-11-02 12:34:23 +00:00 • committed by Fei Yang
commit 2bd24c4542
4 changed files with 10 additions and 10 deletions
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14
src/hotspot/cpu/riscv/assembler_riscv.hpp
View file

@ -1136,7 +1136,7 @@ enum VectorMask {
} }
// Vector Mask // Vector Mask
INSN(vpopc_m, 0b1010111, 0b010, 0b10000, 0b010000); INSN(vcpop_m, 0b1010111, 0b010, 0b10000, 0b010000);
INSN(vfirst_m, 0b1010111, 0b010, 0b10001, 0b010000); INSN(vfirst_m, 0b1010111, 0b010, 0b10001, 0b010000);
#undef INSN #undef INSN
@ -1282,7 +1282,7 @@ enum VectorMask {
} }
// Vector Single-Width Floating-Point Reduction Instructions // Vector Single-Width Floating-Point Reduction Instructions
INSN(vfredsum_vs, 0b1010111, 0b001, 0b000001); INSN(vfredusum_vs, 0b1010111, 0b001, 0b000001);
INSN(vfredosum_vs, 0b1010111, 0b001, 0b000011); INSN(vfredosum_vs, 0b1010111, 0b001, 0b000011);
INSN(vfredmin_vs, 0b1010111, 0b001, 0b000101); INSN(vfredmin_vs, 0b1010111, 0b001, 0b000101);
INSN(vfredmax_vs, 0b1010111, 0b001, 0b000111); INSN(vfredmax_vs, 0b1010111, 0b001, 0b000111);
@ -1492,11 +1492,11 @@ enum VectorMask {
// Vector Mask-Register Logical Instructions // Vector Mask-Register Logical Instructions
INSN(vmxnor_mm, 0b1010111, 0b010, 0b1, 0b011111); INSN(vmxnor_mm, 0b1010111, 0b010, 0b1, 0b011111);
INSN(vmornot_mm, 0b1010111, 0b010, 0b1, 0b011100); INSN(vmorn_mm, 0b1010111, 0b010, 0b1, 0b011100);
INSN(vmnor_mm, 0b1010111, 0b010, 0b1, 0b011110); INSN(vmnor_mm, 0b1010111, 0b010, 0b1, 0b011110);
INSN(vmor_mm, 0b1010111, 0b010, 0b1, 0b011010); INSN(vmor_mm, 0b1010111, 0b010, 0b1, 0b011010);
INSN(vmxor_mm, 0b1010111, 0b010, 0b1, 0b011011); INSN(vmxor_mm, 0b1010111, 0b010, 0b1, 0b011011);
INSN(vmandnot_mm, 0b1010111, 0b010, 0b1, 0b011000); INSN(vmandn_mm, 0b1010111, 0b010, 0b1, 0b011000);
INSN(vmnand_mm, 0b1010111, 0b010, 0b1, 0b011101); INSN(vmnand_mm, 0b1010111, 0b010, 0b1, 0b011101);
INSN(vmand_mm, 0b1010111, 0b010, 0b1, 0b011001); INSN(vmand_mm, 0b1010111, 0b010, 0b1, 0b011001);
@ -1596,7 +1596,7 @@ enum Nf {
} }
// Vector Load/Store Instructions // Vector Load/Store Instructions
INSN(vl1r_v, 0b0000111, 0b01000, 0b1, 0b00, g1); INSN(vl1re8_v, 0b0000111, 0b01000, 0b1, 0b00, g1);
#undef INSN #undef INSN
@ -1617,8 +1617,8 @@ enum Nf {
} }
// Vector Unit-Stride Instructions // Vector Unit-Stride Instructions
INSN(vle1_v, 0b0000111, 0b000, 0b01011, 0b00, 0b0); INSN(vlm_v, 0b0000111, 0b000, 0b01011, 0b00, 0b0);
INSN(vse1_v, 0b0100111, 0b000, 0b01011, 0b00, 0b0); INSN(vsm_v, 0b0100111, 0b000, 0b01011, 0b00, 0b0);
#undef INSN #undef INSN

2
src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp
View file

@ -1673,7 +1673,7 @@ void C2_MacroAssembler::reduce_minmax_FD_v(FloatRegister dst,
bind(L_NaN); bind(L_NaN);
vfmv_s_f(tmp2, src1); vfmv_s_f(tmp2, src1);
vfredsum_vs(tmp1, src2, tmp2); vfredusum_vs(tmp1, src2, tmp2);
bind(L_done); bind(L_done);
vfmv_f_s(dst, tmp1); vfmv_f_s(dst, tmp1);

2
src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.hpp
View file

@ -134,7 +134,7 @@
void unspill(VectorRegister v, int offset) { void unspill(VectorRegister v, int offset) {
add(t0, sp, offset); add(t0, sp, offset);
vl1r_v(v, t0); vl1re8_v(v, t0);
} }
void spill_copy_vector_stack_to_stack(int src_offset, int dst_offset, int vec_reg_size_in_bytes) { void spill_copy_vector_stack_to_stack(int src_offset, int dst_offset, int vec_reg_size_in_bytes) {

2
src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
View file

@ -1310,7 +1310,7 @@ int MacroAssembler::pop_v(unsigned int bitset, Register stack) {
int count = bitset_to_regs(bitset, regs); int count = bitset_to_regs(bitset, regs);
for (int i = count - 1; i >= 0; i--) { for (int i = count - 1; i >= 0; i--) {
vl1r_v(as_VectorRegister(regs[i]), stack); vl1re8_v(as_VectorRegister(regs[i]), stack);
add(stack, stack, vector_size_in_bytes); add(stack, stack, vector_size_in_bytes);
} }