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8149418: AArch64: replace tst+br with tbz instruction when tst's constant operand is 2 power

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Replace tst+br with tbz instruction when tst's constant operand is 2 power

Reviewed-by: aph
This commit is contained in:
Fei Yang 2016-06-02 21:12:46 +08:00
parent 35f9db149b
commit 2e85bb45ff
4 changed files with 9 additions and 16 deletions
Download patch file Download diff file Expand all files Collapse all files

3
hotspot/src/cpu/aarch64/vm/c1_Runtime1_aarch64.cpp
View file

@ -944,8 +944,7 @@ OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
Register t = r5;
__ load_klass(t, r0);
__ ldrw(t, Address(t, Klass::access_flags_offset()));
__ tst(t, JVM_ACC_HAS_FINALIZER);
__ br(Assembler::NE, register_finalizer);
__ tbnz(t, exact_log2(JVM_ACC_HAS_FINALIZER), register_finalizer);
__ ret(lr);
__ bind(register_finalizer);

13
hotspot/src/cpu/aarch64/vm/interp_masm_aarch64.cpp
View file

@ -93,10 +93,8 @@ void InterpreterMacroAssembler::check_and_handle_popframe(Register java_thread)
// This method is only called just after the call into the vm in
// call_VM_base, so the arg registers are available.
ldrw(rscratch1, Address(rthread, JavaThread::popframe_condition_offset()));
tstw(rscratch1, JavaThread::popframe_pending_bit);
br(Assembler::EQ, L);
tstw(rscratch1, JavaThread::popframe_processing_bit);
br(Assembler::NE, L);
tbz(rscratch1, exact_log2(JavaThread::popframe_pending_bit), L);
tbnz(rscratch1, exact_log2(JavaThread::popframe_processing_bit), L);
// Call Interpreter::remove_activation_preserving_args_entry() to get the
// address of the same-named entrypoint in the generated interpreter code.
call_VM_leaf(CAST_FROM_FN_PTR(address, Interpreter::remove_activation_preserving_args_entry));
@ -505,8 +503,7 @@ void InterpreterMacroAssembler::remove_activation(
// get method access flags
ldr(r1, Address(rfp, frame::interpreter_frame_method_offset * wordSize));
ldr(r2, Address(r1, Method::access_flags_offset()));
tst(r2, JVM_ACC_SYNCHRONIZED);
br(Assembler::EQ, unlocked);
tbz(r2, exact_log2(JVM_ACC_SYNCHRONIZED), unlocked);
// Don't unlock anything if the _do_not_unlock_if_synchronized flag
// is set.
@ -1582,8 +1579,8 @@ void InterpreterMacroAssembler::profile_obj_type(Register obj, const Address& md
// do. The unknown bit may have been
// set already but no need to check.
tst(obj, TypeEntries::type_unknown);
br(Assembler::NE, next); // already unknown. Nothing to do anymore.
tbnz(obj, exact_log2(TypeEntries::type_unknown), next);
// already unknown. Nothing to do anymore.
ldr(rscratch1, mdo_addr);
cbz(rscratch1, none);

6
hotspot/src/cpu/aarch64/vm/templateInterpreterGenerator_aarch64.cpp
View file

@ -1242,8 +1242,7 @@ address TemplateInterpreterGenerator::generate_native_entry(bool synchronized) {
{
Label L;
__ ldrw(t, Address(rmethod, Method::access_flags_offset()));
__ tst(t, JVM_ACC_STATIC);
__ br(Assembler::EQ, L);
__ tbz(t, exact_log2(JVM_ACC_STATIC), L);
// get mirror
__ load_mirror(t, rmethod);
// copy mirror into activation frame
@ -1435,8 +1434,7 @@ address TemplateInterpreterGenerator::generate_native_entry(bool synchronized) {
{
Label L;
__ ldrw(t, Address(rmethod, Method::access_flags_offset()));
__ tst(t, JVM_ACC_SYNCHRONIZED);
__ br(Assembler::EQ, L);
__ tbz(t, exact_log2(JVM_ACC_SYNCHRONIZED), L);
// the code below should be shared with interpreter macro
// assembler implementation
{

3
hotspot/src/cpu/aarch64/vm/templateTable_aarch64.cpp
View file

@ -2190,9 +2190,8 @@ void TemplateTable::_return(TosState state)
__ ldr(c_rarg1, aaddress(0));
__ load_klass(r3, c_rarg1);
__ ldrw(r3, Address(r3, Klass::access_flags_offset()));
__ tst(r3, JVM_ACC_HAS_FINALIZER);
Label skip_register_finalizer;
__ br(Assembler::EQ, skip_register_finalizer);
__ tbz(r3, exact_log2(JVM_ACC_HAS_FINALIZER), skip_register_finalizer);
__ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::register_finalizer), c_rarg1);