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8187443: Forest Consolidation: Move files to unified layout
Reviewed-by: darcy, ihse
This commit is contained in:
Erik Joelsson
parent
270fe13182
commit
3789983e89
56923 changed files with 3 additions and 15727 deletions
331
src/hotspot/cpu/sparc/vm_version_sparc.hpp
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331
src/hotspot/cpu/sparc/vm_version_sparc.hpp
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/*
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* Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*
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*/
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#ifndef CPU_SPARC_VM_VM_VERSION_SPARC_HPP
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#define CPU_SPARC_VM_VM_VERSION_SPARC_HPP
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#include "runtime/globals_extension.hpp"
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#include "runtime/vm_version.hpp"
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class VM_Version: public Abstract_VM_Version {
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friend class VMStructs;
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friend class JVMCIVMStructs;
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protected:
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enum {
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ISA_V9,
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ISA_POPC,
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ISA_VIS1,
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ISA_VIS2,
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ISA_BLK_INIT,
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ISA_FMAF,
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ISA_VIS3,
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ISA_HPC,
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ISA_IMA,
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ISA_AES,
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ISA_DES,
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ISA_KASUMI,
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ISA_CAMELLIA,
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ISA_MD5,
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ISA_SHA1,
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ISA_SHA256,
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ISA_SHA512,
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ISA_MPMUL,
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ISA_MONT,
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ISA_PAUSE,
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ISA_CBCOND,
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ISA_CRC32C,
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ISA_FJATHPLUS,
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ISA_VIS3B,
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ISA_ADI,
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ISA_SPARC5,
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ISA_MWAIT,
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ISA_XMPMUL,
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ISA_XMONT,
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ISA_PAUSE_NSEC,
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ISA_VAMASK,
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// Synthesised properties:
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CPU_FAST_IDIV,
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CPU_FAST_RDPC,
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CPU_FAST_BIS,
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CPU_FAST_LD,
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CPU_FAST_CMOVE,
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CPU_FAST_IND_BR,
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CPU_BLK_ZEROING
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};
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private:
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enum { ISA_last_feature = ISA_VAMASK,
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CPU_last_feature = CPU_BLK_ZEROING };
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enum {
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ISA_unknown_msk = 0,
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ISA_v9_msk = UINT64_C(1) << ISA_V9,
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ISA_popc_msk = UINT64_C(1) << ISA_POPC,
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ISA_vis1_msk = UINT64_C(1) << ISA_VIS1,
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ISA_vis2_msk = UINT64_C(1) << ISA_VIS2,
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ISA_blk_init_msk = UINT64_C(1) << ISA_BLK_INIT,
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ISA_fmaf_msk = UINT64_C(1) << ISA_FMAF,
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ISA_vis3_msk = UINT64_C(1) << ISA_VIS3,
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ISA_hpc_msk = UINT64_C(1) << ISA_HPC,
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ISA_ima_msk = UINT64_C(1) << ISA_IMA,
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ISA_aes_msk = UINT64_C(1) << ISA_AES,
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ISA_des_msk = UINT64_C(1) << ISA_DES,
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ISA_kasumi_msk = UINT64_C(1) << ISA_KASUMI,
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ISA_camellia_msk = UINT64_C(1) << ISA_CAMELLIA,
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ISA_md5_msk = UINT64_C(1) << ISA_MD5,
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ISA_sha1_msk = UINT64_C(1) << ISA_SHA1,
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ISA_sha256_msk = UINT64_C(1) << ISA_SHA256,
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ISA_sha512_msk = UINT64_C(1) << ISA_SHA512,
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ISA_mpmul_msk = UINT64_C(1) << ISA_MPMUL,
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ISA_mont_msk = UINT64_C(1) << ISA_MONT,
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ISA_pause_msk = UINT64_C(1) << ISA_PAUSE,
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ISA_cbcond_msk = UINT64_C(1) << ISA_CBCOND,
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ISA_crc32c_msk = UINT64_C(1) << ISA_CRC32C,
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ISA_fjathplus_msk = UINT64_C(1) << ISA_FJATHPLUS,
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ISA_vis3b_msk = UINT64_C(1) << ISA_VIS3B,
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ISA_adi_msk = UINT64_C(1) << ISA_ADI,
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ISA_sparc5_msk = UINT64_C(1) << ISA_SPARC5,
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ISA_mwait_msk = UINT64_C(1) << ISA_MWAIT,
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ISA_xmpmul_msk = UINT64_C(1) << ISA_XMPMUL,
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ISA_xmont_msk = UINT64_C(1) << ISA_XMONT,
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ISA_pause_nsec_msk = UINT64_C(1) << ISA_PAUSE_NSEC,
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ISA_vamask_msk = UINT64_C(1) << ISA_VAMASK,
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CPU_fast_idiv_msk = UINT64_C(1) << CPU_FAST_IDIV,
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CPU_fast_rdpc_msk = UINT64_C(1) << CPU_FAST_RDPC,
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CPU_fast_bis_msk = UINT64_C(1) << CPU_FAST_BIS,
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CPU_fast_ld_msk = UINT64_C(1) << CPU_FAST_LD,
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CPU_fast_cmove_msk = UINT64_C(1) << CPU_FAST_CMOVE,
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CPU_fast_ind_br_msk = UINT64_C(1) << CPU_FAST_IND_BR,
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CPU_blk_zeroing_msk = UINT64_C(1) << CPU_BLK_ZEROING,
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last_feature_msk = CPU_blk_zeroing_msk,
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full_feature_msk = (last_feature_msk << 1) - 1
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};
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/* The following, previously supported, SPARC implementations are no longer
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* supported.
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*
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* UltraSPARC I/II:
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* SPARC-V9, VIS
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* UltraSPARC III/+: (Cheetah/+)
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* SPARC-V9, VIS
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* UltraSPARC IV: (Jaguar)
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* SPARC-V9, VIS
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* UltraSPARC IV+: (Panther)
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* SPARC-V9, VIS, POPC
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*
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* The currently supported SPARC implementations are listed below (including
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* generic V9 support).
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*
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* UltraSPARC T1: (Niagara)
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* SPARC-V9, VIS, ASI_BIS (Crypto/hash in SPU)
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* UltraSPARC T2: (Niagara-2)
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* SPARC-V9, VIS, ASI_BIS, POPC (Crypto/hash in SPU)
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* UltraSPARC T2+: (Victoria Falls, etc.)
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* SPARC-V9, VIS, VIS2, ASI_BIS, POPC (Crypto/hash in SPU)
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*
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* UltraSPARC T3: (Rainbow Falls/S2)
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* SPARC-V9, VIS, VIS2, ASI_BIS, POPC (Crypto/hash in SPU)
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*
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* Oracle SPARC T4/T5/M5: (Core S3)
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* SPARC-V9, VIS, VIS2, VIS3, ASI_BIS, HPC, POPC, FMAF, IMA, PAUSE, CBCOND,
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* AES, DES, Kasumi, Camellia, MD5, SHA1, SHA256, SHA512, CRC32C, MONT, MPMUL
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*
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* Oracle SPARC M7: (Core S4)
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* SPARC-V9, VIS, VIS2, VIS3, ASI_BIS, HPC, POPC, FMAF, IMA, PAUSE, CBCOND,
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* AES, DES, Camellia, MD5, SHA1, SHA256, SHA512, CRC32C, MONT, MPMUL, VIS3b,
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* ADI, SPARC5, MWAIT, XMPMUL, XMONT, PAUSE_NSEC, VAMASK
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*
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*/
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enum {
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niagara1_msk = ISA_v9_msk | ISA_vis1_msk | ISA_blk_init_msk,
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niagara2_msk = niagara1_msk | ISA_popc_msk,
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core_S2_msk = niagara2_msk | ISA_vis2_msk,
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core_S3_msk = core_S2_msk | ISA_fmaf_msk | ISA_vis3_msk | ISA_hpc_msk |
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ISA_ima_msk | ISA_aes_msk | ISA_des_msk | ISA_kasumi_msk |
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ISA_camellia_msk | ISA_md5_msk | ISA_sha1_msk | ISA_sha256_msk |
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ISA_sha512_msk | ISA_mpmul_msk | ISA_mont_msk | ISA_pause_msk |
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ISA_cbcond_msk | ISA_crc32c_msk,
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core_S4_msk = core_S3_msk - ISA_kasumi_msk |
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ISA_vis3b_msk | ISA_adi_msk | ISA_sparc5_msk | ISA_mwait_msk |
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ISA_xmpmul_msk | ISA_xmont_msk | ISA_pause_nsec_msk | ISA_vamask_msk,
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ultra_sparc_t1_msk = niagara1_msk,
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ultra_sparc_t2_msk = niagara2_msk,
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ultra_sparc_t3_msk = core_S2_msk,
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ultra_sparc_m5_msk = core_S3_msk, // NOTE: First out-of-order pipeline.
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ultra_sparc_m7_msk = core_S4_msk
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};
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static uint _L2_data_cache_line_size;
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static uint L2_data_cache_line_size() { return _L2_data_cache_line_size; }
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static void determine_features();
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static void platform_features();
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static void print_features();
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public:
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enum {
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// Adopt a conservative behaviour (modelling single-insn-fetch-n-issue) for
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// Niagara (and SPARC64). While there are at least two entries/slots in the
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// instruction fetch buffer on any Niagara core (and as many as eight on a
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// SPARC64), the performance improvement from keeping hot branch targets on
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// optimally aligned addresses is such a small one (if any) that we choose
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// not to use the extra code space required.
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insn_fetch_alignment = 4 // Byte alignment in L1 insn. cache.
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};
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static void initialize();
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static void init_before_ergo() { determine_features(); }
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// Instruction feature support:
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static bool has_v9() { return (_features & ISA_v9_msk) != 0; }
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static bool has_popc() { return (_features & ISA_popc_msk) != 0; }
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static bool has_vis1() { return (_features & ISA_vis1_msk) != 0; }
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static bool has_vis2() { return (_features & ISA_vis2_msk) != 0; }
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static bool has_blk_init() { return (_features & ISA_blk_init_msk) != 0; }
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static bool has_fmaf() { return (_features & ISA_fmaf_msk) != 0; }
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static bool has_vis3() { return (_features & ISA_vis3_msk) != 0; }
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static bool has_hpc() { return (_features & ISA_hpc_msk) != 0; }
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static bool has_ima() { return (_features & ISA_ima_msk) != 0; }
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static bool has_aes() { return (_features & ISA_aes_msk) != 0; }
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static bool has_des() { return (_features & ISA_des_msk) != 0; }
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static bool has_kasumi() { return (_features & ISA_kasumi_msk) != 0; }
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static bool has_camellia() { return (_features & ISA_camellia_msk) != 0; }
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static bool has_md5() { return (_features & ISA_md5_msk) != 0; }
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static bool has_sha1() { return (_features & ISA_sha1_msk) != 0; }
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static bool has_sha256() { return (_features & ISA_sha256_msk) != 0; }
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static bool has_sha512() { return (_features & ISA_sha512_msk) != 0; }
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static bool has_mpmul() { return (_features & ISA_mpmul_msk) != 0; }
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static bool has_mont() { return (_features & ISA_mont_msk) != 0; }
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static bool has_pause() { return (_features & ISA_pause_msk) != 0; }
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static bool has_cbcond() { return (_features & ISA_cbcond_msk) != 0; }
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static bool has_crc32c() { return (_features & ISA_crc32c_msk) != 0; }
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static bool has_athena_plus() { return (_features & ISA_fjathplus_msk) != 0; }
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static bool has_vis3b() { return (_features & ISA_vis3b_msk) != 0; }
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static bool has_adi() { return (_features & ISA_adi_msk) != 0; }
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static bool has_sparc5() { return (_features & ISA_sparc5_msk) != 0; }
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static bool has_mwait() { return (_features & ISA_mwait_msk) != 0; }
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static bool has_xmpmul() { return (_features & ISA_xmpmul_msk) != 0; }
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static bool has_xmont() { return (_features & ISA_xmont_msk) != 0; }
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static bool has_pause_nsec() { return (_features & ISA_pause_nsec_msk) != 0; }
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static bool has_vamask() { return (_features & ISA_vamask_msk) != 0; }
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static bool has_fast_idiv() { return (_features & CPU_fast_idiv_msk) != 0; }
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static bool has_fast_rdpc() { return (_features & CPU_fast_rdpc_msk) != 0; }
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static bool has_fast_bis() { return (_features & CPU_fast_bis_msk) != 0; }
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static bool has_fast_ld() { return (_features & CPU_fast_ld_msk) != 0; }
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static bool has_fast_cmove() { return (_features & CPU_fast_cmove_msk) != 0; }
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// If indirect and direct branching is equally fast.
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static bool has_fast_ind_br() { return (_features & CPU_fast_ind_br_msk) != 0; }
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// If SPARC BIS to the beginning of cache line always zeros it.
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static bool has_blk_zeroing() { return (_features & CPU_blk_zeroing_msk) != 0; }
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static bool supports_compare_and_exchange() { return true; }
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// FIXME: To be removed.
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static bool is_post_niagara() {
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return (_features & niagara2_msk) == niagara2_msk;
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}
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// Default prefetch block size on SPARC.
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static uint prefetch_data_size() { return L2_data_cache_line_size(); }
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private:
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// Prefetch policy and characteristics:
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//
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// These support routines are used in order to isolate any CPU/core specific
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// logic from the actual flag/option processing. They should reflect the HW
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// characteristics for the associated options on the current platform.
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//
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// The three Prefetch* options below (assigned -1 in the configuration) are
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// treated according to (given the accepted range [-1..<maxint>]):
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// -1: Determine a proper HW-specific value for the current HW.
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// 0: Off
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// >0: Command-line supplied value to use.
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//
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// FIXME: The documentation string in the configuration is wrong, saying that
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// -1 is also interpreted as off.
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//
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static intx prefetch_copy_interval_in_bytes() {
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intx bytes = PrefetchCopyIntervalInBytes;
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return bytes < 0 ? 512 : bytes;
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}
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static intx prefetch_scan_interval_in_bytes() {
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intx bytes = PrefetchScanIntervalInBytes;
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return bytes < 0 ? 512 : bytes;
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}
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static intx prefetch_fields_ahead() {
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intx count = PrefetchFieldsAhead;
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return count < 0 ? 0 : count;
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}
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// AllocatePrefetchDistance is treated under the same interpretation as the
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// Prefetch* options above (i.e., -1, 0, >0).
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static intx allocate_prefetch_distance() {
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intx count = AllocatePrefetchDistance;
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return count < 0 ? 512 : count;
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}
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// AllocatePrefetchStyle is guaranteed to be in range [0..3] defined by the
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// configuration.
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static intx allocate_prefetch_style() {
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intx distance = allocate_prefetch_distance();
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// Return 0 (off/none) if AllocatePrefetchDistance was not defined.
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return distance > 0 ? AllocatePrefetchStyle : 0;
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}
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public:
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// Assembler testing
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static void allow_all();
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static void revert();
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// Override the Abstract_VM_Version implementation.
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//
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// FIXME: Removed broken test on sun4v (always false when invoked prior to the
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// proper capability setup), thus always returning 2. Still need to fix
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// this properly in order to enable complete page size support.
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static uint page_size_count() { return 2; }
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// Calculates the number of parallel threads
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static unsigned int calc_parallel_worker_threads();
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};
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#endif // CPU_SPARC_VM_VM_VERSION_SPARC_HPP
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