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https://github.com/openjdk/jdk.git
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8295270: RISC-V: Clean up and refactoring for assembler functions
Reviewed-by: fjiang, yadongwang, shade
This commit is contained in:
Fei Yang
parent
be3b335452
commit
3d75e88eb2
12 changed files with 751 additions and 713 deletions
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@ -719,7 +719,34 @@ void MacroAssembler::vfneg_v(VectorRegister vd, VectorRegister vs) {
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vfsgnjn_vv(vd, vs, vs);
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}
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void MacroAssembler::la(Register Rd, const address &dest) {
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void MacroAssembler::baseOffset32(Register Rd, const Address &adr, int32_t &offset) {
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assert(Rd != noreg, "Rd must not be empty register!");
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guarantee(Rd != adr.base(), "should use different registers!");
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if (is_offset_in_range(adr.offset(), 32)) {
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int32_t imm = adr.offset();
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int32_t upper = imm, lower = imm;
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lower = (imm << 20) >> 20;
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upper -= lower;
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lui(Rd, upper);
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offset = lower;
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} else {
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offset = ((int32_t)adr.offset() << 20) >> 20;
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li(Rd, adr.offset() - offset);
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}
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add(Rd, Rd, adr.base());
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}
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void MacroAssembler::baseOffset(Register Rd, const Address &adr, int32_t &offset) {
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if (is_offset_in_range(adr.offset(), 12)) {
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assert(Rd != noreg, "Rd must not be empty register!");
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addi(Rd, adr.base(), adr.offset());
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offset = 0;
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} else {
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baseOffset32(Rd, adr, offset);
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}
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}
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void MacroAssembler::la(Register Rd, const address dest) {
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int64_t offset = dest - pc();
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if (is_offset_in_range(offset, 32)) {
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auipc(Rd, (int32_t)offset + 0x800); //0x800, Note:the 11th sign bit
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@ -757,8 +784,210 @@ void MacroAssembler::la(Register Rd, Label &label) {
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la(Rd, target(label));
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}
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void MacroAssembler::li32(Register Rd, int32_t imm) {
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// int32_t is in range 0x8000 0000 ~ 0x7fff ffff, and imm[31] is the sign bit
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int64_t upper = imm, lower = imm;
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lower = (imm << 20) >> 20;
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upper -= lower;
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upper = (int32_t)upper;
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// lui Rd, imm[31:12] + imm[11]
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lui(Rd, upper);
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// use addiw to distinguish li32 to li64
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addiw(Rd, Rd, lower);
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}
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void MacroAssembler::li64(Register Rd, int64_t imm) {
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// Load upper 32 bits. upper = imm[63:32], but if imm[31] == 1 or
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// (imm[31:20] == 0x7ff && imm[19] == 1), upper = imm[63:32] + 1.
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int64_t lower = imm & 0xffffffff;
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lower -= ((lower << 44) >> 44);
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int64_t tmp_imm = ((uint64_t)(imm & 0xffffffff00000000)) + (uint64_t)lower;
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int32_t upper = (tmp_imm - (int32_t)lower) >> 32;
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// Load upper 32 bits
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int64_t up = upper, lo = upper;
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lo = (lo << 52) >> 52;
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up -= lo;
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up = (int32_t)up;
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lui(Rd, up);
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addi(Rd, Rd, lo);
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// Load the rest 32 bits.
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slli(Rd, Rd, 12);
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addi(Rd, Rd, (int32_t)lower >> 20);
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slli(Rd, Rd, 12);
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lower = ((int32_t)imm << 12) >> 20;
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addi(Rd, Rd, lower);
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slli(Rd, Rd, 8);
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lower = imm & 0xff;
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addi(Rd, Rd, lower);
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}
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void MacroAssembler::li(Register Rd, int64_t imm) {
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// int64_t is in range 0x8000 0000 0000 0000 ~ 0x7fff ffff ffff ffff
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// li -> c.li
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if (do_compress() && (is_imm_in_range(imm, 6, 0) && Rd != x0)) {
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c_li(Rd, imm);
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return;
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}
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int shift = 12;
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int64_t upper = imm, lower = imm;
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// Split imm to a lower 12-bit sign-extended part and the remainder,
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// because addi will sign-extend the lower imm.
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lower = ((int32_t)imm << 20) >> 20;
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upper -= lower;
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// Test whether imm is a 32-bit integer.
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if (!(((imm) & ~(int64_t)0x7fffffff) == 0 ||
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(((imm) & ~(int64_t)0x7fffffff) == ~(int64_t)0x7fffffff))) {
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while (((upper >> shift) & 1) == 0) { shift++; }
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upper >>= shift;
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li(Rd, upper);
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slli(Rd, Rd, shift);
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if (lower != 0) {
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addi(Rd, Rd, lower);
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}
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} else {
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// 32-bit integer
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Register hi_Rd = zr;
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if (upper != 0) {
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lui(Rd, (int32_t)upper);
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hi_Rd = Rd;
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}
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if (lower != 0 || hi_Rd == zr) {
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addiw(Rd, hi_Rd, lower);
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}
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}
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}
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#define INSN(NAME, REGISTER) \
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void MacroAssembler::NAME(const address dest, Register temp) { \
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assert_cond(dest != NULL); \
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int64_t distance = dest - pc(); \
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if (is_imm_in_range(distance, 20, 1)) { \
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Assembler::jal(REGISTER, distance); \
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} else { \
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assert(temp != noreg, "temp must not be empty register!"); \
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int32_t offset = 0; \
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movptr(temp, dest, offset); \
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Assembler::jalr(REGISTER, temp, offset); \
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} \
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} \
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INSN(j, x0);
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INSN(jal, x1);
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#undef INSN
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#define INSN(NAME, REGISTER) \
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void MacroAssembler::NAME(const Address &adr, Register temp) { \
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switch (adr.getMode()) { \
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case Address::literal: { \
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relocate(adr.rspec()); \
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NAME(adr.target(), temp); \
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break; \
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} \
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case Address::base_plus_offset: { \
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int32_t offset = 0; \
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baseOffset(temp, adr, offset); \
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Assembler::jalr(REGISTER, temp, offset); \
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break; \
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} \
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default: \
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ShouldNotReachHere(); \
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} \
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}
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INSN(j, x0);
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INSN(jal, x1);
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#undef INSN
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#define INSN(NAME) \
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void MacroAssembler::NAME(Register Rd, const address dest, Register temp) { \
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assert_cond(dest != NULL); \
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int64_t distance = dest - pc(); \
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if (is_imm_in_range(distance, 20, 1)) { \
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Assembler::NAME(Rd, distance); \
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} else { \
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assert_different_registers(Rd, temp); \
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int32_t offset = 0; \
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movptr(temp, dest, offset); \
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jalr(Rd, temp, offset); \
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} \
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} \
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void MacroAssembler::NAME(Register Rd, Label &L, Register temp) { \
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assert_different_registers(Rd, temp); \
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wrap_label(Rd, L, temp, &MacroAssembler::NAME); \
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}
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INSN(jal);
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#undef INSN
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#define INSN(NAME, REGISTER) \
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void MacroAssembler::NAME(Label &l, Register temp) { \
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jal(REGISTER, l, temp); \
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} \
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INSN(j, x0);
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INSN(jal, x1);
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#undef INSN
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void MacroAssembler::wrap_label(Register Rt, Label &L, Register tmp, load_insn_by_temp insn) {
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if (L.is_bound()) {
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(this->*insn)(Rt, target(L), tmp);
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} else {
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L.add_patch_at(code(), locator());
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(this->*insn)(Rt, pc(), tmp);
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}
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}
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void MacroAssembler::wrap_label(Register Rt, Label &L, jal_jalr_insn insn) {
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if (L.is_bound()) {
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(this->*insn)(Rt, target(L));
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} else {
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L.add_patch_at(code(), locator());
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(this->*insn)(Rt, pc());
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}
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}
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void MacroAssembler::wrap_label(Register r1, Register r2, Label &L,
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compare_and_branch_insn insn,
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compare_and_branch_label_insn neg_insn, bool is_far) {
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if (is_far) {
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Label done;
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(this->*neg_insn)(r1, r2, done, /* is_far */ false);
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j(L);
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bind(done);
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} else {
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if (L.is_bound()) {
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(this->*insn)(r1, r2, target(L));
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} else {
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L.add_patch_at(code(), locator());
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(this->*insn)(r1, r2, pc());
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}
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}
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}
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#define INSN(NAME, NEG_INSN) \
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void MacroAssembler::NAME(Register Rs1, Register Rs2, Label &L, bool is_far) { \
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wrap_label(Rs1, Rs2, L, &MacroAssembler::NAME, &MacroAssembler::NEG_INSN, is_far); \
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}
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INSN(beq, bne);
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INSN(bne, beq);
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INSN(blt, bge);
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INSN(bge, blt);
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INSN(bltu, bgeu);
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INSN(bgeu, bltu);
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#undef INSN
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#define INSN(NAME) \
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void MacroAssembler::NAME##z(Register Rs, const address &dest) { \
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void MacroAssembler::NAME##z(Register Rs, const address dest) { \
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NAME(Rs, zr, dest); \
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} \
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void MacroAssembler::NAME##z(Register Rs, Label &l, bool is_far) { \
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@ -774,16 +1003,31 @@ void MacroAssembler::la(Register Rd, Label &label) {
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#undef INSN
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#define INSN(NAME, NEG_INSN) \
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void MacroAssembler::NAME(Register Rs, Register Rt, const address dest) { \
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NEG_INSN(Rt, Rs, dest); \
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} \
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void MacroAssembler::NAME(Register Rs, Register Rt, Label &l, bool is_far) { \
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NEG_INSN(Rt, Rs, l, is_far); \
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}
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INSN(bgt, blt);
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INSN(ble, bge);
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INSN(bgtu, bltu);
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INSN(bleu, bgeu);
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#undef INSN
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// Float compare branch instructions
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#define INSN(NAME, FLOATCMP, BRANCH) \
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void MacroAssembler::float_##NAME(FloatRegister Rs1, FloatRegister Rs2, Label &l, bool is_far, bool is_unordered) { \
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FLOATCMP##_s(t0, Rs1, Rs2); \
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BRANCH(t0, l, is_far); \
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} \
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void MacroAssembler::double_##NAME(FloatRegister Rs1, FloatRegister Rs2, Label &l, bool is_far, bool is_unordered) { \
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FLOATCMP##_d(t0, Rs1, Rs2); \
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BRANCH(t0, l, is_far); \
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#define INSN(NAME, FLOATCMP, BRANCH) \
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void MacroAssembler::float_##NAME(FloatRegister Rs1, FloatRegister Rs2, Label &l, bool is_far, bool is_unordered) { \
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FLOATCMP##_s(t0, Rs1, Rs2); \
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BRANCH(t0, l, is_far); \
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} \
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void MacroAssembler::double_##NAME(FloatRegister Rs1, FloatRegister Rs2, Label &l, bool is_far, bool is_unordered) { \
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FLOATCMP##_d(t0, Rs1, Rs2); \
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BRANCH(t0, l, is_far); \
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}
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INSN(beq, feq, bnez);
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@ -928,7 +1172,7 @@ void MacroAssembler::push_reg(Register Rs)
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void MacroAssembler::pop_reg(Register Rd)
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{
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ld(Rd, esp, 0);
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ld(Rd, Address(esp, 0));
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addi(esp, esp, wordSize);
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}
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@ -1361,6 +1605,85 @@ void MacroAssembler::mv(Register Rd, RegisterOrConstant src) {
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}
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}
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void MacroAssembler::movptr(Register Rd, address addr, int32_t &offset) {
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int64_t imm64 = (int64_t)addr;
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#ifndef PRODUCT
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{
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char buffer[64];
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snprintf(buffer, sizeof(buffer), "0x%" PRIx64, imm64);
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block_comment(buffer);
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}
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#endif
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assert(is_unsigned_imm_in_range(imm64, 47, 0) || (imm64 == (int64_t)-1),
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"bit 47 overflows in address constant");
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// Load upper 31 bits
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int64_t imm = imm64 >> 17;
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int64_t upper = imm, lower = imm;
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lower = (lower << 52) >> 52;
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upper -= lower;
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upper = (int32_t)upper;
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lui(Rd, upper);
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addi(Rd, Rd, lower);
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// Load the rest 17 bits.
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slli(Rd, Rd, 11);
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addi(Rd, Rd, (imm64 >> 6) & 0x7ff);
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slli(Rd, Rd, 6);
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// This offset will be used by following jalr/ld.
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offset = imm64 & 0x3f;
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}
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void MacroAssembler::movptr(Register Rd, uintptr_t imm64) {
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movptr(Rd, (address)imm64);
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}
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void MacroAssembler::movptr(Register Rd, address addr) {
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int offset = 0;
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movptr(Rd, addr, offset);
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addi(Rd, Rd, offset);
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}
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void MacroAssembler::add(Register Rd, Register Rn, int64_t increment, Register temp) {
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if (is_imm_in_range(increment, 12, 0)) {
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addi(Rd, Rn, increment);
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} else {
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assert_different_registers(Rn, temp);
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li(temp, increment);
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add(Rd, Rn, temp);
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}
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}
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void MacroAssembler::addw(Register Rd, Register Rn, int32_t increment, Register temp) {
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if (is_imm_in_range(increment, 12, 0)) {
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addiw(Rd, Rn, increment);
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} else {
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assert_different_registers(Rn, temp);
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li(temp, increment);
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addw(Rd, Rn, temp);
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}
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}
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void MacroAssembler::sub(Register Rd, Register Rn, int64_t decrement, Register temp) {
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if (is_imm_in_range(-decrement, 12, 0)) {
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addi(Rd, Rn, -decrement);
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} else {
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assert_different_registers(Rn, temp);
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li(temp, decrement);
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sub(Rd, Rn, temp);
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}
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}
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void MacroAssembler::subw(Register Rd, Register Rn, int32_t decrement, Register temp) {
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if (is_imm_in_range(-decrement, 12, 0)) {
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addiw(Rd, Rn, -decrement);
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} else {
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assert_different_registers(Rn, temp);
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li(temp, decrement);
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subw(Rd, Rn, temp);
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}
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}
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void MacroAssembler::andrw(Register Rd, Register Rs1, Register Rs2) {
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andr(Rd, Rs1, Rs2);
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// addw: The result is clipped to 32 bits, then the sign bit is extended,
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@ -3858,7 +4181,7 @@ void MacroAssembler::zero_memory(Register addr, Register len, Register tmp) {
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bind(loop);
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sub(len, len, unroll);
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for (int i = -unroll; i < 0; i++) {
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Assembler::sd(zr, Address(tmp, i * wordSize));
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sd(zr, Address(tmp, i * wordSize));
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}
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bind(entry);
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add(tmp, tmp, unroll * wordSize);
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