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8328986: Deprecate UseRTM* flags for removal
Co-authored-by: Roman Kennke <rkennke@openjdk.org> Reviewed-by: vlivanov, sviswanathan, dholmes
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0cb0b5db2a
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4 changed files with 96 additions and 81 deletions
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@ -2477,24 +2477,6 @@ This option has a limit of 2 GB; otherwise, an error is generated.
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The maximum code cache size shouldn\[aq]t be less than the initial code
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cache size; see the option \f[V]-XX:InitialCodeCacheSize\f[R].
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.TP
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\f[V]-XX:RTMAbortRatio=\f[R]\f[I]abort_ratio\f[R]
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Specifies the RTM abort ratio is specified as a percentage (%) of all
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executed RTM transactions.
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If a number of aborted transactions becomes greater than this ratio,
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then the compiled code is deoptimized.
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This ratio is used when the \f[V]-XX:+UseRTMDeopt\f[R] option is
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enabled.
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The default value of this option is 50.
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This means that the compiled code is deoptimized if 50% of all
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transactions are aborted.
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.TP
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\f[V]-XX:RTMRetryCount=\f[R]\f[I]number_of_retries\f[R]
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Specifies the number of times that the RTM locking code is retried, when
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it is aborted or busy, before falling back to the normal locking
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mechanism.
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The default value for this option is 5.
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The \f[V]-XX:UseRTMLocking\f[R] option must be enabled.
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.TP
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\f[V]-XX:+SegmentedCodeCache\f[R]
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Enables segmentation of the code cache, without which the code cache
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consists of one large segment.
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@ -2728,65 +2710,6 @@ FMA intrinsics are generated for the
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value of \f[V](\f[R] \f[I]a\f[R] \f[V]*\f[R] \f[I]b\f[R] \f[V]+\f[R]
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\f[I]c\f[R] \f[V])\f[R] expressions.
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.TP
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\f[V]-XX:+UseRTMDeopt\f[R]
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Autotunes RTM locking depending on the abort ratio.
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This ratio is specified by the \f[V]-XX:RTMAbortRatio\f[R] option.
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If the number of aborted transactions exceeds the abort ratio, then the
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method containing the lock is deoptimized and recompiled with all locks
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as normal locks.
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This option is disabled by default.
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The \f[V]-XX:+UseRTMLocking\f[R] option must be enabled.
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.TP
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\f[V]-XX:+UseRTMLocking\f[R]
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Generates Restricted Transactional Memory (RTM) locking code for all
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inflated locks, with the normal locking mechanism as the fallback
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handler.
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This option is disabled by default.
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Options related to RTM are available only on x86 CPUs that support
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Transactional Synchronization Extensions (TSX).
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.RS
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.PP
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RTM is part of Intel\[aq]s TSX, which is an x86 instruction set
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extension and facilitates the creation of multithreaded applications.
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RTM introduces the new instructions \f[V]XBEGIN\f[R], \f[V]XABORT\f[R],
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\f[V]XEND\f[R], and \f[V]XTEST\f[R].
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The \f[V]XBEGIN\f[R] and \f[V]XEND\f[R] instructions enclose a set of
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instructions to run as a transaction.
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If no conflict is found when running the transaction, then the memory
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and register modifications are committed together at the \f[V]XEND\f[R]
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instruction.
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The \f[V]XABORT\f[R] instruction can be used to explicitly abort a
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transaction and the \f[V]XTEST\f[R] instruction checks if a set of
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instructions is being run in a transaction.
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.PP
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A lock on a transaction is inflated when another thread tries to access
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the same transaction, thereby blocking the thread that didn\[aq]t
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originally request access to the transaction.
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RTM requires that a fallback set of operations be specified in case a
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transaction aborts or fails.
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An RTM lock is a lock that has been delegated to the TSX\[aq]s system.
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.PP
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RTM improves performance for highly contended locks with low conflict in
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a critical region (which is code that must not be accessed by more than
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one thread concurrently).
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RTM also improves the performance of coarse-grain locking, which
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typically doesn\[aq]t perform well in multithreaded applications.
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(Coarse-grain locking is the strategy of holding locks for long periods
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to minimize the overhead of taking and releasing locks, while
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fine-grained locking is the strategy of trying to achieve maximum
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parallelism by locking only when necessary and unlocking as soon as
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possible.)
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Also, for lightly contended locks that are used by different threads,
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RTM can reduce false cache line sharing, also known as cache line
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ping-pong.
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This occurs when multiple threads from different processors are
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accessing different resources, but the resources share the same cache
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line.
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As a result, the processors repeatedly invalidate the cache lines of
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other processors, which forces them to read from main memory instead of
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their cache.
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.RE
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.TP
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\f[V]-XX:+UseSuperWord\f[R]
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Enables the transformation of scalar operations into superword
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operations.
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@ -3825,6 +3748,83 @@ The default value is 2.
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.PP
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Use the option \f[V]-XX:MinRAMPercentage\f[R] instead.
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.RE
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.TP
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\f[V]-XX:RTMAbortRatio=\f[R]\f[I]abort_ratio\f[R]
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Specifies the RTM abort ratio is specified as a percentage (%) of all
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executed RTM transactions.
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If a number of aborted transactions becomes greater than this ratio,
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then the compiled code is deoptimized.
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This ratio is used when the \f[V]-XX:+UseRTMDeopt\f[R] option is
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enabled.
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The default value of this option is 50.
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This means that the compiled code is deoptimized if 50% of all
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transactions are aborted.
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.TP
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\f[V]-XX:RTMRetryCount=\f[R]\f[I]number_of_retries\f[R]
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Specifies the number of times that the RTM locking code is retried, when
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it is aborted or busy, before falling back to the normal locking
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mechanism.
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The default value for this option is 5.
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The \f[V]-XX:UseRTMLocking\f[R] option must be enabled.
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.TP
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\f[V]-XX:+UseRTMDeopt\f[R]
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Autotunes RTM locking depending on the abort ratio.
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This ratio is specified by the \f[V]-XX:RTMAbortRatio\f[R] option.
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If the number of aborted transactions exceeds the abort ratio, then the
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method containing the lock is deoptimized and recompiled with all locks
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as normal locks.
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This option is disabled by default.
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The \f[V]-XX:+UseRTMLocking\f[R] option must be enabled.
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.TP
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\f[V]-XX:+UseRTMLocking\f[R]
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Generates Restricted Transactional Memory (RTM) locking code for all
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inflated locks, with the normal locking mechanism as the fallback
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handler.
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This option is disabled by default.
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Options related to RTM are available only on x86 CPUs that support
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Transactional Synchronization Extensions (TSX).
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.RS
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.PP
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RTM is part of Intel\[aq]s TSX, which is an x86 instruction set
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extension and facilitates the creation of multithreaded applications.
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RTM introduces the new instructions \f[V]XBEGIN\f[R], \f[V]XABORT\f[R],
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\f[V]XEND\f[R], and \f[V]XTEST\f[R].
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The \f[V]XBEGIN\f[R] and \f[V]XEND\f[R] instructions enclose a set of
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instructions to run as a transaction.
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If no conflict is found when running the transaction, then the memory
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and register modifications are committed together at the \f[V]XEND\f[R]
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instruction.
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The \f[V]XABORT\f[R] instruction can be used to explicitly abort a
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transaction and the \f[V]XTEST\f[R] instruction checks if a set of
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instructions is being run in a transaction.
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.PP
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A lock on a transaction is inflated when another thread tries to access
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the same transaction, thereby blocking the thread that didn\[aq]t
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originally request access to the transaction.
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RTM requires that a fallback set of operations be specified in case a
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transaction aborts or fails.
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An RTM lock is a lock that has been delegated to the TSX\[aq]s system.
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.PP
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RTM improves performance for highly contended locks with low conflict in
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a critical region (which is code that must not be accessed by more than
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one thread concurrently).
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RTM also improves the performance of coarse-grain locking, which
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typically doesn\[aq]t perform well in multithreaded applications.
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(Coarse-grain locking is the strategy of holding locks for long periods
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to minimize the overhead of taking and releasing locks, while
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fine-grained locking is the strategy of trying to achieve maximum
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parallelism by locking only when necessary and unlocking as soon as
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possible.)
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Also, for lightly contended locks that are used by different threads,
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RTM can reduce false cache line sharing, also known as cache line
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ping-pong.
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This occurs when multiple threads from different processors are
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accessing different resources, but the resources share the same cache
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line.
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As a result, the processors repeatedly invalidate the cache lines of
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other processors, which forces them to read from main memory instead of
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their cache.
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.RE
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.SH OBSOLETE JAVA OPTIONS
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.PP
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These \f[V]java\f[R] options are still accepted but ignored, and a
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