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8154473: Update for CompilerDirectives to control stub generation and intrinsics
Use -XX:DisableIntrinsic flag to control intrinsics usage in Interpreter. Reviewed-by: twisti, neliasso, kvn, simonis
This commit is contained in:
Vivek Deshpande
parent
6dfcf1dd81
commit
489b38091e
9 changed files with 144 additions and 298 deletions
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@ -2584,6 +2584,11 @@ void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, in
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}
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// Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
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void MacroAssembler::call_VM_leaf0(address entry_point) {
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MacroAssembler::call_VM_leaf_base(entry_point, 0);
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}
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void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
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call_VM_leaf_base(entry_point, number_of_arguments);
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}
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@ -5629,235 +5634,6 @@ void MacroAssembler::incr_allocated_bytes(Register thread,
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#endif
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}
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void MacroAssembler::fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use) {
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pusha();
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// if we are coming from c1, xmm registers may be live
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int num_xmm_regs = LP64_ONLY(16) NOT_LP64(8);
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if (UseAVX > 2) {
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num_xmm_regs = LP64_ONLY(32) NOT_LP64(8);
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}
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if (UseSSE == 1) {
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subptr(rsp, sizeof(jdouble)*8);
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for (int n = 0; n < 8; n++) {
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movflt(Address(rsp, n*sizeof(jdouble)), as_XMMRegister(n));
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}
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} else if (UseSSE >= 2) {
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if (UseAVX > 2) {
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push(rbx);
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movl(rbx, 0xffff);
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kmovwl(k1, rbx);
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pop(rbx);
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}
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#ifdef COMPILER2
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if (MaxVectorSize > 16) {
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if(UseAVX > 2) {
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// Save upper half of ZMM registers
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subptr(rsp, 32*num_xmm_regs);
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for (int n = 0; n < num_xmm_regs; n++) {
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vextractf64x4_high(Address(rsp, n*32), as_XMMRegister(n));
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}
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}
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assert(UseAVX > 0, "256 bit vectors are supported only with AVX");
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// Save upper half of YMM registers
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subptr(rsp, 16*num_xmm_regs);
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for (int n = 0; n < num_xmm_regs; n++) {
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vextractf128_high(Address(rsp, n*16), as_XMMRegister(n));
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}
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}
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#endif
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// Save whole 128bit (16 bytes) XMM registers
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subptr(rsp, 16*num_xmm_regs);
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#ifdef _LP64
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if (VM_Version::supports_evex()) {
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for (int n = 0; n < num_xmm_regs; n++) {
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vextractf32x4(Address(rsp, n*16), as_XMMRegister(n), 0);
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}
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} else {
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for (int n = 0; n < num_xmm_regs; n++) {
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movdqu(Address(rsp, n*16), as_XMMRegister(n));
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}
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}
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#else
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for (int n = 0; n < num_xmm_regs; n++) {
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movdqu(Address(rsp, n*16), as_XMMRegister(n));
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}
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#endif
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}
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// Preserve registers across runtime call
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int incoming_argument_and_return_value_offset = -1;
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if (num_fpu_regs_in_use > 1) {
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// Must preserve all other FPU regs (could alternatively convert
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// SharedRuntime::dsin, dcos etc. into assembly routines known not to trash
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// FPU state, but can not trust C compiler)
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NEEDS_CLEANUP;
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// NOTE that in this case we also push the incoming argument(s) to
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// the stack and restore it later; we also use this stack slot to
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// hold the return value from dsin, dcos etc.
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for (int i = 0; i < num_fpu_regs_in_use; i++) {
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subptr(rsp, sizeof(jdouble));
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fstp_d(Address(rsp, 0));
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}
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incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1);
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for (int i = nb_args-1; i >= 0; i--) {
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fld_d(Address(rsp, incoming_argument_and_return_value_offset-i*sizeof(jdouble)));
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}
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}
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subptr(rsp, nb_args*sizeof(jdouble));
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for (int i = 0; i < nb_args; i++) {
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fstp_d(Address(rsp, i*sizeof(jdouble)));
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}
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#ifdef _LP64
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if (nb_args > 0) {
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movdbl(xmm0, Address(rsp, 0));
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}
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if (nb_args > 1) {
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movdbl(xmm1, Address(rsp, sizeof(jdouble)));
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}
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assert(nb_args <= 2, "unsupported number of args");
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#endif // _LP64
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// NOTE: we must not use call_VM_leaf here because that requires a
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// complete interpreter frame in debug mode -- same bug as 4387334
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// MacroAssembler::call_VM_leaf_base is perfectly safe and will
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// do proper 64bit abi
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NEEDS_CLEANUP;
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// Need to add stack banging before this runtime call if it needs to
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// be taken; however, there is no generic stack banging routine at
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// the MacroAssembler level
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MacroAssembler::call_VM_leaf_base(runtime_entry, 0);
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#ifdef _LP64
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movsd(Address(rsp, 0), xmm0);
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fld_d(Address(rsp, 0));
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#endif // _LP64
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addptr(rsp, sizeof(jdouble)*nb_args);
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if (num_fpu_regs_in_use > 1) {
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// Must save return value to stack and then restore entire FPU
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// stack except incoming arguments
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fstp_d(Address(rsp, incoming_argument_and_return_value_offset));
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for (int i = 0; i < num_fpu_regs_in_use - nb_args; i++) {
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fld_d(Address(rsp, 0));
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addptr(rsp, sizeof(jdouble));
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}
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fld_d(Address(rsp, (nb_args-1)*sizeof(jdouble)));
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addptr(rsp, sizeof(jdouble)*nb_args);
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}
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if (UseSSE == 1) {
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for (int n = 0; n < 8; n++) {
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movflt(as_XMMRegister(n), Address(rsp, n*sizeof(jdouble)));
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}
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addptr(rsp, sizeof(jdouble)*8);
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} else if (UseSSE >= 2) {
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// Restore whole 128bit (16 bytes) XMM registers
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#ifdef _LP64
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if (VM_Version::supports_evex()) {
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for (int n = 0; n < num_xmm_regs; n++) {
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vinsertf32x4(as_XMMRegister(n), as_XMMRegister(n), Address(rsp, n*16), 0);
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}
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} else {
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for (int n = 0; n < num_xmm_regs; n++) {
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movdqu(as_XMMRegister(n), Address(rsp, n*16));
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}
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}
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#else
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for (int n = 0; n < num_xmm_regs; n++) {
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movdqu(as_XMMRegister(n), Address(rsp, n*16));
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}
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#endif
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addptr(rsp, 16*num_xmm_regs);
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#ifdef COMPILER2
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if (MaxVectorSize > 16) {
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// Restore upper half of YMM registers.
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for (int n = 0; n < num_xmm_regs; n++) {
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vinsertf128_high(as_XMMRegister(n), Address(rsp, n*16));
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}
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addptr(rsp, 16*num_xmm_regs);
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if(UseAVX > 2) {
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for (int n = 0; n < num_xmm_regs; n++) {
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vinsertf64x4_high(as_XMMRegister(n), Address(rsp, n*32));
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}
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addptr(rsp, 32*num_xmm_regs);
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}
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}
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#endif
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}
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popa();
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}
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static const double pi_4 = 0.7853981633974483;
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void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) {
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// A hand-coded argument reduction for values in fabs(pi/4, pi/2)
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// was attempted in this code; unfortunately it appears that the
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// switch to 80-bit precision and back causes this to be
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// unprofitable compared with simply performing a runtime call if
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// the argument is out of the (-pi/4, pi/4) range.
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Register tmp = noreg;
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if (!VM_Version::supports_cmov()) {
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// fcmp needs a temporary so preserve rbx,
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tmp = rbx;
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push(tmp);
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}
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Label slow_case, done;
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if (trig == 't') {
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ExternalAddress pi4_adr = (address)&pi_4;
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if (reachable(pi4_adr)) {
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// x ?<= pi/4
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fld_d(pi4_adr);
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fld_s(1); // Stack: X PI/4 X
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fabs(); // Stack: |X| PI/4 X
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fcmp(tmp);
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jcc(Assembler::above, slow_case);
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// fastest case: -pi/4 <= x <= pi/4
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ftan();
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jmp(done);
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}
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}
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// slow case: runtime call
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bind(slow_case);
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switch(trig) {
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case 's':
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{
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fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 1, num_fpu_regs_in_use);
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}
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break;
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case 'c':
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{
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fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 1, num_fpu_regs_in_use);
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}
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break;
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case 't':
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{
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fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 1, num_fpu_regs_in_use);
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}
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break;
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default:
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assert(false, "bad intrinsic");
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break;
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}
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// Come here with result in F-TOS
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bind(done);
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if (tmp != noreg) {
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pop(tmp);
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}
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}
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// Look up the method for a megamorphic invokeinterface call.
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// The target method is determined by <intf_klass, itable_index>.
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// The receiver klass is in recv_klass.
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