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7063628: Use cbcond on T4
Add new short branch instruction to Hotspot sparc assembler. Reviewed-by: never, twisti, jrose
This commit is contained in:
Vladimir Kozlov
parent
aa16309657
commit
48c1293916
30 changed files with 966 additions and 1097 deletions
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@ -761,7 +761,7 @@ class Assembler : public AbstractAssembler {
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mwtos_opf = 0x119
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};
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enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7 };
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enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7, rc_last = rc_gez };
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enum Condition {
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// for FBfcc & FBPfcc instruction
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@ -866,9 +866,18 @@ class Assembler : public AbstractAssembler {
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return is_simm(d, nbits + 2);
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}
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address target_distance(Label& L) {
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// Assembler::target(L) should be called only when
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// a branch instruction is emitted since non-bound
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// labels record current pc() as a branch address.
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if (L.is_bound()) return target(L);
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// Return current address for non-bound labels.
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return pc();
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}
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// test if label is in simm16 range in words (wdisp16).
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bool is_in_wdisp16_range(Label& L) {
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return is_in_wdisp_range(target(L), pc(), 16);
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return is_in_wdisp_range(target_distance(L), pc(), 16);
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}
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// test if the distance between two addresses fits in simm30 range in words
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static bool is_in_wdisp30_range(address a, address b) {
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@ -975,6 +984,20 @@ class Assembler : public AbstractAssembler {
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static int sx( int i) { return u_field(i, 12, 12); } // shift x=1 means 64-bit
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static int opf( int x) { return u_field(x, 13, 5); }
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static bool is_cbcond( int x ) {
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return (VM_Version::has_cbcond() && (inv_cond(x) > rc_last) &&
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inv_op(x) == branch_op && inv_op2(x) == bpr_op2);
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}
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static bool is_cxb( int x ) {
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assert(is_cbcond(x), "wrong instruction");
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return (x & (1<<21)) != 0;
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}
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static int cond_cbcond( int x) { return u_field((((x & 8)<<1) + 8 + (x & 7)), 29, 25); }
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static int inv_cond_cbcond(int x) {
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assert(is_cbcond(x), "wrong instruction");
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return inv_u_field(x, 27, 25) | (inv_u_field(x, 29, 29)<<3);
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}
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static int opf_cc( CC c, bool useFloat ) { return u_field((useFloat ? 0 : 4) + c, 13, 11); }
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static int mov_cc( CC c, bool useFloat ) { return u_field(useFloat ? 0 : 1, 18, 18) | u_field(c, 12, 11); }
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@ -1026,6 +1049,26 @@ class Assembler : public AbstractAssembler {
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return r;
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}
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// compute inverse of wdisp10
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static intptr_t inv_wdisp10(int x, intptr_t pos) {
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assert(is_cbcond(x), "wrong instruction");
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int lo = inv_u_field(x, 12, 5);
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int hi = (x >> 19) & 3;
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if (hi >= 2) hi |= ~1;
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return (((hi << 8) | lo) << 2) + pos;
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}
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// word offset for cbcond, 8 bits at [B12,B5], 2 bits at [B20,B19]
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static int wdisp10(intptr_t x, intptr_t off) {
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assert(VM_Version::has_cbcond(), "This CPU does not have CBCOND instruction");
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intptr_t xx = x - off;
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assert_signed_word_disp_range(xx, 10);
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int r = ( ( (xx >> 2 ) & ((1 << 8) - 1) ) << 5 )
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| ( ( (xx >> (2+8)) & 3 ) << 19 );
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// Have to fake cbcond instruction to pass assert in inv_wdisp10()
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assert(inv_wdisp10((r | op(branch_op) | cond_cbcond(rc_last+1) | op2(bpr_op2)), off) == x, "inverse is not inverse");
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return r;
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}
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// word displacement in low-order nbits bits
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@ -1138,6 +1181,24 @@ class Assembler : public AbstractAssembler {
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#endif
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}
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// cbcond instruction should not be generated one after an other
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bool cbcond_before() {
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if (offset() == 0) return false; // it is first instruction
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int x = *(int*)(intptr_t(pc()) - 4); // previous instruction
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return is_cbcond(x);
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}
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void no_cbcond_before() {
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assert(offset() == 0 || !cbcond_before(), "cbcond should not follow an other cbcond");
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}
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bool use_cbcond(Label& L) {
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if (!UseCBCond || cbcond_before()) return false;
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intptr_t x = intptr_t(target_distance(L)) - intptr_t(pc());
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assert( (x & 3) == 0, "not word aligned");
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return is_simm(x, 12);
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}
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public:
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// Tells assembler you know that next instruction is delayed
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Assembler* delayed() {
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@ -1181,10 +1242,11 @@ public:
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void addccc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
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void addccc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
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// pp 136
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inline void bpr( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none );
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inline void bpr( RCondition c, bool a, Predict p, Register s1, Label& L);
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inline void bpr(RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none);
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inline void bpr(RCondition c, bool a, Predict p, Register s1, Label& L);
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protected: // use MacroAssembler::br instead
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@ -1198,8 +1260,6 @@ public:
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inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
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inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
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public:
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// pp 144
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inline void br( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
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@ -1215,11 +1275,17 @@ public:
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inline void cb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
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inline void cb( Condition c, bool a, Label& L );
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// compare and branch
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inline void cbcond(Condition c, CC cc, Register s1, Register s2, Label& L);
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inline void cbcond(Condition c, CC cc, Register s1, int simm5, Label& L);
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// pp 149
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inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type );
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inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type );
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public:
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// pp 150
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// These instructions compare the contents of s2 with the contents of
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@ -1862,8 +1928,8 @@ class MacroAssembler: public Assembler {
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inline void fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
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inline void fb( Condition c, bool a, Predict p, Label& L );
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// compares register with zero and branches (V9 and V8 instructions)
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void br_zero( Condition c, bool a, Predict p, Register s1, Label& L);
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// compares register with zero (32 bit) and branches (V9 and V8 instructions)
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void cmp_zero_and_br( Condition c, Register s1, Label& L, bool a = false, Predict p = pn );
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// Compares a pointer register with zero and branches on (not)null.
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// Does a test & branch on 32-bit systems and a register-branch on 64-bit.
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void br_null ( Register s1, bool a, Predict p, Label& L );
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@ -1875,6 +1941,26 @@ class MacroAssembler: public Assembler {
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void br_on_reg_cond( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none );
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void br_on_reg_cond( RCondition c, bool a, Predict p, Register s1, Label& L);
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//
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// Compare registers and branch with nop in delay slot or cbcond without delay slot.
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//
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// ATTENTION: use these instructions with caution because cbcond instruction
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// has very short distance: 512 instructions (2Kbyte).
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// Compare integer (32 bit) values (icc only).
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void cmp_and_br_short(Register s1, Register s2, Condition c, Predict p, Label& L);
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void cmp_and_br_short(Register s1, int simm13a, Condition c, Predict p, Label& L);
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// Platform depending version for pointer compare (icc on !LP64 and xcc on LP64).
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void cmp_and_brx_short(Register s1, Register s2, Condition c, Predict p, Label& L);
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void cmp_and_brx_short(Register s1, int simm13a, Condition c, Predict p, Label& L);
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// Short branch version for compares a pointer pwith zero.
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void br_null_short ( Register s1, Predict p, Label& L );
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void br_notnull_short( Register s1, Predict p, Label& L );
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// unconditional short branch
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void ba_short(Label& L);
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inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
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inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
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@ -1882,8 +1968,8 @@ class MacroAssembler: public Assembler {
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inline void brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
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inline void brx( Condition c, bool a, Predict p, Label& L );
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// unconditional short branch
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inline void ba( bool a, Label& L );
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// unconditional branch
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inline void ba( Label& L );
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// Branch that tests fp condition codes
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inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
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@ -2167,7 +2253,6 @@ public:
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inline void stbool(Register d, const Address& a) { stb(d, a); }
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inline void ldbool(const Address& a, Register d) { ldsb(a, d); }
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inline void tstbool( Register s ) { tst(s); }
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inline void movbool( bool boolconst, Register d) { mov( (int) boolconst, d); }
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// klass oop manipulations if compressed
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@ -2469,8 +2554,7 @@ public:
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Label* L_success,
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Label* L_failure,
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Label* L_slow_path,
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RegisterOrConstant super_check_offset = RegisterOrConstant(-1),
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Register instanceof_hack = noreg);
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RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
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// The rest of the type check; must be wired to a corresponding fast path.
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// It does not repeat the fast path logic, so don't use it standalone.
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