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7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
For C2 moved saving EBP after ESP adjustment. For C1 generated 5 byte nop instruction first if needed. Reviewed-by: never, twisti, azeemj
This commit is contained in:
Vladimir Kozlov
parent
24b07e7ae6
commit
539616f85a
6 changed files with 205 additions and 207 deletions
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@ -236,6 +236,16 @@ void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
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}
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}
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// Force generation of a 4 byte immediate value even if it fits into 8bit
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void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
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assert(isByte(op1) && isByte(op2), "wrong opcode");
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assert((op1 & 0x01) == 1, "should be 32bit operation");
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assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
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emit_byte(op1);
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emit_byte(op2 | encode(dst));
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emit_long(imm32);
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}
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// immediate-to-memory forms
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void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
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assert((op1 & 0x01) == 1, "should be 32bit operation");
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@ -939,6 +949,7 @@ void Assembler::addl(Register dst, Register src) {
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}
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void Assembler::addr_nop_4() {
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assert(UseAddressNop, "no CPU support");
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// 4 bytes: NOP DWORD PTR [EAX+0]
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emit_byte(0x0F);
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emit_byte(0x1F);
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@ -947,6 +958,7 @@ void Assembler::addr_nop_4() {
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}
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void Assembler::addr_nop_5() {
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assert(UseAddressNop, "no CPU support");
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// 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
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emit_byte(0x0F);
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emit_byte(0x1F);
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@ -956,6 +968,7 @@ void Assembler::addr_nop_5() {
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}
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void Assembler::addr_nop_7() {
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assert(UseAddressNop, "no CPU support");
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// 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
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emit_byte(0x0F);
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emit_byte(0x1F);
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@ -964,6 +977,7 @@ void Assembler::addr_nop_7() {
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}
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void Assembler::addr_nop_8() {
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assert(UseAddressNop, "no CPU support");
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// 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
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emit_byte(0x0F);
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emit_byte(0x1F);
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@ -2769,6 +2783,12 @@ void Assembler::subl(Register dst, int32_t imm32) {
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emit_arith(0x81, 0xE8, dst, imm32);
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}
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// Force generation of a 4 byte immediate value even if it fits into 8bit
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void Assembler::subl_imm32(Register dst, int32_t imm32) {
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prefix(dst);
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emit_arith_imm32(0x81, 0xE8, dst, imm32);
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}
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void Assembler::subl(Register dst, Address src) {
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InstructionMark im(this);
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prefix(src, dst);
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@ -4760,6 +4780,12 @@ void Assembler::subq(Register dst, int32_t imm32) {
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emit_arith(0x81, 0xE8, dst, imm32);
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}
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// Force generation of a 4 byte immediate value even if it fits into 8bit
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void Assembler::subq_imm32(Register dst, int32_t imm32) {
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(void) prefixq_and_encode(dst->encoding());
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emit_arith_imm32(0x81, 0xE8, dst, imm32);
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}
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void Assembler::subq(Register dst, Address src) {
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InstructionMark im(this);
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prefixq(src, dst);
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@ -5101,15 +5127,6 @@ void MacroAssembler::extend_sign(Register hi, Register lo) {
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}
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}
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void MacroAssembler::fat_nop() {
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// A 5 byte nop that is safe for patching (see patch_verified_entry)
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emit_byte(0x26); // es:
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emit_byte(0x2e); // cs:
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emit_byte(0x64); // fs:
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emit_byte(0x65); // gs:
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emit_byte(0x90);
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}
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void MacroAssembler::jC2(Register tmp, Label& L) {
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// set parity bit if FPU flag C2 is set (via rax)
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save_rax(tmp);
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@ -5704,17 +5721,6 @@ void MacroAssembler::decrementq(Address dst, int value) {
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/* else */ { subq(dst, value) ; return; }
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}
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void MacroAssembler::fat_nop() {
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// A 5 byte nop that is safe for patching (see patch_verified_entry)
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// Recommened sequence from 'Software Optimization Guide for the AMD
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// Hammer Processor'
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emit_byte(0x66);
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emit_byte(0x66);
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emit_byte(0x90);
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emit_byte(0x66);
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emit_byte(0x90);
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}
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void MacroAssembler::incrementq(Register reg, int value) {
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if (value == min_jint) { addq(reg, value); return; }
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if (value < 0) { decrementq(reg, -value); return; }
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@ -6766,6 +6772,19 @@ void MacroAssembler::enter() {
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mov(rbp, rsp);
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}
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// A 5 byte nop that is safe for patching (see patch_verified_entry)
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void MacroAssembler::fat_nop() {
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if (UseAddressNop) {
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addr_nop_5();
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} else {
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emit_byte(0x26); // es:
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emit_byte(0x2e); // cs:
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emit_byte(0x64); // fs:
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emit_byte(0x65); // gs:
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emit_byte(0x90);
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}
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}
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void MacroAssembler::fcmp(Register tmp) {
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fcmp(tmp, 1, true, true);
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}
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@ -7825,6 +7844,11 @@ void MacroAssembler::subptr(Register dst, int32_t imm32) {
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LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
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}
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// Force generation of a 4 byte immediate value even if it fits into 8bit
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void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
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LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
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}
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void MacroAssembler::subptr(Register dst, Register src) {
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LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
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}
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@ -9292,6 +9316,80 @@ void MacroAssembler::reinit_heapbase() {
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}
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#endif // _LP64
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// C2 compiled method's prolog code.
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void MacroAssembler::verified_entry(int framesize, bool stack_bang, bool fp_mode_24b) {
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// WARNING: Initial instruction MUST be 5 bytes or longer so that
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// NativeJump::patch_verified_entry will be able to patch out the entry
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// code safely. The push to verify stack depth is ok at 5 bytes,
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// the frame allocation can be either 3 or 6 bytes. So if we don't do
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// stack bang then we must use the 6 byte frame allocation even if
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// we have no frame. :-(
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assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
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// Remove word for return addr
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framesize -= wordSize;
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// Calls to C2R adapters often do not accept exceptional returns.
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// We require that their callers must bang for them. But be careful, because
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// some VM calls (such as call site linkage) can use several kilobytes of
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// stack. But the stack safety zone should account for that.
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// See bugs 4446381, 4468289, 4497237.
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if (stack_bang) {
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generate_stack_overflow_check(framesize);
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// We always push rbp, so that on return to interpreter rbp, will be
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// restored correctly and we can correct the stack.
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push(rbp);
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// Remove word for ebp
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framesize -= wordSize;
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// Create frame
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if (framesize) {
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subptr(rsp, framesize);
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}
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} else {
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// Create frame (force generation of a 4 byte immediate value)
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subptr_imm32(rsp, framesize);
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// Save RBP register now.
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framesize -= wordSize;
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movptr(Address(rsp, framesize), rbp);
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}
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if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
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framesize -= wordSize;
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movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
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}
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#ifndef _LP64
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// If method sets FPU control word do it now
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if (fp_mode_24b) {
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fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
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}
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if (UseSSE >= 2 && VerifyFPU) {
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verify_FPU(0, "FPU stack must be clean on entry");
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}
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#endif
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#ifdef ASSERT
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if (VerifyStackAtCalls) {
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Label L;
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push(rax);
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mov(rax, rsp);
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andptr(rax, StackAlignmentInBytes-1);
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cmpptr(rax, StackAlignmentInBytes-wordSize);
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pop(rax);
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jcc(Assembler::equal, L);
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stop("Stack is not properly aligned!");
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bind(L);
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}
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#endif
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}
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// IndexOf for constant substrings with size >= 8 chars
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// which don't need to be loaded through stack.
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void MacroAssembler::string_indexofC8(Register str1, Register str2,
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