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8294187: RISC-V: Unify all relocations for the backend into AbstractAssembler::relocate()

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Reviewed-by: fjiang, yadongwang, fyang
This commit is contained in:
Xiaolin Zheng 2022-09-23 13:15:44 +00:00 • committed by Fei Yang
parent acd75e0f1c
commit 664e5b1d2e
7 changed files with 15 additions and 30 deletions
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2
src/hotspot/cpu/riscv/assembler_riscv.cpp
View file

@ -215,7 +215,7 @@ void Assembler::ret() {
void Assembler::NAME(const Address &adr, Register temp) { \ void Assembler::NAME(const Address &adr, Register temp) { \
switch (adr.getMode()) { \ switch (adr.getMode()) { \
case Address::literal: { \ case Address::literal: { \
code_section()->relocate(pc(), adr.rspec()); \ relocate(adr.rspec()); \
NAME(adr.target(), temp); \ NAME(adr.target(), temp); \
break; \ break; \
} \ } \

10
src/hotspot/cpu/riscv/assembler_riscv.hpp
View file

@ -488,7 +488,7 @@ public:
result_type header { \ result_type header { \
guarantee(rtype == relocInfo::internal_word_type, \ guarantee(rtype == relocInfo::internal_word_type, \
"only internal_word_type relocs make sense here"); \ "only internal_word_type relocs make sense here"); \
code_section()->relocate(pc(), InternalAddress(dest).rspec()); relocate(InternalAddress(dest).rspec());
// Load/store register (all modes) // Load/store register (all modes)
#define INSN(NAME, op, funct3) \ #define INSN(NAME, op, funct3) \
@ -533,7 +533,7 @@ public:
void NAME(Register Rd, const Address &adr, Register temp = t0) { \ void NAME(Register Rd, const Address &adr, Register temp = t0) { \
switch (adr.getMode()) { \ switch (adr.getMode()) { \
case Address::literal: { \ case Address::literal: { \
code_section()->relocate(pc(), adr.rspec()); \ relocate(adr.rspec()); \
NAME(Rd, adr.target()); \ NAME(Rd, adr.target()); \
break; \ break; \
} \ } \
@ -607,7 +607,7 @@ public:
void NAME(FloatRegister Rd, const Address &adr, Register temp = t0) { \ void NAME(FloatRegister Rd, const Address &adr, Register temp = t0) { \
switch (adr.getMode()) { \ switch (adr.getMode()) { \
case Address::literal: { \ case Address::literal: { \
code_section()->relocate(pc(), adr.rspec()); \ relocate(adr.rspec()); \
NAME(Rd, adr.target(), temp); \ NAME(Rd, adr.target(), temp); \
break; \ break; \
} \ } \
@ -750,7 +750,7 @@ public:
switch (adr.getMode()) { \ switch (adr.getMode()) { \
case Address::literal: { \ case Address::literal: { \
assert_different_registers(Rs, temp); \ assert_different_registers(Rs, temp); \
code_section()->relocate(pc(), adr.rspec()); \ relocate(adr.rspec()); \
NAME(Rs, adr.target(), temp); \ NAME(Rs, adr.target(), temp); \
break; \ break; \
} \ } \
@ -793,7 +793,7 @@ public:
void NAME(FloatRegister Rs, const Address &adr, Register temp = t0) { \ void NAME(FloatRegister Rs, const Address &adr, Register temp = t0) { \
switch (adr.getMode()) { \ switch (adr.getMode()) { \
case Address::literal: { \ case Address::literal: { \
code_section()->relocate(pc(), adr.rspec()); \ relocate(adr.rspec()); \
NAME(Rs, adr.target(), temp); \ NAME(Rs, adr.target(), temp); \
break; \ break; \
} \ } \

2
src/hotspot/cpu/riscv/c1_CodeStubs_riscv.cpp
View file

@ -42,7 +42,7 @@
void C1SafepointPollStub::emit_code(LIR_Assembler* ce) { void C1SafepointPollStub::emit_code(LIR_Assembler* ce) {
__ bind(_entry); __ bind(_entry);
InternalAddress safepoint_pc(__ pc() - __ offset() + safepoint_offset()); InternalAddress safepoint_pc(__ pc() - __ offset() + safepoint_offset());
__ code_section()->relocate(__ pc(), safepoint_pc.rspec()); __ relocate(safepoint_pc.rspec());
__ la(t0, safepoint_pc.target()); __ la(t0, safepoint_pc.target());
__ sd(t0, Address(xthread, JavaThread::saved_exception_pc_offset())); __ sd(t0, Address(xthread, JavaThread::saved_exception_pc_offset()));

10
src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.cpp
View file

@ -2144,16 +2144,6 @@ void LIR_Assembler::typecheck_lir_store(LIR_OpTypeCheck* op, bool should_profile
__ bind(done); __ bind(done);
} }
void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
_masm->code_section()->relocate(adr, relocInfo::poll_type);
int pc_offset = code_offset();
flush_debug_info(pc_offset);
info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
if (info->exception_handlers() != NULL) {
compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
}
}
void LIR_Assembler::type_profile(Register obj, ciMethodData* md, Register klass_RInfo, Register k_RInfo, void LIR_Assembler::type_profile(Register obj, ciMethodData* md, Register klass_RInfo, Register k_RInfo,
ciProfileData* data, Label* success, Label* failure, ciProfileData* data, Label* success, Label* failure,
Label& profile_cast_success, Label& profile_cast_failure) { Label& profile_cast_success, Label& profile_cast_failure) {

2
src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.hpp
View file

@ -58,8 +58,6 @@ private:
ciMethodData *md, ciProfileData *data, ciMethodData *md, ciProfileData *data,
Register recv, Label* update_done); Register recv, Label* update_done);
void add_debug_info_for_branch(address adr, CodeEmitInfo* info);
void casw(Register addr, Register newval, Register cmpval); void casw(Register addr, Register newval, Register cmpval);
void caswu(Register addr, Register newval, Register cmpval); void caswu(Register addr, Register newval, Register cmpval);
void casl(Register addr, Register newval, Register cmpval); void casl(Register addr, Register newval, Register cmpval);

2
src/hotspot/cpu/riscv/c2_safepointPollStubTable_riscv.cpp
View file

@ -39,7 +39,7 @@ void C2SafepointPollStubTable::emit_stub_impl(MacroAssembler& masm, C2SafepointP
__ bind(entry->_stub_label); __ bind(entry->_stub_label);
InternalAddress safepoint_pc(masm.pc() - masm.offset() + entry->_safepoint_offset); InternalAddress safepoint_pc(masm.pc() - masm.offset() + entry->_safepoint_offset);
masm.code_section()->relocate(masm.pc(), safepoint_pc.rspec()); masm.relocate(safepoint_pc.rspec());
__ la(t0, safepoint_pc.target()); __ la(t0, safepoint_pc.target());
__ sd(t0, Address(xthread, JavaThread::saved_exception_pc_offset())); __ sd(t0, Address(xthread, JavaThread::saved_exception_pc_offset()));
__ far_jump(callback_addr); __ far_jump(callback_addr);

17
src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
View file

@ -730,14 +730,13 @@ void MacroAssembler::la(Register Rd, const address &dest) {
} }
void MacroAssembler::la(Register Rd, const Address &adr) { void MacroAssembler::la(Register Rd, const Address &adr) {
code_section()->relocate(pc(), adr.rspec());
relocInfo::relocType rtype = adr.rspec().reloc()->type();
switch (adr.getMode()) { switch (adr.getMode()) {
case Address::literal: { case Address::literal: {
relocInfo::relocType rtype = adr.rspec().reloc()->type();
if (rtype == relocInfo::none) { if (rtype == relocInfo::none) {
mv(Rd, (intptr_t)(adr.target())); mv(Rd, (intptr_t)(adr.target()));
} else { } else {
relocate(adr.rspec());
movptr(Rd, adr.target()); movptr(Rd, adr.target());
} }
break; break;
@ -1349,7 +1348,7 @@ void MacroAssembler::reinit_heapbase() {
void MacroAssembler::mv(Register Rd, Address dest) { void MacroAssembler::mv(Register Rd, Address dest) {
assert(dest.getMode() == Address::literal, "Address mode should be Address::literal"); assert(dest.getMode() == Address::literal, "Address mode should be Address::literal");
code_section()->relocate(pc(), dest.rspec()); relocate(dest.rspec());
movptr(Rd, dest.target()); movptr(Rd, dest.target());
} }
@ -2700,7 +2699,7 @@ void MacroAssembler::la_patchable(Register reg1, const Address &dest, int32_t &o
assert(is_valid_riscv64_address(dest.target()), "bad address"); assert(is_valid_riscv64_address(dest.target()), "bad address");
assert(dest.getMode() == Address::literal, "la_patchable must be applied to a literal address"); assert(dest.getMode() == Address::literal, "la_patchable must be applied to a literal address");
code_section()->relocate(pc(), dest.rspec()); relocate(dest.rspec());
// RISC-V doesn't compute a page-aligned address, in order to partially // RISC-V doesn't compute a page-aligned address, in order to partially
// compensate for the use of *signed* offsets in its base+disp12 // compensate for the use of *signed* offsets in its base+disp12
// addressing mode (RISC-V's PC-relative reach remains asymmetric // addressing mode (RISC-V's PC-relative reach remains asymmetric
@ -2764,7 +2763,7 @@ void MacroAssembler::get_polling_page(Register dest, relocInfo::relocType rtype)
// Read the polling page. The address of the polling page must // Read the polling page. The address of the polling page must
// already be in r. // already be in r.
void MacroAssembler::read_polling_page(Register r, int32_t offset, relocInfo::relocType rtype) { void MacroAssembler::read_polling_page(Register r, int32_t offset, relocInfo::relocType rtype) {
code_section()->relocate(pc(), rtype); relocate(rtype);
lwu(zr, Address(r, offset)); lwu(zr, Address(r, offset));
} }
@ -2779,8 +2778,7 @@ void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
} }
#endif #endif
int oop_index = oop_recorder()->find_index(obj); int oop_index = oop_recorder()->find_index(obj);
RelocationHolder rspec = oop_Relocation::spec(oop_index); relocate(oop_Relocation::spec(oop_index));
code_section()->relocate(pc(), rspec);
li32(dst, 0xDEADBEEF); li32(dst, 0xDEADBEEF);
zero_extend(dst, dst, 32); zero_extend(dst, dst, 32);
} }
@ -2791,9 +2789,8 @@ void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
int index = oop_recorder()->find_index(k); int index = oop_recorder()->find_index(k);
assert(!Universe::heap()->is_in(k), "should not be an oop"); assert(!Universe::heap()->is_in(k), "should not be an oop");
RelocationHolder rspec = metadata_Relocation::spec(index);
code_section()->relocate(pc(), rspec);
narrowKlass nk = CompressedKlassPointers::encode(k); narrowKlass nk = CompressedKlassPointers::encode(k);
relocate(metadata_Relocation::spec(index));
li32(dst, nk); li32(dst, nk);
zero_extend(dst, dst, 32); zero_extend(dst, dst, 32);
} }