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8144448: Avoid placing CTI immediately following or preceding RDPC instruction

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Best practice for new SPARC CPUs

Reviewed-by: kvn
This commit is contained in:
Patric Hedlin 2017-06-27 15:46:16 +02:00 • committed by Nils Eliasson
parent 065a8981f5
commit 6a9aa18f63
9 changed files with 1546 additions and 852 deletions
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8
hotspot/src/cpu/sparc/vm/macroAssembler_sparc.cpp
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@ -651,9 +651,9 @@ void MacroAssembler::card_table_write(jbyte* byte_map_base,
void MacroAssembler::internal_sethi(const AddressLiteral& addrlit, Register d, bool ForceRelocatable) {
address save_pc;
int shiftcnt;
# ifdef CHECK_DELAY
assert_not_delayed((char*) "cannot put two instructions in delay slot");
# endif
#ifdef VALIDATE_PIPELINE
assert_no_delay("Cannot put two instructions in delay-slot.");
#endif
v9_dep();
save_pc = pc();
@ -752,7 +752,7 @@ void MacroAssembler::internal_set(const AddressLiteral& addrlit, Register d, boo
return;
}
}
assert_not_delayed((char*) "cannot put two instructions in delay slot");
assert_no_delay("Cannot put two instructions in delay-slot.");
internal_sethi(addrlit, d, ForceRelocatable);
if (ForceRelocatable || addrlit.rspec().type() != relocInfo::none || addrlit.low10() != 0) {
add(d, addrlit.low10(), d, addrlit.rspec());