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6829193: JSR 292 needs to support SPARC
There are unimplemented portions of the hotspot code for method handles and invokedynamic specific to SPARC. Reviewed-by: kvn, never, jrose
This commit is contained in:
Christian Thalinger
parent
78e6939c37
commit
6d2a896bcd
14 changed files with 1210 additions and 126 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved.
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* Copyright 1997-2010 Sun Microsystems, Inc. All Rights Reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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@ -1380,24 +1380,25 @@ public:
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// pp 181
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void and3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | rs2(s2) ); }
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void and3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
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void and3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | rs2(s2) ); }
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void and3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
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void andcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
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void andcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
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void andn( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | rs2(s2) ); }
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void andn( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
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void andn( Register s1, RegisterOrConstant s2, Register d);
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void andncc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
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void andncc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
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void or3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | rs2(s2) ); }
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void or3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
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void or3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | rs2(s2) ); }
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void or3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
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void orcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
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void orcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
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void orn( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | rs2(s2) ); }
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void orn( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
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void orncc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
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void orncc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
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void xor3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | rs2(s2) ); }
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void xor3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
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void xor3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | rs2(s2) ); }
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void xor3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
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void xorcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
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void xorcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
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void xnor( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | rs2(s2) ); }
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@ -2026,8 +2027,8 @@ public:
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inline void st_ptr(Register d, Register s1, ByteSize simm13a);
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#endif
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// ld_long will perform ld for 32 bit VM's and ldx for 64 bit VM's
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// st_long will perform st for 32 bit VM's and stx for 64 bit VM's
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// ld_long will perform ldd for 32 bit VM's and ldx for 64 bit VM's
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// st_long will perform std for 32 bit VM's and stx for 64 bit VM's
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inline void ld_long(Register s1, Register s2, Register d);
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inline void ld_long(Register s1, int simm13a, Register d);
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inline void ld_long(Register s1, RegisterOrConstant s2, Register d);
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@ -2038,23 +2039,19 @@ public:
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inline void st_long(Register d, const Address& a, int offset = 0);
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// Helpers for address formation.
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// They update the dest in place, whether it is a register or constant.
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// They emit no code at all if src is a constant zero.
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// If dest is a constant and src is a register, the temp argument
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// is required, and becomes the result.
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// If dest is a register and src is a non-simm13 constant,
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// the temp argument is required, and is used to materialize the constant.
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void regcon_inc_ptr( RegisterOrConstant& dest, RegisterOrConstant src,
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Register temp = noreg );
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void regcon_sll_ptr( RegisterOrConstant& dest, RegisterOrConstant src,
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Register temp = noreg );
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// - They emit only a move if s2 is a constant zero.
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// - If dest is a constant and either s1 or s2 is a register, the temp argument is required and becomes the result.
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// - If dest is a register and either s1 or s2 is a non-simm13 constant, the temp argument is required and used to materialize the constant.
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RegisterOrConstant regcon_andn_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
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RegisterOrConstant regcon_inc_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
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RegisterOrConstant regcon_sll_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
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RegisterOrConstant ensure_simm13_or_reg(RegisterOrConstant roc, Register Rtemp) {
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guarantee(Rtemp != noreg, "constant offset overflow");
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if (is_simm13(roc.constant_or_zero()))
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return roc; // register or short constant
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set(roc.as_constant(), Rtemp);
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return RegisterOrConstant(Rtemp);
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RegisterOrConstant ensure_simm13_or_reg(RegisterOrConstant src, Register temp) {
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if (is_simm13(src.constant_or_zero()))
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return src; // register or short constant
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guarantee(temp != noreg, "constant offset overflow");
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set(src.as_constant(), temp);
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return temp;
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}
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// --------------------------------------------------
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@ -2303,6 +2300,9 @@ public:
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void lcmp( Register Ra, Register Rb, Register Rresult);
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#endif
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// Loading values by size and signed-ness
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void load_sized_value(Address src, Register dst, size_t size_in_bytes, bool is_signed);
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void float_cmp( bool is_float, int unordered_result,
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FloatRegister Fa, FloatRegister Fb,
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Register Rresult);
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@ -2421,12 +2421,16 @@ public:
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void check_method_handle_type(Register mtype_reg, Register mh_reg,
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Register temp_reg,
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Label& wrong_method_type);
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void jump_to_method_handle_entry(Register mh_reg, Register temp_reg);
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void load_method_handle_vmslots(Register vmslots_reg, Register mh_reg,
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Register temp_reg);
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void jump_to_method_handle_entry(Register mh_reg, Register temp_reg, bool emit_delayed_nop = true);
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// offset relative to Gargs of argument at tos[arg_slot].
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// (arg_slot == 0 means the last argument, not the first).
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RegisterOrConstant argument_offset(RegisterOrConstant arg_slot,
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int extra_slot_offset = 0);
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// Address of Gargs and argument_offset.
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Address argument_address(RegisterOrConstant arg_slot,
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int extra_slot_offset = 0);
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// Stack overflow checking
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