mirror of
https://github.com/openjdk/jdk.git
synced 2025-09-24 04:54:40 +02:00
Merge
This commit is contained in:
Jesper Wilhelmsson
commit
6f4adc7c72
65 changed files with 1141 additions and 355 deletions
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@ -54,6 +54,7 @@ define_pd_global(intx, INTPRESSURE, 25);
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define_pd_global(intx, InteriorEntryAlignment, 16);
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define_pd_global(intx, NewSizeThreadIncrease, ScaleForWordSize(4*K));
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define_pd_global(intx, LoopUnrollLimit, 60);
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define_pd_global(intx, LoopPercentProfileLimit, 10);
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// InitialCodeCacheSize derived from specjbb2000 run.
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define_pd_global(intx, InitialCodeCacheSize, 2496*K); // Integral multiple of CodeCacheExpansionSize
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define_pd_global(intx, CodeCacheExpansionSize, 64*K);
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2015, 2016, Oracle and/or its affiliates. All rights reserved.
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||||
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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||||
*
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||||
* This code is free software; you can redistribute it and/or modify it
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@ -30,39 +30,151 @@
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#include "vmreg_aarch64.inline.hpp"
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jint CodeInstaller::pd_next_offset(NativeInstruction* inst, jint pc_offset, Handle method, TRAPS) {
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Unimplemented();
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return 0;
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if (inst->is_call() || inst->is_jump() || inst->is_blr()) {
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return pc_offset + NativeCall::instruction_size;
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} else if (inst->is_general_jump()) {
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return pc_offset + NativeGeneralJump::instruction_size;
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} else {
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JVMCI_ERROR_0("unsupported type of instruction for call site");
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}
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}
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void CodeInstaller::pd_patch_OopConstant(int pc_offset, Handle constant, TRAPS) {
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Unimplemented();
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address pc = _instructions->start() + pc_offset;
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Handle obj = HotSpotObjectConstantImpl::object(constant);
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jobject value = JNIHandles::make_local(obj());
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if (HotSpotObjectConstantImpl::compressed(constant)) {
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int oop_index = _oop_recorder->find_index(value);
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RelocationHolder rspec = oop_Relocation::spec(oop_index);
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_instructions->relocate(pc, rspec, 1);
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Unimplemented();
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} else {
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NativeMovConstReg* move = nativeMovConstReg_at(pc);
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move->set_data((intptr_t) value);
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int oop_index = _oop_recorder->find_index(value);
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RelocationHolder rspec = oop_Relocation::spec(oop_index);
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_instructions->relocate(pc, rspec);
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}
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}
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void CodeInstaller::pd_patch_MetaspaceConstant(int pc_offset, Handle constant, TRAPS) {
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Unimplemented();
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address pc = _instructions->start() + pc_offset;
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if (HotSpotMetaspaceConstantImpl::compressed(constant)) {
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narrowKlass narrowOop = record_narrow_metadata_reference(constant, CHECK);
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TRACE_jvmci_3("relocating (narrow metaspace constant) at " PTR_FORMAT "/0x%x", p2i(pc), narrowOop);
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Unimplemented();
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} else {
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NativeMovConstReg* move = nativeMovConstReg_at(pc);
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Metadata* reference = record_metadata_reference(constant, CHECK);
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move->set_data((intptr_t) reference);
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TRACE_jvmci_3("relocating (metaspace constant) at " PTR_FORMAT "/" PTR_FORMAT, p2i(pc), p2i(reference));
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}
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}
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void CodeInstaller::pd_patch_DataSectionReference(int pc_offset, int data_offset) {
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Unimplemented();
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void CodeInstaller::pd_patch_DataSectionReference(int pc_offset, int data_offset, TRAPS) {
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address pc = _instructions->start() + pc_offset;
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NativeInstruction* inst = nativeInstruction_at(pc);
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if (inst->is_adr_aligned()) {
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address dest = _constants->start() + data_offset;
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_instructions->relocate(pc, section_word_Relocation::spec((address) dest, CodeBuffer::SECT_CONSTS));
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TRACE_jvmci_3("relocating at " PTR_FORMAT " (+%d) with destination at %d", p2i(pc), pc_offset, data_offset);
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} else {
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JVMCI_ERROR("unknown load or move instruction at " PTR_FORMAT, p2i(pc));
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}
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}
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void CodeInstaller::pd_relocate_ForeignCall(NativeInstruction* inst, jlong foreign_call_destination, TRAPS) {
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Unimplemented();
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address pc = (address) inst;
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if (inst->is_call()) {
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NativeCall* call = nativeCall_at(pc);
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call->set_destination((address) foreign_call_destination);
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_instructions->relocate(call->instruction_address(), runtime_call_Relocation::spec());
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} else if (inst->is_jump()) {
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NativeJump* jump = nativeJump_at(pc);
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jump->set_jump_destination((address) foreign_call_destination);
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_instructions->relocate(jump->instruction_address(), runtime_call_Relocation::spec());
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} else if (inst->is_general_jump()) {
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NativeGeneralJump* jump = nativeGeneralJump_at(pc);
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jump->set_jump_destination((address) foreign_call_destination);
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_instructions->relocate(jump->instruction_address(), runtime_call_Relocation::spec());
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} else {
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JVMCI_ERROR("unknown call or jump instruction at " PTR_FORMAT, p2i(pc));
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}
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TRACE_jvmci_3("relocating (foreign call) at " PTR_FORMAT, p2i(inst));
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}
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void CodeInstaller::pd_relocate_JavaMethod(Handle hotspot_method, jint pc_offset, TRAPS) {
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Unimplemented();
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#ifdef ASSERT
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Method* method = NULL;
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// we need to check, this might also be an unresolved method
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if (hotspot_method->is_a(HotSpotResolvedJavaMethodImpl::klass())) {
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method = getMethodFromHotSpotMethod(hotspot_method());
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}
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#endif
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switch (_next_call_type) {
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case INLINE_INVOKE:
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break;
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case INVOKEVIRTUAL:
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case INVOKEINTERFACE: {
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assert(method == NULL || !method->is_static(), "cannot call static method with invokeinterface");
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NativeCall* call = nativeCall_at(_instructions->start() + pc_offset);
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call->set_destination(SharedRuntime::get_resolve_virtual_call_stub());
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_instructions->relocate(call->instruction_address(), virtual_call_Relocation::spec(_invoke_mark_pc));
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break;
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}
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case INVOKESTATIC: {
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assert(method == NULL || method->is_static(), "cannot call non-static method with invokestatic");
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NativeCall* call = nativeCall_at(_instructions->start() + pc_offset);
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call->set_destination(SharedRuntime::get_resolve_static_call_stub());
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_instructions->relocate(call->instruction_address(), relocInfo::static_call_type);
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break;
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}
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case INVOKESPECIAL: {
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assert(method == NULL || !method->is_static(), "cannot call static method with invokespecial");
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NativeCall* call = nativeCall_at(_instructions->start() + pc_offset);
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call->set_destination(SharedRuntime::get_resolve_opt_virtual_call_stub());
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_instructions->relocate(call->instruction_address(), relocInfo::opt_virtual_call_type);
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break;
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}
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default:
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JVMCI_ERROR("invalid _next_call_type value");
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break;
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}
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}
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void CodeInstaller::pd_relocate_poll(address pc, jint mark, TRAPS) {
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Unimplemented();
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switch (mark) {
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case POLL_NEAR:
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JVMCI_ERROR("unimplemented");
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break;
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case POLL_FAR:
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_instructions->relocate(pc, relocInfo::poll_type);
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break;
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case POLL_RETURN_NEAR:
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JVMCI_ERROR("unimplemented");
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break;
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case POLL_RETURN_FAR:
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_instructions->relocate(pc, relocInfo::poll_return_type);
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break;
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default:
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JVMCI_ERROR("invalid mark value");
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break;
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}
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}
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// convert JVMCI register indices (as used in oop maps) to HotSpot registers
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VMReg CodeInstaller::get_hotspot_reg(jint jvmci_reg, TRAPS) {
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return NULL;
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if (jvmci_reg < RegisterImpl::number_of_registers) {
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return as_Register(jvmci_reg)->as_VMReg();
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} else {
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jint floatRegisterNumber = jvmci_reg - RegisterImpl::number_of_registers;
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if (floatRegisterNumber < FloatRegisterImpl::number_of_registers) {
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return as_FloatRegister(floatRegisterNumber)->as_VMReg();
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}
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JVMCI_ERROR_NULL("invalid register number: %d", jvmci_reg);
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}
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}
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bool CodeInstaller::is_general_purpose_reg(VMReg hotspotRegister) {
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return false;
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return !hotspotRegister->is_FloatRegister();
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}
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@ -136,7 +136,7 @@ void NativeMovConstReg::set_data(intptr_t x) {
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MacroAssembler::pd_patch_instruction(instruction_address(), (address)x);
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ICache::invalidate_range(instruction_address(), instruction_size);
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}
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};
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}
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void NativeMovConstReg::print() {
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tty->print_cr(PTR_FORMAT ": mov reg, " INTPTR_FORMAT,
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@ -208,6 +208,32 @@ void NativeJump::set_jump_destination(address dest) {
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//-------------------------------------------------------------------
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address NativeGeneralJump::jump_destination() const {
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NativeMovConstReg* move = nativeMovConstReg_at(instruction_address());
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address dest = (address) move->data();
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// We use jump to self as the unresolved address which the inline
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// cache code (and relocs) know about
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// return -1 if jump to self
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dest = (dest == (address) this) ? (address) -1 : dest;
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return dest;
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}
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void NativeGeneralJump::set_jump_destination(address dest) {
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NativeMovConstReg* move = nativeMovConstReg_at(instruction_address());
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// We use jump to self as the unresolved address which the inline
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// cache code (and relocs) know about
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if (dest == (address) -1) {
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dest = instruction_address();
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}
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move->set_data((uintptr_t) dest);
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};
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//-------------------------------------------------------------------
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bool NativeInstruction::is_safepoint_poll() {
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// a safepoint_poll is implemented in two steps as either
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//
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@ -249,6 +275,22 @@ bool NativeInstruction::is_ldrw_to_zr(address instr) {
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Instruction_aarch64::extract(insn, 4, 0) == 0b11111);
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}
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bool NativeInstruction::is_general_jump() {
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if (is_movz()) {
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NativeInstruction* inst1 = nativeInstruction_at(addr_at(instruction_size * 1));
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if (inst1->is_movk()) {
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NativeInstruction* inst2 = nativeInstruction_at(addr_at(instruction_size * 2));
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if (inst2->is_movk()) {
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NativeInstruction* inst3 = nativeInstruction_at(addr_at(instruction_size * 3));
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if (inst3->is_blr()) {
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return true;
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}
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}
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}
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}
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return false;
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}
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bool NativeInstruction::is_movz() {
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return Instruction_aarch64::extract(int_at(0), 30, 23) == 0b10100101;
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}
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@ -54,11 +54,22 @@ class NativeInstruction VALUE_OBJ_CLASS_SPEC {
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friend class Relocation;
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friend bool is_NativeCallTrampolineStub_at(address);
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public:
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enum { instruction_size = 4 };
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enum {
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instruction_size = 4
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};
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juint encoding() const {
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return uint_at(0);
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}
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bool is_blr() const { return (encoding() & 0xfffffc1f) == 0xd63f0000; }
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bool is_adr_aligned() const { return (encoding() & 0xff000000) == 0x10000000; } // adr Xn, <label>, where label is aligned to 4 bytes (address of instruction).
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inline bool is_nop();
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inline bool is_illegal();
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inline bool is_return();
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bool is_jump();
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bool is_general_jump();
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inline bool is_jump_or_nop();
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inline bool is_cond_jump();
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bool is_safepoint_poll();
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@ -341,11 +352,15 @@ class NativeMovRegMemPatching: public NativeMovRegMem {
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// An interface for accessing/manipulating native leal instruction of form:
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// leal reg, [reg + offset]
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class NativeLoadAddress: public NativeMovRegMem {
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static const bool has_rex = true;
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static const int rex_size = 1;
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public:
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class NativeLoadAddress: public NativeInstruction {
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enum AArch64_specific_constants {
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instruction_size = 4,
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instruction_offset = 0,
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data_offset = 0,
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next_instruction_offset = 4
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};
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public:
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void verify();
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void print ();
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@ -398,6 +413,10 @@ public:
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data_offset = 0,
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next_instruction_offset = 4 * 4
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};
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address jump_destination() const;
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void set_jump_destination(address dest);
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static void insert_unconditional(address code_pos, address entry);
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static void replace_mt_safe(address instr_addr, address code_buffer);
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static void verify();
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|
|
|
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|
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@ -54,6 +54,7 @@ define_pd_global(intx, RegisterCostAreaRatio, 16000);
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define_pd_global(bool, UseTLAB, true);
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define_pd_global(bool, ResizeTLAB, true);
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define_pd_global(intx, LoopUnrollLimit, 60);
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define_pd_global(intx, LoopPercentProfileLimit, 10);
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||||
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// Peephole and CISC spilling both break the graph, and so make the
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// scheduler sick.
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||||
|
|
|
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|
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@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2015, 2016, Oracle and/or its affiliates. All rights reserved.
|
||||
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
*
|
||||
* This code is free software; you can redistribute it and/or modify it
|
||||
|
|
@ -42,7 +42,7 @@ void CodeInstaller::pd_patch_MetaspaceConstant(int pc_offset, Handle constant, T
|
|||
Unimplemented();
|
||||
}
|
||||
|
||||
void CodeInstaller::pd_patch_DataSectionReference(int pc_offset, int data_offset) {
|
||||
void CodeInstaller::pd_patch_DataSectionReference(int pc_offset, int data_offset, TRAPS) {
|
||||
Unimplemented();
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -52,6 +52,7 @@ define_pd_global(intx, RegisterCostAreaRatio, 12000);
|
|||
define_pd_global(bool, UseTLAB, true);
|
||||
define_pd_global(bool, ResizeTLAB, true);
|
||||
define_pd_global(intx, LoopUnrollLimit, 60); // Design center runs on 1.3.1
|
||||
define_pd_global(intx, LoopPercentProfileLimit, 10);
|
||||
define_pd_global(intx, MinJumpTableSize, 5);
|
||||
|
||||
// Peephole and CISC spilling both break the graph, and so makes the
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2013, 2015, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2013, 2016, Oracle and/or its affiliates. All rights reserved.
|
||||
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
*
|
||||
* This code is free software; you can redistribute it and/or modify it
|
||||
|
|
@ -85,7 +85,7 @@ void CodeInstaller::pd_patch_MetaspaceConstant(int pc_offset, Handle constant, T
|
|||
}
|
||||
}
|
||||
|
||||
void CodeInstaller::pd_patch_DataSectionReference(int pc_offset, int data_offset) {
|
||||
void CodeInstaller::pd_patch_DataSectionReference(int pc_offset, int data_offset, TRAPS) {
|
||||
address pc = _instructions->start() + pc_offset;
|
||||
NativeInstruction* inst = nativeInstruction_at(pc);
|
||||
NativeInstruction* inst1 = nativeInstruction_at(pc + 4);
|
||||
|
|
|
|||
|
|
@ -2015,23 +2015,33 @@ nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
|
|||
int vep_offset = ((intptr_t)__ pc()) - start;
|
||||
|
||||
#ifdef COMPILER1
|
||||
if (InlineObjectHash && method->intrinsic_id() == vmIntrinsics::_hashCode) {
|
||||
// Object.hashCode can pull the hashCode from the header word
|
||||
// instead of doing a full VM transition once it's been computed.
|
||||
// Since hashCode is usually polymorphic at call sites we can't do
|
||||
// this optimization at the call site without a lot of work.
|
||||
if ((InlineObjectHash && method->intrinsic_id() == vmIntrinsics::_hashCode) || (method->intrinsic_id() == vmIntrinsics::_identityHashCode)) {
|
||||
// Object.hashCode, System.identityHashCode can pull the hashCode from the
|
||||
// header word instead of doing a full VM transition once it's been computed.
|
||||
// Since hashCode is usually polymorphic at call sites we can't do this
|
||||
// optimization at the call site without a lot of work.
|
||||
Label slowCase;
|
||||
Register receiver = O0;
|
||||
Label done;
|
||||
Register obj_reg = O0;
|
||||
Register result = O0;
|
||||
Register header = G3_scratch;
|
||||
Register hash = G3_scratch; // overwrite header value with hash value
|
||||
Register mask = G1; // to get hash field from header
|
||||
|
||||
// Unlike for Object.hashCode, System.identityHashCode is static method and
|
||||
// gets object as argument instead of the receiver.
|
||||
if (method->intrinsic_id() == vmIntrinsics::_identityHashCode) {
|
||||
assert(method->is_static(), "method should be static");
|
||||
// return 0 for null reference input
|
||||
__ br_null(obj_reg, false, Assembler::pn, done);
|
||||
__ delayed()->mov(obj_reg, hash);
|
||||
}
|
||||
|
||||
// Read the header and build a mask to get its hash field. Give up if the object is not unlocked.
|
||||
// We depend on hash_mask being at most 32 bits and avoid the use of
|
||||
// hash_mask_in_place because it could be larger than 32 bits in a 64-bit
|
||||
// vm: see markOop.hpp.
|
||||
__ ld_ptr(receiver, oopDesc::mark_offset_in_bytes(), header);
|
||||
__ ld_ptr(obj_reg, oopDesc::mark_offset_in_bytes(), header);
|
||||
__ sethi(markOopDesc::hash_mask, mask);
|
||||
__ btst(markOopDesc::unlocked_value, header);
|
||||
__ br(Assembler::zero, false, Assembler::pn, slowCase);
|
||||
|
|
@ -2054,6 +2064,7 @@ nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
|
|||
__ delayed()->nop();
|
||||
|
||||
// leaf return.
|
||||
__ bind(done);
|
||||
__ retl();
|
||||
__ delayed()->mov(hash, result);
|
||||
__ bind(slowCase);
|
||||
|
|
|
|||
|
|
@ -2361,7 +2361,7 @@ void Assembler::movdqa(XMMRegister dst, Address src) {
|
|||
void Assembler::movdqu(XMMRegister dst, Address src) {
|
||||
NOT_LP64(assert(VM_Version::supports_sse2(), ""));
|
||||
InstructionMark im(this);
|
||||
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
|
||||
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
|
||||
attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
|
||||
simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
|
||||
emit_int8(0x6F);
|
||||
|
|
@ -2398,7 +2398,7 @@ void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
|
|||
void Assembler::vmovdqu(XMMRegister dst, Address src) {
|
||||
assert(UseAVX > 0, "");
|
||||
InstructionMark im(this);
|
||||
InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
|
||||
InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
|
||||
attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
|
||||
vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
|
||||
emit_int8(0x6F);
|
||||
|
|
@ -2486,7 +2486,7 @@ void Assembler::evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
|
|||
void Assembler::evmovdqul(XMMRegister dst, Address src, int vector_len) {
|
||||
assert(VM_Version::supports_evex(), "");
|
||||
InstructionMark im(this);
|
||||
InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
|
||||
InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ true);
|
||||
attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
|
||||
vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
|
||||
emit_int8(0x6F);
|
||||
|
|
@ -2515,7 +2515,7 @@ void Assembler::evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
|
|||
void Assembler::evmovdquq(XMMRegister dst, Address src, int vector_len) {
|
||||
assert(VM_Version::supports_evex(), "");
|
||||
InstructionMark im(this);
|
||||
InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
|
||||
InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
|
||||
attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
|
||||
vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
|
||||
emit_int8(0x6F);
|
||||
|
|
@ -2640,7 +2640,7 @@ void Assembler::movsbl(Register dst, Register src) { // movsxb
|
|||
|
||||
void Assembler::movsd(XMMRegister dst, XMMRegister src) {
|
||||
NOT_LP64(assert(VM_Version::supports_sse2(), ""));
|
||||
InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
|
||||
InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
|
||||
int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
|
||||
emit_int8(0x10);
|
||||
emit_int8((unsigned char)(0xC0 | encode));
|
||||
|
|
@ -2649,7 +2649,7 @@ void Assembler::movsd(XMMRegister dst, XMMRegister src) {
|
|||
void Assembler::movsd(XMMRegister dst, Address src) {
|
||||
NOT_LP64(assert(VM_Version::supports_sse2(), ""));
|
||||
InstructionMark im(this);
|
||||
InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
|
||||
InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
|
||||
attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
|
||||
simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
|
||||
emit_int8(0x10);
|
||||
|
|
@ -2668,7 +2668,7 @@ void Assembler::movsd(Address dst, XMMRegister src) {
|
|||
|
||||
void Assembler::movss(XMMRegister dst, XMMRegister src) {
|
||||
NOT_LP64(assert(VM_Version::supports_sse(), ""));
|
||||
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
|
||||
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
|
||||
int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
|
||||
emit_int8(0x10);
|
||||
emit_int8((unsigned char)(0xC0 | encode));
|
||||
|
|
@ -2677,7 +2677,7 @@ void Assembler::movss(XMMRegister dst, XMMRegister src) {
|
|||
void Assembler::movss(XMMRegister dst, Address src) {
|
||||
NOT_LP64(assert(VM_Version::supports_sse(), ""));
|
||||
InstructionMark im(this);
|
||||
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
|
||||
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
|
||||
attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
|
||||
simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
|
||||
emit_int8(0x10);
|
||||
|
|
@ -2782,7 +2782,7 @@ void Assembler::mull(Register src) {
|
|||
void Assembler::mulsd(XMMRegister dst, Address src) {
|
||||
NOT_LP64(assert(VM_Version::supports_sse2(), ""));
|
||||
InstructionMark im(this);
|
||||
InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
|
||||
InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
|
||||
attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
|
||||
simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
|
||||
emit_int8(0x59);
|
||||
|
|
@ -2791,7 +2791,7 @@ void Assembler::mulsd(XMMRegister dst, Address src) {
|
|||
|
||||
void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
|
||||
NOT_LP64(assert(VM_Version::supports_sse2(), ""));
|
||||
InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
|
||||
InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
|
||||
int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
|
||||
emit_int8(0x59);
|
||||
emit_int8((unsigned char)(0xC0 | encode));
|
||||
|
|
@ -2800,7 +2800,7 @@ void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
|
|||
void Assembler::mulss(XMMRegister dst, Address src) {
|
||||
NOT_LP64(assert(VM_Version::supports_sse(), ""));
|
||||
InstructionMark im(this);
|
||||
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
|
||||
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
|
||||
attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
|
||||
simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
|
||||
emit_int8(0x59);
|
||||
|
|
@ -2809,7 +2809,7 @@ void Assembler::mulss(XMMRegister dst, Address src) {
|
|||
|
||||
void Assembler::mulss(XMMRegister dst, XMMRegister src) {
|
||||
NOT_LP64(assert(VM_Version::supports_sse(), ""));
|
||||
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
|
||||
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
|
||||
int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
|
||||
emit_int8(0x59);
|
||||
emit_int8((unsigned char)(0xC0 | encode));
|
||||
|
|
@ -3993,7 +3993,7 @@ void Assembler::smovl() {
|
|||
|
||||
void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
|
||||
NOT_LP64(assert(VM_Version::supports_sse2(), ""));
|
||||
InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
|
||||
InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
|
||||
int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
|
||||
emit_int8(0x51);
|
||||
emit_int8((unsigned char)(0xC0 | encode));
|
||||
|
|
@ -4002,7 +4002,7 @@ void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
|
|||
void Assembler::sqrtsd(XMMRegister dst, Address src) {
|
||||
NOT_LP64(assert(VM_Version::supports_sse2(), ""));
|
||||
InstructionMark im(this);
|
||||
InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
|
||||
InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
|
||||
attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
|
||||
simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
|
||||
emit_int8(0x51);
|
||||
|
|
@ -4011,7 +4011,7 @@ void Assembler::sqrtsd(XMMRegister dst, Address src) {
|
|||
|
||||
void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
|
||||
NOT_LP64(assert(VM_Version::supports_sse(), ""));
|
||||
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
|
||||
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
|
||||
int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
|
||||
emit_int8(0x51);
|
||||
emit_int8((unsigned char)(0xC0 | encode));
|
||||
|
|
@ -4024,7 +4024,7 @@ void Assembler::std() {
|
|||
void Assembler::sqrtss(XMMRegister dst, Address src) {
|
||||
NOT_LP64(assert(VM_Version::supports_sse(), ""));
|
||||
InstructionMark im(this);
|
||||
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
|
||||
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
|
||||
attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
|
||||
simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
|
||||
emit_int8(0x51);
|
||||
|
|
@ -4078,7 +4078,7 @@ void Assembler::subl(Register dst, Register src) {
|
|||
|
||||
void Assembler::subsd(XMMRegister dst, XMMRegister src) {
|
||||
NOT_LP64(assert(VM_Version::supports_sse2(), ""));
|
||||
InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
|
||||
InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
|
||||
int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
|
||||
emit_int8(0x5C);
|
||||
emit_int8((unsigned char)(0xC0 | encode));
|
||||
|
|
@ -4087,7 +4087,7 @@ void Assembler::subsd(XMMRegister dst, XMMRegister src) {
|
|||
void Assembler::subsd(XMMRegister dst, Address src) {
|
||||
NOT_LP64(assert(VM_Version::supports_sse2(), ""));
|
||||
InstructionMark im(this);
|
||||
InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
|
||||
InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
|
||||
attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
|
||||
simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
|
||||
emit_int8(0x5C);
|
||||
|
|
@ -4096,7 +4096,7 @@ void Assembler::subsd(XMMRegister dst, Address src) {
|
|||
|
||||
void Assembler::subss(XMMRegister dst, XMMRegister src) {
|
||||
NOT_LP64(assert(VM_Version::supports_sse(), ""));
|
||||
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
|
||||
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ false);
|
||||
int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
|
||||
emit_int8(0x5C);
|
||||
emit_int8((unsigned char)(0xC0 | encode));
|
||||
|
|
@ -4105,7 +4105,7 @@ void Assembler::subss(XMMRegister dst, XMMRegister src) {
|
|||
void Assembler::subss(XMMRegister dst, Address src) {
|
||||
NOT_LP64(assert(VM_Version::supports_sse(), ""));
|
||||
InstructionMark im(this);
|
||||
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
|
||||
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
|
||||
attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
|
||||
simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
|
||||
emit_int8(0x5C);
|
||||
|
|
@ -4293,7 +4293,7 @@ void Assembler::xorb(Register dst, Address src) {
|
|||
void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
|
||||
assert(VM_Version::supports_avx(), "");
|
||||
InstructionMark im(this);
|
||||
InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
|
||||
InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
|
||||
attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
|
||||
int nds_enc = nds->is_valid() ? nds->encoding() : 0;
|
||||
vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
|
||||
|
|
@ -4303,7 +4303,7 @@ void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
|
|||
|
||||
void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
|
||||
assert(VM_Version::supports_avx(), "");
|
||||
InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
|
||||
InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
|
||||
int nds_enc = nds->is_valid() ? nds->encoding() : 0;
|
||||
int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
|
||||
emit_int8(0x58);
|
||||
|
|
@ -4313,7 +4313,7 @@ void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
|
|||
void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
|
||||
assert(VM_Version::supports_avx(), "");
|
||||
InstructionMark im(this);
|
||||
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
|
||||
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
|
||||
attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
|
||||
int nds_enc = nds->is_valid() ? nds->encoding() : 0;
|
||||
vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
|
||||
|
|
@ -4323,7 +4323,7 @@ void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
|
|||
|
||||
void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
|
||||
assert(VM_Version::supports_avx(), "");
|
||||
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
|
||||
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
|
||||
int nds_enc = nds->is_valid() ? nds->encoding() : 0;
|
||||
int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
|
||||
emit_int8(0x58);
|
||||
|
|
@ -4333,7 +4333,7 @@ void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
|
|||
void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
|
||||
assert(VM_Version::supports_avx(), "");
|
||||
InstructionMark im(this);
|
||||
InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
|
||||
InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
|
||||
attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
|
||||
int nds_enc = nds->is_valid() ? nds->encoding() : 0;
|
||||
vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
|
||||
|
|
@ -4343,7 +4343,7 @@ void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
|
|||
|
||||
void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
|
||||
assert(VM_Version::supports_avx(), "");
|
||||
InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
|
||||
InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
|
||||
int nds_enc = nds->is_valid() ? nds->encoding() : 0;
|
||||
int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
|
||||
emit_int8(0x5E);
|
||||
|
|
@ -4353,7 +4353,7 @@ void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
|
|||
void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
|
||||
assert(VM_Version::supports_avx(), "");
|
||||
InstructionMark im(this);
|
||||
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
|
||||
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
|
||||
attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
|
||||
int nds_enc = nds->is_valid() ? nds->encoding() : 0;
|
||||
vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
|
||||
|
|
@ -4363,7 +4363,7 @@ void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
|
|||
|
||||
void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
|
||||
assert(VM_Version::supports_avx(), "");
|
||||
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
|
||||
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
|
||||
int nds_enc = nds->is_valid() ? nds->encoding() : 0;
|
||||
int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
|
||||
emit_int8(0x5E);
|
||||
|
|
@ -4373,7 +4373,7 @@ void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
|
|||
void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
|
||||
assert(VM_Version::supports_avx(), "");
|
||||
InstructionMark im(this);
|
||||
InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
|
||||
InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
|
||||
attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
|
||||
int nds_enc = nds->is_valid() ? nds->encoding() : 0;
|
||||
vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
|
||||
|
|
@ -4383,7 +4383,7 @@ void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
|
|||
|
||||
void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
|
||||
assert(VM_Version::supports_avx(), "");
|
||||
InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
|
||||
InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
|
||||
int nds_enc = nds->is_valid() ? nds->encoding() : 0;
|
||||
int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
|
||||
emit_int8(0x59);
|
||||
|
|
@ -4393,7 +4393,7 @@ void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
|
|||
void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
|
||||
assert(VM_Version::supports_avx(), "");
|
||||
InstructionMark im(this);
|
||||
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
|
||||
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
|
||||
attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
|
||||
int nds_enc = nds->is_valid() ? nds->encoding() : 0;
|
||||
vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
|
||||
|
|
@ -4403,7 +4403,7 @@ void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
|
|||
|
||||
void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
|
||||
assert(VM_Version::supports_avx(), "");
|
||||
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
|
||||
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
|
||||
int nds_enc = nds->is_valid() ? nds->encoding() : 0;
|
||||
int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
|
||||
emit_int8(0x59);
|
||||
|
|
@ -4413,7 +4413,7 @@ void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
|
|||
void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
|
||||
assert(VM_Version::supports_avx(), "");
|
||||
InstructionMark im(this);
|
||||
InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
|
||||
InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
|
||||
attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
|
||||
int nds_enc = nds->is_valid() ? nds->encoding() : 0;
|
||||
vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
|
||||
|
|
@ -4423,7 +4423,7 @@ void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
|
|||
|
||||
void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
|
||||
assert(VM_Version::supports_avx(), "");
|
||||
InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
|
||||
InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
|
||||
int nds_enc = nds->is_valid() ? nds->encoding() : 0;
|
||||
int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
|
||||
emit_int8(0x5C);
|
||||
|
|
@ -4433,7 +4433,7 @@ void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
|
|||
void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
|
||||
assert(VM_Version::supports_avx(), "");
|
||||
InstructionMark im(this);
|
||||
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
|
||||
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
|
||||
attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
|
||||
int nds_enc = nds->is_valid() ? nds->encoding() : 0;
|
||||
vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
|
||||
|
|
@ -4443,7 +4443,7 @@ void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
|
|||
|
||||
void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
|
||||
assert(VM_Version::supports_avx(), "");
|
||||
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
|
||||
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
|
||||
int nds_enc = nds->is_valid() ? nds->encoding() : 0;
|
||||
int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
|
||||
emit_int8(0x5C);
|
||||
|
|
@ -5901,7 +5901,7 @@ void Assembler::vpbroadcastw(XMMRegister dst, XMMRegister src) {
|
|||
// duplicate 1-byte integer data from src into 16||32|64 locations in dest : requires AVX512BW and AVX512VL
|
||||
void Assembler::evpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) {
|
||||
assert(VM_Version::supports_evex(), "");
|
||||
InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
|
||||
InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
|
||||
int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
|
||||
emit_int8(0x78);
|
||||
emit_int8((unsigned char)(0xC0 | encode));
|
||||
|
|
@ -5911,7 +5911,7 @@ void Assembler::evpbroadcastb(XMMRegister dst, Address src, int vector_len) {
|
|||
assert(VM_Version::supports_evex(), "");
|
||||
assert(dst != xnoreg, "sanity");
|
||||
InstructionMark im(this);
|
||||
InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
|
||||
InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
|
||||
attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
|
||||
// swap src<->dst for encoding
|
||||
vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
|
||||
|
|
@ -5922,7 +5922,7 @@ void Assembler::evpbroadcastb(XMMRegister dst, Address src, int vector_len) {
|
|||
// duplicate 2-byte integer data from src into 8|16||32 locations in dest : requires AVX512BW and AVX512VL
|
||||
void Assembler::evpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
|
||||
assert(VM_Version::supports_evex(), "");
|
||||
InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
|
||||
InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
|
||||
int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
|
||||
emit_int8(0x79);
|
||||
emit_int8((unsigned char)(0xC0 | encode));
|
||||
|
|
@ -5932,7 +5932,7 @@ void Assembler::evpbroadcastw(XMMRegister dst, Address src, int vector_len) {
|
|||
assert(VM_Version::supports_evex(), "");
|
||||
assert(dst != xnoreg, "sanity");
|
||||
InstructionMark im(this);
|
||||
InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
|
||||
InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
|
||||
attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
|
||||
// swap src<->dst for encoding
|
||||
vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
|
||||
|
|
@ -6027,7 +6027,7 @@ void Assembler::evpbroadcastsd(XMMRegister dst, Address src, int vector_len) {
|
|||
// duplicate 1-byte integer data from src into 16||32|64 locations in dest : requires AVX512BW and AVX512VL
|
||||
void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) {
|
||||
assert(VM_Version::supports_evex(), "");
|
||||
InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
|
||||
InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
|
||||
int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
|
||||
emit_int8(0x7A);
|
||||
emit_int8((unsigned char)(0xC0 | encode));
|
||||
|
|
@ -6036,7 +6036,7 @@ void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) {
|
|||
// duplicate 2-byte integer data from src into 8|16||32 locations in dest : requires AVX512BW and AVX512VL
|
||||
void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) {
|
||||
assert(VM_Version::supports_evex(), "");
|
||||
InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
|
||||
InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
|
||||
int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
|
||||
emit_int8(0x7B);
|
||||
emit_int8((unsigned char)(0xC0 | encode));
|
||||
|
|
|
|||
|
|
@ -2044,11 +2044,11 @@ private:
|
|||
class InstructionAttr {
|
||||
public:
|
||||
InstructionAttr(
|
||||
int vector_len,
|
||||
bool rex_vex_w,
|
||||
bool legacy_mode,
|
||||
bool no_reg_mask,
|
||||
bool uses_vl)
|
||||
int vector_len, // The length of vector to be applied in encoding - for both AVX and EVEX
|
||||
bool rex_vex_w, // Width of data: if 32-bits or less, false, else if 64-bit or specially defined, true
|
||||
bool legacy_mode, // Details if either this instruction is conditionally encoded to AVX or earlier if true else possibly EVEX
|
||||
bool no_reg_mask, // when true, k0 is used when EVEX encoding is chosen, else k1 is used under the same condition
|
||||
bool uses_vl) // This instruction may have legacy constraints based on vector length for EVEX
|
||||
:
|
||||
_avx_vector_len(vector_len),
|
||||
_rex_vex_w(rex_vex_w),
|
||||
|
|
|
|||
|
|
@ -46,6 +46,7 @@ define_pd_global(intx, OnStackReplacePercentage, 140);
|
|||
define_pd_global(intx, ConditionalMoveLimit, 3);
|
||||
define_pd_global(intx, FreqInlineSize, 325);
|
||||
define_pd_global(intx, MinJumpTableSize, 10);
|
||||
define_pd_global(intx, LoopPercentProfileLimit, 30);
|
||||
#ifdef AMD64
|
||||
define_pd_global(intx, INTPRESSURE, 13);
|
||||
define_pd_global(intx, FLOATPRESSURE, 14);
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2013, 2015, Oracle and/or its affiliates. All rights reserved.
|
||||
* Copyright (c) 2013, 2016, Oracle and/or its affiliates. All rights reserved.
|
||||
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
*
|
||||
* This code is free software; you can redistribute it and/or modify it
|
||||
|
|
@ -101,7 +101,7 @@ void CodeInstaller::pd_patch_MetaspaceConstant(int pc_offset, Handle constant, T
|
|||
}
|
||||
}
|
||||
|
||||
void CodeInstaller::pd_patch_DataSectionReference(int pc_offset, int data_offset) {
|
||||
void CodeInstaller::pd_patch_DataSectionReference(int pc_offset, int data_offset, TRAPS) {
|
||||
address pc = _instructions->start() + pc_offset;
|
||||
|
||||
address operand = Assembler::locate_operand(pc, Assembler::disp32_operand);
|
||||
|
|
|
|||
|
|
@ -7840,7 +7840,9 @@ void MacroAssembler::string_compare(Register str1, Register str2,
|
|||
Label COMPARE_WIDE_VECTORS_LOOP_FAILED; // used only _LP64 && AVX3
|
||||
int stride, stride2, adr_stride, adr_stride1, adr_stride2;
|
||||
int stride2x2 = 0x40;
|
||||
Address::ScaleFactor scale, scale1, scale2;
|
||||
Address::ScaleFactor scale = Address::no_scale;
|
||||
Address::ScaleFactor scale1 = Address::no_scale;
|
||||
Address::ScaleFactor scale2 = Address::no_scale;
|
||||
|
||||
if (ae != StrIntrinsicNode::LL) {
|
||||
stride2x2 = 0x20;
|
||||
|
|
@ -7894,9 +7896,9 @@ void MacroAssembler::string_compare(Register str1, Register str2,
|
|||
stride = 8;
|
||||
}
|
||||
} else {
|
||||
scale = Address::no_scale; // not used
|
||||
scale1 = Address::times_1;
|
||||
scale2 = Address::times_2;
|
||||
// scale not used
|
||||
stride = 8;
|
||||
}
|
||||
|
||||
|
|
|
|||
91
hotspot/src/cpu/x86/vm/sharedRuntime_x86.cpp
Normal file
91
hotspot/src/cpu/x86/vm/sharedRuntime_x86.cpp
Normal file
|
|
@ -0,0 +1,91 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved.
|
||||
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
||||
*
|
||||
* This code is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 only, as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This code is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
* version 2 for more details (a copy is included in the LICENSE file that
|
||||
* accompanied this code).
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License version
|
||||
* 2 along with this work; if not, write to the Free Software Foundation,
|
||||
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
|
||||
* or visit www.oracle.com if you need additional information or have any
|
||||
* questions.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "precompiled.hpp"
|
||||
#include "asm/macroAssembler.hpp"
|
||||
#include "runtime/sharedRuntime.hpp"
|
||||
#include "vmreg_x86.inline.hpp"
|
||||
#ifdef COMPILER1
|
||||
#include "c1/c1_Runtime1.hpp"
|
||||
#endif //COMPILER1
|
||||
|
||||
#define __ masm->
|
||||
|
||||
#ifdef COMPILER1
|
||||
// ---------------------------------------------------------------------------
|
||||
// Object.hashCode, System.identityHashCode can pull the hashCode from the
|
||||
// header word instead of doing a full VM transition once it's been computed.
|
||||
// Since hashCode is usually polymorphic at call sites we can't do this
|
||||
// optimization at the call site without a lot of work.
|
||||
void SharedRuntime::inline_check_hashcode_from_object_header(MacroAssembler* masm,
|
||||
methodHandle method,
|
||||
Register obj_reg,
|
||||
Register result) {
|
||||
Label slowCase;
|
||||
|
||||
// Unlike for Object.hashCode, System.identityHashCode is static method and
|
||||
// gets object as argument instead of the receiver.
|
||||
if (method->intrinsic_id() == vmIntrinsics::_identityHashCode) {
|
||||
Label Continue;
|
||||
// return 0 for null reference input
|
||||
__ cmpptr(obj_reg, (int32_t)NULL_WORD);
|
||||
__ jcc(Assembler::notEqual, Continue);
|
||||
__ xorptr(result, result);
|
||||
__ ret(0);
|
||||
__ bind(Continue);
|
||||
}
|
||||
|
||||
__ movptr(result, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
|
||||
|
||||
// check if locked
|
||||
__ testptr(result, markOopDesc::unlocked_value);
|
||||
__ jcc(Assembler::zero, slowCase);
|
||||
|
||||
if (UseBiasedLocking) {
|
||||
// Check if biased and fall through to runtime if so
|
||||
__ testptr(result, markOopDesc::biased_lock_bit_in_place);
|
||||
__ jcc(Assembler::notZero, slowCase);
|
||||
}
|
||||
|
||||
// get hash
|
||||
#ifdef _LP64
|
||||
// Read the header and build a mask to get its hash field.
|
||||
// Depend on hash_mask being at most 32 bits and avoid the use of hash_mask_in_place
|
||||
// because it could be larger than 32 bits in a 64-bit vm. See markOop.hpp.
|
||||
__ shrptr(result, markOopDesc::hash_shift);
|
||||
__ andptr(result, markOopDesc::hash_mask);
|
||||
#else
|
||||
__ andptr(result, markOopDesc::hash_mask_in_place);
|
||||
#endif //_LP64
|
||||
|
||||
// test if hashCode exists
|
||||
__ jcc(Assembler::zero, slowCase);
|
||||
#ifndef _LP64
|
||||
__ shrptr(result, markOopDesc::hash_shift);
|
||||
#endif
|
||||
__ ret(0);
|
||||
__ bind(slowCase);
|
||||
}
|
||||
#endif //COMPILER1
|
||||
|
||||
|
|
@ -1754,34 +1754,10 @@ nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
|
|||
int vep_offset = ((intptr_t)__ pc()) - start;
|
||||
|
||||
#ifdef COMPILER1
|
||||
if (InlineObjectHash && method->intrinsic_id() == vmIntrinsics::_hashCode) {
|
||||
// Object.hashCode can pull the hashCode from the header word
|
||||
// instead of doing a full VM transition once it's been computed.
|
||||
// Since hashCode is usually polymorphic at call sites we can't do
|
||||
// this optimization at the call site without a lot of work.
|
||||
Label slowCase;
|
||||
Register receiver = rcx;
|
||||
Register result = rax;
|
||||
__ movptr(result, Address(receiver, oopDesc::mark_offset_in_bytes()));
|
||||
|
||||
// check if locked
|
||||
__ testptr(result, markOopDesc::unlocked_value);
|
||||
__ jcc (Assembler::zero, slowCase);
|
||||
|
||||
if (UseBiasedLocking) {
|
||||
// Check if biased and fall through to runtime if so
|
||||
__ testptr(result, markOopDesc::biased_lock_bit_in_place);
|
||||
__ jcc (Assembler::notZero, slowCase);
|
||||
}
|
||||
|
||||
// get hash
|
||||
__ andptr(result, markOopDesc::hash_mask_in_place);
|
||||
// test if hashCode exists
|
||||
__ jcc (Assembler::zero, slowCase);
|
||||
__ shrptr(result, markOopDesc::hash_shift);
|
||||
__ ret(0);
|
||||
__ bind (slowCase);
|
||||
}
|
||||
// For Object.hashCode, System.identityHashCode try to pull hashCode from object header if available.
|
||||
if ((InlineObjectHash && method->intrinsic_id() == vmIntrinsics::_hashCode) || (method->intrinsic_id() == vmIntrinsics::_identityHashCode)) {
|
||||
inline_check_hashcode_from_object_header(masm, method, rcx /*obj_reg*/, rax /*result*/);
|
||||
}
|
||||
#endif // COMPILER1
|
||||
|
||||
// The instruction at the verified entry point must be 5 bytes or longer
|
||||
|
|
|
|||
|
|
@ -2058,6 +2058,13 @@ nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
|
|||
|
||||
int vep_offset = ((intptr_t)__ pc()) - start;
|
||||
|
||||
#ifdef COMPILER1
|
||||
// For Object.hashCode, System.identityHashCode try to pull hashCode from object header if available.
|
||||
if ((InlineObjectHash && method->intrinsic_id() == vmIntrinsics::_hashCode) || (method->intrinsic_id() == vmIntrinsics::_identityHashCode)) {
|
||||
inline_check_hashcode_from_object_header(masm, method, j_rarg0 /*obj_reg*/, rax /*result*/);
|
||||
}
|
||||
#endif // COMPILER1
|
||||
|
||||
// The instruction at the verified entry point must be 5 bytes or longer
|
||||
// because it can be patched on the fly by make_non_entrant. The stack bang
|
||||
// instruction fits that requirement.
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue