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8294100: RISC-V: Move rt_call and xxx_move from SharedRuntime to MacroAssembler
Reviewed-by: shade, fyang
This commit is contained in:
Feilong Jiang
Fei Yang
parent
2283c3244f
commit
742bc041ea
3 changed files with 230 additions and 212 deletions
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@ -3957,3 +3957,206 @@ void MacroAssembler::cmp_l2i(Register dst, Register src1, Register src2, Registe
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neg(dst, dst);
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bind(done);
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}
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// The java_calling_convention describes stack locations as ideal slots on
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// a frame with no abi restrictions. Since we must observe abi restrictions
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// (like the placement of the register window) the slots must be biased by
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// the following value.
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static int reg2offset_in(VMReg r) {
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// Account for saved fp and ra
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// This should really be in_preserve_stack_slots
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return r->reg2stack() * VMRegImpl::stack_slot_size;
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}
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static int reg2offset_out(VMReg r) {
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return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
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}
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// On 64 bit we will store integer like items to the stack as
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// 64 bits items (riscv64 abi) even though java would only store
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// 32bits for a parameter. On 32bit it will simply be 32 bits
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// So this routine will do 32->32 on 32bit and 32->64 on 64bit
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void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp) {
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if (src.first()->is_stack()) {
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if (dst.first()->is_stack()) {
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// stack to stack
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ld(tmp, Address(fp, reg2offset_in(src.first())));
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sd(tmp, Address(sp, reg2offset_out(dst.first())));
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} else {
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// stack to reg
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lw(dst.first()->as_Register(), Address(fp, reg2offset_in(src.first())));
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}
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} else if (dst.first()->is_stack()) {
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// reg to stack
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sd(src.first()->as_Register(), Address(sp, reg2offset_out(dst.first())));
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} else {
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if (dst.first() != src.first()) {
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// 32bits extend sign
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addw(dst.first()->as_Register(), src.first()->as_Register(), zr);
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}
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}
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}
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// An oop arg. Must pass a handle not the oop itself
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void MacroAssembler::object_move(OopMap* map,
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int oop_handle_offset,
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int framesize_in_slots,
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VMRegPair src,
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VMRegPair dst,
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bool is_receiver,
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int* receiver_offset) {
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assert_cond(map != NULL && receiver_offset != NULL);
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// must pass a handle. First figure out the location we use as a handle
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Register rHandle = dst.first()->is_stack() ? t1 : dst.first()->as_Register();
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// See if oop is NULL if it is we need no handle
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if (src.first()->is_stack()) {
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// Oop is already on the stack as an argument
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int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
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map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
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if (is_receiver) {
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*receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
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}
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ld(t0, Address(fp, reg2offset_in(src.first())));
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la(rHandle, Address(fp, reg2offset_in(src.first())));
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// conditionally move a NULL
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Label notZero1;
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bnez(t0, notZero1);
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mv(rHandle, zr);
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bind(notZero1);
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} else {
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// Oop is in a register we must store it to the space we reserve
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// on the stack for oop_handles and pass a handle if oop is non-NULL
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const Register rOop = src.first()->as_Register();
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int oop_slot = -1;
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if (rOop == j_rarg0) {
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oop_slot = 0;
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} else if (rOop == j_rarg1) {
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oop_slot = 1;
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} else if (rOop == j_rarg2) {
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oop_slot = 2;
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} else if (rOop == j_rarg3) {
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oop_slot = 3;
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} else if (rOop == j_rarg4) {
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oop_slot = 4;
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} else if (rOop == j_rarg5) {
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oop_slot = 5;
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} else if (rOop == j_rarg6) {
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oop_slot = 6;
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} else {
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assert(rOop == j_rarg7, "wrong register");
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oop_slot = 7;
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}
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oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
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int offset = oop_slot * VMRegImpl::stack_slot_size;
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map->set_oop(VMRegImpl::stack2reg(oop_slot));
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// Store oop in handle area, may be NULL
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sd(rOop, Address(sp, offset));
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if (is_receiver) {
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*receiver_offset = offset;
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}
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//rOop maybe the same as rHandle
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if (rOop == rHandle) {
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Label isZero;
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beqz(rOop, isZero);
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la(rHandle, Address(sp, offset));
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bind(isZero);
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} else {
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Label notZero2;
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la(rHandle, Address(sp, offset));
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bnez(rOop, notZero2);
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mv(rHandle, zr);
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bind(notZero2);
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}
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}
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// If arg is on the stack then place it otherwise it is already in correct reg.
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if (dst.first()->is_stack()) {
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sd(rHandle, Address(sp, reg2offset_out(dst.first())));
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}
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}
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// A float arg may have to do float reg int reg conversion
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void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp) {
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assert(src.first()->is_stack() && dst.first()->is_stack() ||
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src.first()->is_reg() && dst.first()->is_reg() ||
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src.first()->is_stack() && dst.first()->is_reg(), "Unexpected error");
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if (src.first()->is_stack()) {
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if (dst.first()->is_stack()) {
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lwu(tmp, Address(fp, reg2offset_in(src.first())));
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sw(tmp, Address(sp, reg2offset_out(dst.first())));
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} else if (dst.first()->is_Register()) {
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lwu(dst.first()->as_Register(), Address(fp, reg2offset_in(src.first())));
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} else {
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ShouldNotReachHere();
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}
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} else if (src.first() != dst.first()) {
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if (src.is_single_phys_reg() && dst.is_single_phys_reg()) {
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fmv_s(dst.first()->as_FloatRegister(), src.first()->as_FloatRegister());
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} else {
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ShouldNotReachHere();
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}
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}
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}
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// A long move
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void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp) {
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if (src.first()->is_stack()) {
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if (dst.first()->is_stack()) {
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// stack to stack
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ld(tmp, Address(fp, reg2offset_in(src.first())));
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sd(tmp, Address(sp, reg2offset_out(dst.first())));
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} else {
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// stack to reg
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ld(dst.first()->as_Register(), Address(fp, reg2offset_in(src.first())));
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}
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} else if (dst.first()->is_stack()) {
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// reg to stack
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sd(src.first()->as_Register(), Address(sp, reg2offset_out(dst.first())));
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} else {
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if (dst.first() != src.first()) {
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mv(dst.first()->as_Register(), src.first()->as_Register());
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}
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}
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}
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// A double move
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void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp) {
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assert(src.first()->is_stack() && dst.first()->is_stack() ||
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src.first()->is_reg() && dst.first()->is_reg() ||
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src.first()->is_stack() && dst.first()->is_reg(), "Unexpected error");
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if (src.first()->is_stack()) {
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if (dst.first()->is_stack()) {
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ld(tmp, Address(fp, reg2offset_in(src.first())));
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sd(tmp, Address(sp, reg2offset_out(dst.first())));
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} else if (dst.first()-> is_Register()) {
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ld(dst.first()->as_Register(), Address(fp, reg2offset_in(src.first())));
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} else {
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ShouldNotReachHere();
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}
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} else if (src.first() != dst.first()) {
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if (src.is_single_phys_reg() && dst.is_single_phys_reg()) {
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fmv_d(dst.first()->as_FloatRegister(), src.first()->as_FloatRegister());
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} else {
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ShouldNotReachHere();
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}
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}
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}
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void MacroAssembler::rt_call(address dest, Register tmp) {
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CodeBlob *cb = CodeCache::find_blob(dest);
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if (cb) {
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far_call(RuntimeAddress(dest));
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} else {
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int32_t offset = 0;
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la_patchable(tmp, RuntimeAddress(dest), offset);
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jalr(x1, tmp, offset);
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}
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}
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@ -28,6 +28,7 @@
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#define CPU_RISCV_MACROASSEMBLER_RISCV_HPP
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#include "asm/assembler.hpp"
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#include "code/vmreg.hpp"
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#include "metaprogramming/enableIf.hpp"
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#include "oops/compressedOops.hpp"
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#include "utilities/powerOfTwo.hpp"
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@ -869,6 +870,22 @@ public:
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void vncvt_x_x_w(VectorRegister vd, VectorRegister vs, VectorMask vm = unmasked);
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void vfneg_v(VectorRegister vd, VectorRegister vs);
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// support for argument shuffling
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void move32_64(VMRegPair src, VMRegPair dst, Register tmp = t0);
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void float_move(VMRegPair src, VMRegPair dst, Register tmp = t0);
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void long_move(VMRegPair src, VMRegPair dst, Register tmp = t0);
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void double_move(VMRegPair src, VMRegPair dst, Register tmp = t0);
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void object_move(OopMap* map,
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int oop_handle_offset,
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int framesize_in_slots,
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VMRegPair src,
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VMRegPair dst,
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bool is_receiver,
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int* receiver_offset);
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void rt_call(address dest, Register tmp = t0);
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private:
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#ifdef ASSERT
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@ -219,20 +219,6 @@ bool SharedRuntime::is_wide_vector(int size) {
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return UseRVV;
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}
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// The java_calling_convention describes stack locations as ideal slots on
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// a frame with no abi restrictions. Since we must observe abi restrictions
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// (like the placement of the register window) the slots must be biased by
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// the following value.
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static int reg2offset_in(VMReg r) {
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// Account for saved fp and ra
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// This should really be in_preserve_stack_slots
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return r->reg2stack() * VMRegImpl::stack_slot_size;
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}
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static int reg2offset_out(VMReg r) {
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return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
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}
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// ---------------------------------------------------------------------------
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// Read the array of BasicTypes from a signature, and compute where the
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// arguments should go. Values in the VMRegPair regs array refer to 4-byte
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@ -761,183 +747,6 @@ int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
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return stk_args;
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}
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// On 64 bit we will store integer like items to the stack as
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// 64 bits items (riscv64 abi) even though java would only store
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// 32bits for a parameter. On 32bit it will simply be 32 bits
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// So this routine will do 32->32 on 32bit and 32->64 on 64bit
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static void move32_64(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
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if (src.first()->is_stack()) {
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if (dst.first()->is_stack()) {
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// stack to stack
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__ ld(t0, Address(fp, reg2offset_in(src.first())));
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__ sd(t0, Address(sp, reg2offset_out(dst.first())));
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} else {
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// stack to reg
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__ lw(dst.first()->as_Register(), Address(fp, reg2offset_in(src.first())));
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}
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} else if (dst.first()->is_stack()) {
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// reg to stack
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__ sd(src.first()->as_Register(), Address(sp, reg2offset_out(dst.first())));
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} else {
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if (dst.first() != src.first()) {
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// 32bits extend sign
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__ addw(dst.first()->as_Register(), src.first()->as_Register(), zr);
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}
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}
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}
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// An oop arg. Must pass a handle not the oop itself
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static void object_move(MacroAssembler* masm,
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OopMap* map,
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int oop_handle_offset,
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int framesize_in_slots,
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VMRegPair src,
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VMRegPair dst,
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bool is_receiver,
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int* receiver_offset) {
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// must pass a handle. First figure out the location we use as a handle
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Register rHandle = dst.first()->is_stack() ? t1 : dst.first()->as_Register();
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// See if oop is NULL if it is we need no handle
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if (src.first()->is_stack()) {
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// Oop is already on the stack as an argument
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int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
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map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
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if (is_receiver) {
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*receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
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}
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__ ld(t0, Address(fp, reg2offset_in(src.first())));
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__ la(rHandle, Address(fp, reg2offset_in(src.first())));
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// conditionally move a NULL
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Label notZero1;
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__ bnez(t0, notZero1);
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__ mv(rHandle, zr);
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__ bind(notZero1);
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} else {
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// Oop is in a register we must store it to the space we reserve
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// on the stack for oop_handles and pass a handle if oop is non-NULL
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const Register rOop = src.first()->as_Register();
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int oop_slot = -1;
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if (rOop == j_rarg0) {
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oop_slot = 0;
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} else if (rOop == j_rarg1) {
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oop_slot = 1;
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} else if (rOop == j_rarg2) {
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oop_slot = 2;
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} else if (rOop == j_rarg3) {
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oop_slot = 3;
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} else if (rOop == j_rarg4) {
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oop_slot = 4;
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} else if (rOop == j_rarg5) {
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oop_slot = 5;
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} else if (rOop == j_rarg6) {
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oop_slot = 6;
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} else {
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assert(rOop == j_rarg7, "wrong register");
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oop_slot = 7;
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}
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oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
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int offset = oop_slot * VMRegImpl::stack_slot_size;
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map->set_oop(VMRegImpl::stack2reg(oop_slot));
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// Store oop in handle area, may be NULL
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__ sd(rOop, Address(sp, offset));
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if (is_receiver) {
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*receiver_offset = offset;
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}
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//rOop maybe the same as rHandle
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if (rOop == rHandle) {
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Label isZero;
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__ beqz(rOop, isZero);
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__ la(rHandle, Address(sp, offset));
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__ bind(isZero);
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} else {
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Label notZero2;
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__ la(rHandle, Address(sp, offset));
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__ bnez(rOop, notZero2);
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__ mv(rHandle, zr);
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__ bind(notZero2);
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}
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}
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// If arg is on the stack then place it otherwise it is already in correct reg.
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if (dst.first()->is_stack()) {
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__ sd(rHandle, Address(sp, reg2offset_out(dst.first())));
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}
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}
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// A float arg may have to do float reg int reg conversion
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static void float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
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assert(src.first()->is_stack() && dst.first()->is_stack() ||
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src.first()->is_reg() && dst.first()->is_reg() || src.first()->is_stack() && dst.first()->is_reg(), "Unexpected error");
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if (src.first()->is_stack()) {
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if (dst.first()->is_stack()) {
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__ lwu(t0, Address(fp, reg2offset_in(src.first())));
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__ sw(t0, Address(sp, reg2offset_out(dst.first())));
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} else if (dst.first()->is_Register()) {
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__ lwu(dst.first()->as_Register(), Address(fp, reg2offset_in(src.first())));
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} else {
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ShouldNotReachHere();
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}
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} else if (src.first() != dst.first()) {
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if (src.is_single_phys_reg() && dst.is_single_phys_reg()) {
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__ fmv_s(dst.first()->as_FloatRegister(), src.first()->as_FloatRegister());
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} else {
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ShouldNotReachHere();
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}
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}
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}
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// A long move
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static void long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
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if (src.first()->is_stack()) {
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if (dst.first()->is_stack()) {
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// stack to stack
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__ ld(t0, Address(fp, reg2offset_in(src.first())));
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__ sd(t0, Address(sp, reg2offset_out(dst.first())));
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} else {
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// stack to reg
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__ ld(dst.first()->as_Register(), Address(fp, reg2offset_in(src.first())));
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}
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} else if (dst.first()->is_stack()) {
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// reg to stack
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__ sd(src.first()->as_Register(), Address(sp, reg2offset_out(dst.first())));
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} else {
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if (dst.first() != src.first()) {
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__ mv(dst.first()->as_Register(), src.first()->as_Register());
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}
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}
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}
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// A double move
|
||||
static void double_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
|
||||
assert(src.first()->is_stack() && dst.first()->is_stack() ||
|
||||
src.first()->is_reg() && dst.first()->is_reg() || src.first()->is_stack() && dst.first()->is_reg(), "Unexpected error");
|
||||
if (src.first()->is_stack()) {
|
||||
if (dst.first()->is_stack()) {
|
||||
__ ld(t0, Address(fp, reg2offset_in(src.first())));
|
||||
__ sd(t0, Address(sp, reg2offset_out(dst.first())));
|
||||
} else if (dst.first()-> is_Register()) {
|
||||
__ ld(dst.first()->as_Register(), Address(fp, reg2offset_in(src.first())));
|
||||
} else {
|
||||
ShouldNotReachHere();
|
||||
}
|
||||
} else if (src.first() != dst.first()) {
|
||||
if (src.is_single_phys_reg() && dst.is_single_phys_reg()) {
|
||||
__ fmv_d(dst.first()->as_FloatRegister(), src.first()->as_FloatRegister());
|
||||
} else {
|
||||
ShouldNotReachHere();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
|
||||
// We always ignore the frame_slots arg and just use the space just below frame pointer
|
||||
// which by this time is free to use
|
||||
|
|
@ -1005,17 +814,6 @@ static void restore_args(MacroAssembler *masm, int arg_count, int first_arg, VMR
|
|||
}
|
||||
}
|
||||
|
||||
static void rt_call(MacroAssembler* masm, address dest) {
|
||||
CodeBlob *cb = CodeCache::find_blob(dest);
|
||||
if (cb) {
|
||||
__ far_call(RuntimeAddress(dest));
|
||||
} else {
|
||||
int32_t offset = 0;
|
||||
__ la_patchable(t0, RuntimeAddress(dest), offset);
|
||||
__ jalr(x1, t0, offset);
|
||||
}
|
||||
}
|
||||
|
||||
static void verify_oop_args(MacroAssembler* masm,
|
||||
const methodHandle& method,
|
||||
const BasicType* sig_bt,
|
||||
|
|
@ -1397,16 +1195,16 @@ nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
|
|||
switch (in_sig_bt[i]) {
|
||||
case T_ARRAY:
|
||||
case T_OBJECT:
|
||||
object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg],
|
||||
((i == 0) && (!is_static)),
|
||||
&receiver_offset);
|
||||
__ object_move(map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg],
|
||||
((i == 0) && (!is_static)),
|
||||
&receiver_offset);
|
||||
int_args++;
|
||||
break;
|
||||
case T_VOID:
|
||||
break;
|
||||
|
||||
case T_FLOAT:
|
||||
float_move(masm, in_regs[i], out_regs[c_arg]);
|
||||
__ float_move(in_regs[i], out_regs[c_arg]);
|
||||
float_args++;
|
||||
break;
|
||||
|
||||
|
|
@ -1414,12 +1212,12 @@ nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
|
|||
assert( i + 1 < total_in_args &&
|
||||
in_sig_bt[i + 1] == T_VOID &&
|
||||
out_sig_bt[c_arg + 1] == T_VOID, "bad arg list");
|
||||
double_move(masm, in_regs[i], out_regs[c_arg]);
|
||||
__ double_move(in_regs[i], out_regs[c_arg]);
|
||||
float_args++;
|
||||
break;
|
||||
|
||||
case T_LONG :
|
||||
long_move(masm, in_regs[i], out_regs[c_arg]);
|
||||
__ long_move(in_regs[i], out_regs[c_arg]);
|
||||
int_args++;
|
||||
break;
|
||||
|
||||
|
|
@ -1428,7 +1226,7 @@ nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
|
|||
break;
|
||||
|
||||
default:
|
||||
move32_64(masm, in_regs[i], out_regs[c_arg]);
|
||||
__ move32_64(in_regs[i], out_regs[c_arg]);
|
||||
int_args++;
|
||||
}
|
||||
}
|
||||
|
|
@ -1558,7 +1356,7 @@ nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
|
|||
__ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
|
||||
__ sw(t0, Address(t1));
|
||||
|
||||
rt_call(masm, native_func);
|
||||
__ rt_call(native_func);
|
||||
|
||||
__ bind(native_return);
|
||||
|
||||
|
|
@ -1754,7 +1552,7 @@ nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
|
|||
__ ld(x9, Address(xthread, in_bytes(Thread::pending_exception_offset())));
|
||||
__ sd(zr, Address(xthread, in_bytes(Thread::pending_exception_offset())));
|
||||
|
||||
rt_call(masm, CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C));
|
||||
__ rt_call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C));
|
||||
|
||||
#ifdef ASSERT
|
||||
{
|
||||
|
|
@ -1781,7 +1579,7 @@ nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
|
|||
|
||||
__ bind(reguard);
|
||||
save_native_result(masm, ret_type, stack_slots);
|
||||
rt_call(masm, CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages));
|
||||
__ rt_call(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages));
|
||||
restore_native_result(masm, ret_type, stack_slots);
|
||||
// and continue
|
||||
__ j(reguard_done);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue