8267370: [Vector API] Fix several crashes after JDK-8256973

Co-authored-by: Jatin Bhateja <jbhateja@openjdk.org>
Reviewed-by: neliasso, kvn
This commit is contained in:
Jie Fu 2021-05-20 23:59:12 +00:00
parent 83b3607290
commit 7a63ff70c8
5 changed files with 9 additions and 8 deletions

View file

@ -4123,9 +4123,10 @@ void Assembler::pmovmskb(Register dst, XMMRegister src) {
emit_int16((unsigned char)0xD7, (0xC0 | encode)); emit_int16((unsigned char)0xD7, (0xC0 | encode));
} }
void Assembler::vpmovmskb(Register dst, XMMRegister src) { void Assembler::vpmovmskb(Register dst, XMMRegister src, int vec_enc) {
assert(VM_Version::supports_avx2(), ""); assert((VM_Version::supports_avx() && vec_enc == AVX_128bit) ||
InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); (VM_Version::supports_avx2() && vec_enc == AVX_256bit), "");
InstructionAttr attributes(vec_enc, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
emit_int16((unsigned char)0xD7, (0xC0 | encode)); emit_int16((unsigned char)0xD7, (0xC0 | encode));
} }

View file

@ -1746,7 +1746,7 @@ private:
void vpcmpgtq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); void vpcmpgtq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void pmovmskb(Register dst, XMMRegister src); void pmovmskb(Register dst, XMMRegister src);
void vpmovmskb(Register dst, XMMRegister src); void vpmovmskb(Register dst, XMMRegister src, int vec_enc);
// SSE 4.1 extract // SSE 4.1 extract
void pextrd(Register dst, XMMRegister src, int imm8); void pextrd(Register dst, XMMRegister src, int imm8);

View file

@ -3782,7 +3782,7 @@ void C2_MacroAssembler::vector_mask_operation(int opc, Register dst, XMMRegister
assert(VM_Version::supports_avx(), ""); assert(VM_Version::supports_avx(), "");
vpxor(xtmp, xtmp, xtmp, vec_enc); vpxor(xtmp, xtmp, xtmp, vec_enc);
vpsubb(xtmp, xtmp, mask, vec_enc); vpsubb(xtmp, xtmp, mask, vec_enc);
vpmovmskb(tmp, xtmp); vpmovmskb(tmp, xtmp, vec_enc);
switch(opc) { switch(opc) {
case Op_VectorMaskTrueCount: case Op_VectorMaskTrueCount:
popcntq(dst, tmp); popcntq(dst, tmp);

View file

@ -3216,9 +3216,9 @@ void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
Assembler::vpmovzxbw(dst, src, vector_len); Assembler::vpmovzxbw(dst, src, vector_len);
} }
void MacroAssembler::vpmovmskb(Register dst, XMMRegister src) { void MacroAssembler::vpmovmskb(Register dst, XMMRegister src, int vector_len) {
assert((src->encoding() < 16),"XMM register should be 0-15"); assert((src->encoding() < 16),"XMM register should be 0-15");
Assembler::vpmovmskb(dst, src); Assembler::vpmovmskb(dst, src, vector_len);
} }
void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {

View file

@ -1303,7 +1303,7 @@ public:
void vpmovzxbw(XMMRegister dst, Address src, int vector_len); void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
void vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::vpmovzxbw(dst, src, vector_len); } void vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::vpmovzxbw(dst, src, vector_len); }
void vpmovmskb(Register dst, XMMRegister src); void vpmovmskb(Register dst, XMMRegister src, int vector_len = Assembler::AVX_256bit);
void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len); void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);