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8081778: Use Intel x64 CPU instructions for RSA acceleration

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Add intrinsics for BigInteger squareToLen and mulAdd methods.

Reviewed-by: kvn, jrose
This commit is contained in:
Vladimir Kozlov 2015-06-03 15:02:10 -07:00
parent 7d22d69e0a
commit 93d1573c5e
18 changed files with 1077 additions and 2 deletions
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20
hotspot/src/cpu/x86/vm/assembler_x86.cpp
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@ -2813,6 +2813,13 @@ void Assembler::orl(Register dst, Register src) {
emit_arith(0x0B, 0xC0, dst, src);
}
void Assembler::orl(Address dst, Register src) {
InstructionMark im(this);
prefix(dst, src);
emit_int8(0x09);
emit_operand(src, dst);
}
void Assembler::packuswb(XMMRegister dst, Address src) {
NOT_LP64(assert(VM_Version::supports_sse2(), ""));
assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
@ -6907,6 +6914,19 @@ void Assembler::rclq(Register dst, int imm8) {
}
}
void Assembler::rcrq(Register dst, int imm8) {
assert(isShiftCount(imm8 >> 1), "illegal shift count");
int encode = prefixq_and_encode(dst->encoding());
if (imm8 == 1) {
emit_int8((unsigned char)0xD1);
emit_int8((unsigned char)(0xD8 | encode));
} else {
emit_int8((unsigned char)0xC1);
emit_int8((unsigned char)(0xD8 | encode));
emit_int8(imm8);
}
}
void Assembler::rorq(Register dst, int imm8) {
assert(isShiftCount(imm8 >> 1), "illegal shift count");
int encode = prefixq_and_encode(dst->encoding());