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8158012: Use SW prefetch instructions instead of BIS for allocation prefetches on SPARC Core S4

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Reviewed-by: kvn
This commit is contained in:
Shrinivas Joshi 2016-12-07 09:29:28 -08:00 • committed by Vladimir Kozlov
parent d82ff831ba
commit 985cf43c19
2 changed files with 15 additions and 8 deletions
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12
hotspot/src/cpu/sparc/vm/vm_version_sparc.cpp
View file

@ -89,8 +89,18 @@ void VM_Version::initialize() {
if (is_niagara_plus()) {
if (has_blk_init() && (cache_line_size > 0) && UseTLAB &&
FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
// Use BIS instruction for TLAB allocation prefetch.
if (!has_sparc5_instr()) {
// Use BIS instruction for TLAB allocation prefetch
// on Niagara plus processors other than those based on CoreS4
FLAG_SET_DEFAULT(AllocatePrefetchInstr, 1);
} else {
// On CoreS4 processors use prefetch instruction
// to avoid partial RAW issue, also use prefetch style 3
FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
}
}
}
if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
if (AllocatePrefetchInstr == 0) {

9
hotspot/src/share/vm/opto/macro.cpp
View file

@ -1952,7 +1952,7 @@ Node* PhaseMacroExpand::prefetch_allocation(Node* i_o, Node*& needgc_false,
i_o = pf_phi_abio;
} else if( UseTLAB && AllocatePrefetchStyle == 3 ) {
// Insert a prefetch instruction for each allocation.
// This code is used for SPARC with BIS.
// This code is used to generate 1 prefetch instruction per cache line.
// Generate several prefetch instructions.
uint lines = (length != NULL) ? AllocatePrefetchLines : AllocateInstancePrefetchLines;
@ -1965,11 +1965,8 @@ Node* PhaseMacroExpand::prefetch_allocation(Node* i_o, Node*& needgc_false,
transform_later(cache_adr);
cache_adr = new CastP2XNode(needgc_false, cache_adr);
transform_later(cache_adr);
// For BIS instructions to be emitted, the address must be aligned at cache line size.
// (The VM sets AllocatePrefetchStepSize to the cache line size, unless a value is
// specified at the command line.) If the address is not aligned at cache line size
// boundary, a standard store instruction is triggered (instead of the BIS). For the
// latter, 8-byte alignment is necessary.
// Address is aligned to execute prefetch to the beginning of cache line size
// (it is important when BIS instruction is used on SPARC as prefetch).
Node* mask = _igvn.MakeConX(~(intptr_t)(step_size-1));
cache_adr = new AndXNode(cache_adr, mask);
transform_later(cache_adr);