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6978249: spill between cpu and fpu registers when those moves are fast

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Reviewed-by: kvn
This commit is contained in:
Tom Rodriguez 2010-08-19 14:51:47 -07:00
parent a325f5589a
commit a54b1ff70e
10 changed files with 116 additions and 8 deletions
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14
hotspot/src/cpu/x86/vm/vm_version_x86.cpp
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@ -482,6 +482,15 @@ void VM_Version::get_processor_features() {
}
}
#ifdef COMPILER2
if (UseFPUForSpilling) {
if (UseSSE < 2) {
// Only supported with SSE2+
FLAG_SET_DEFAULT(UseFPUForSpilling, false);
}
}
#endif
assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value");
assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value");
@ -520,6 +529,11 @@ void VM_Version::get_processor_features() {
if( supports_sse4_2() && supports_ht() ) { // Nehalem based cpus
AllocatePrefetchDistance = 192;
AllocatePrefetchLines = 4;
#ifdef COMPILER2
if (AggressiveOpts && FLAG_IS_DEFAULT(UseFPUForSpilling)) {
FLAG_SET_DEFAULT(UseFPUForSpilling, true);
}
#endif
}
}
assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value");