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8225642: ZGC: Crash due to bad oops being spilled to stack in load barriers

Browse source 
Co-authored-by: Stuart Monteith <stuart.monteith@linaro.org>
Reviewed-by: neliasso, pliden
This commit is contained in:
Erik Österlund 2019-07-02 11:33:05 +02:00
parent ec5bfaba53
commit a8842c9f59
9 changed files with 55 additions and 54 deletions
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28
src/hotspot/cpu/aarch64/gc/z/z_aarch64.ad
View file

@ -61,7 +61,7 @@ static void z_load_barrier_slow_reg(MacroAssembler& _masm, Register dst,
// //
// Execute ZGC load barrier (strong) slow path // Execute ZGC load barrier (strong) slow path
// //
instruct loadBarrierSlowReg(iRegP dst, memory mem, rFlagsReg cr, instruct loadBarrierSlowReg(iRegP dst, memory src, rFlagsReg cr,
vRegD_V0 v0, vRegD_V1 v1, vRegD_V2 v2, vRegD_V3 v3, vRegD_V4 v4, vRegD_V0 v0, vRegD_V1 v1, vRegD_V2 v2, vRegD_V3 v3, vRegD_V4 v4,
vRegD_V5 v5, vRegD_V6 v6, vRegD_V7 v7, vRegD_V8 v8, vRegD_V9 v9, vRegD_V5 v5, vRegD_V6 v6, vRegD_V7 v7, vRegD_V8 v8, vRegD_V9 v9,
vRegD_V10 v10, vRegD_V11 v11, vRegD_V12 v12, vRegD_V13 v13, vRegD_V14 v14, vRegD_V10 v10, vRegD_V11 v11, vRegD_V12 v12, vRegD_V13 v13, vRegD_V14 v14,
@ -69,20 +69,22 @@ instruct loadBarrierSlowReg(iRegP dst, memory mem, rFlagsReg cr,
vRegD_V20 v20, vRegD_V21 v21, vRegD_V22 v22, vRegD_V23 v23, vRegD_V24 v24, vRegD_V20 v20, vRegD_V21 v21, vRegD_V22 v22, vRegD_V23 v23, vRegD_V24 v24,
vRegD_V25 v25, vRegD_V26 v26, vRegD_V27 v27, vRegD_V28 v28, vRegD_V29 v29, vRegD_V25 v25, vRegD_V26 v26, vRegD_V27 v27, vRegD_V28 v28, vRegD_V29 v29,
vRegD_V30 v30, vRegD_V31 v31) %{ vRegD_V30 v30, vRegD_V31 v31) %{
match(Set dst (LoadBarrierSlowReg mem)); match(Set dst (LoadBarrierSlowReg src dst));
predicate(!n->as_LoadBarrierSlowReg()->is_weak()); predicate(!n->as_LoadBarrierSlowReg()->is_weak());
effect(DEF dst, KILL cr, effect(KILL cr,
KILL v0, KILL v1, KILL v2, KILL v3, KILL v4, KILL v5, KILL v6, KILL v7, KILL v0, KILL v1, KILL v2, KILL v3, KILL v4, KILL v5, KILL v6, KILL v7,
KILL v8, KILL v9, KILL v10, KILL v11, KILL v12, KILL v13, KILL v14, KILL v8, KILL v9, KILL v10, KILL v11, KILL v12, KILL v13, KILL v14,
KILL v15, KILL v16, KILL v17, KILL v18, KILL v19, KILL v20, KILL v21, KILL v15, KILL v16, KILL v17, KILL v18, KILL v19, KILL v20, KILL v21,
KILL v22, KILL v23, KILL v24, KILL v25, KILL v26, KILL v27, KILL v28, KILL v22, KILL v23, KILL v24, KILL v25, KILL v26, KILL v27, KILL v28,
KILL v29, KILL v30, KILL v31); KILL v29, KILL v30, KILL v31);
format %{"LoadBarrierSlowReg $dst, $mem" %} format %{ "lea $dst, $src\n\t"
"call #ZLoadBarrierSlowPath" %}
ins_encode %{ ins_encode %{
z_load_barrier_slow_reg(_masm, $dst$$Register, $mem$$base$$Register, z_load_barrier_slow_reg(_masm, $dst$$Register, $src$$base$$Register,
$mem$$index, $mem$$scale, $mem$$disp, false); $src$$index, $src$$scale, $src$$disp, false);
%} %}
ins_pipe(pipe_slow); ins_pipe(pipe_slow);
%} %}
@ -90,7 +92,7 @@ instruct loadBarrierSlowReg(iRegP dst, memory mem, rFlagsReg cr,
// //
// Execute ZGC load barrier (weak) slow path // Execute ZGC load barrier (weak) slow path
// //
instruct loadBarrierWeakSlowReg(iRegP dst, memory mem, rFlagsReg cr, instruct loadBarrierWeakSlowReg(iRegP dst, memory src, rFlagsReg cr,
vRegD_V0 v0, vRegD_V1 v1, vRegD_V2 v2, vRegD_V3 v3, vRegD_V4 v4, vRegD_V0 v0, vRegD_V1 v1, vRegD_V2 v2, vRegD_V3 v3, vRegD_V4 v4,
vRegD_V5 v5, vRegD_V6 v6, vRegD_V7 v7, vRegD_V8 v8, vRegD_V9 v9, vRegD_V5 v5, vRegD_V6 v6, vRegD_V7 v7, vRegD_V8 v8, vRegD_V9 v9,
vRegD_V10 v10, vRegD_V11 v11, vRegD_V12 v12, vRegD_V13 v13, vRegD_V14 v14, vRegD_V10 v10, vRegD_V11 v11, vRegD_V12 v12, vRegD_V13 v13, vRegD_V14 v14,
@ -98,20 +100,22 @@ instruct loadBarrierWeakSlowReg(iRegP dst, memory mem, rFlagsReg cr,
vRegD_V20 v20, vRegD_V21 v21, vRegD_V22 v22, vRegD_V23 v23, vRegD_V24 v24, vRegD_V20 v20, vRegD_V21 v21, vRegD_V22 v22, vRegD_V23 v23, vRegD_V24 v24,
vRegD_V25 v25, vRegD_V26 v26, vRegD_V27 v27, vRegD_V28 v28, vRegD_V29 v29, vRegD_V25 v25, vRegD_V26 v26, vRegD_V27 v27, vRegD_V28 v28, vRegD_V29 v29,
vRegD_V30 v30, vRegD_V31 v31) %{ vRegD_V30 v30, vRegD_V31 v31) %{
match(Set dst (LoadBarrierSlowReg mem)); match(Set dst (LoadBarrierSlowReg src dst));
predicate(n->as_LoadBarrierSlowReg()->is_weak()); predicate(n->as_LoadBarrierSlowReg()->is_weak());
effect(DEF dst, KILL cr, effect(KILL cr,
KILL v0, KILL v1, KILL v2, KILL v3, KILL v4, KILL v5, KILL v6, KILL v7, KILL v0, KILL v1, KILL v2, KILL v3, KILL v4, KILL v5, KILL v6, KILL v7,
KILL v8, KILL v9, KILL v10, KILL v11, KILL v12, KILL v13, KILL v14, KILL v8, KILL v9, KILL v10, KILL v11, KILL v12, KILL v13, KILL v14,
KILL v15, KILL v16, KILL v17, KILL v18, KILL v19, KILL v20, KILL v21, KILL v15, KILL v16, KILL v17, KILL v18, KILL v19, KILL v20, KILL v21,
KILL v22, KILL v23, KILL v24, KILL v25, KILL v26, KILL v27, KILL v28, KILL v22, KILL v23, KILL v24, KILL v25, KILL v26, KILL v27, KILL v28,
KILL v29, KILL v30, KILL v31); KILL v29, KILL v30, KILL v31);
format %{"LoadBarrierWeakSlowReg $dst, $mem" %} format %{ "lea $dst, $src\n\t"
"call #ZLoadBarrierSlowPath" %}
ins_encode %{ ins_encode %{
z_load_barrier_slow_reg(_masm, $dst$$Register, $mem$$base$$Register, z_load_barrier_slow_reg(_masm, $dst$$Register, $src$$base$$Register,
$mem$$index, $mem$$scale, $mem$$disp, true); $src$$index, $src$$scale, $src$$disp, true);
%} %}
ins_pipe(pipe_slow); ins_pipe(pipe_slow);
%} %}

50
src/hotspot/cpu/x86/gc/z/z_x86_64.ad
View file

@ -45,32 +45,31 @@ static void z_load_barrier_slow_reg(MacroAssembler& _masm, Register dst, Address
// For XMM and YMM enabled processors // For XMM and YMM enabled processors
instruct zLoadBarrierSlowRegXmmAndYmm(rRegP dst, memory src, rFlagsReg cr, instruct zLoadBarrierSlowRegXmmAndYmm(rRegP dst, memory src, rFlagsReg cr,
rxmm0 x0, rxmm1 x1, rxmm2 x2,rxmm3 x3, rxmm0 x0, rxmm1 x1, rxmm2 x2, rxmm3 x3,
rxmm4 x4, rxmm5 x5, rxmm6 x6, rxmm7 x7, rxmm4 x4, rxmm5 x5, rxmm6 x6, rxmm7 x7,
rxmm8 x8, rxmm9 x9, rxmm10 x10, rxmm11 x11, rxmm8 x8, rxmm9 x9, rxmm10 x10, rxmm11 x11,
rxmm12 x12, rxmm13 x13, rxmm14 x14, rxmm15 x15) %{ rxmm12 x12, rxmm13 x13, rxmm14 x14, rxmm15 x15) %{
match(Set dst (LoadBarrierSlowReg src dst));
predicate(UseAVX <= 2 && !n->as_LoadBarrierSlowReg()->is_weak());
match(Set dst (LoadBarrierSlowReg src)); effect(KILL cr,
predicate((UseAVX <= 2) && !n->as_LoadBarrierSlowReg()->is_weak());
effect(DEF dst, KILL cr,
KILL x0, KILL x1, KILL x2, KILL x3, KILL x0, KILL x1, KILL x2, KILL x3,
KILL x4, KILL x5, KILL x6, KILL x7, KILL x4, KILL x5, KILL x6, KILL x7,
KILL x8, KILL x9, KILL x10, KILL x11, KILL x8, KILL x9, KILL x10, KILL x11,
KILL x12, KILL x13, KILL x14, KILL x15); KILL x12, KILL x13, KILL x14, KILL x15);
format %{ "zLoadBarrierSlowRegXmmAndYmm $dst, $src" %} format %{ "lea $dst, $src\n\t"
"call #ZLoadBarrierSlowPath" %}
ins_encode %{ ins_encode %{
z_load_barrier_slow_reg(_masm, $dst$$Register, $src$$Address, false /* weak */); z_load_barrier_slow_reg(_masm, $dst$$Register, $src$$Address, false /* weak */);
%} %}
ins_pipe(pipe_slow); ins_pipe(pipe_slow);
%} %}
// For ZMM enabled processors // For ZMM enabled processors
instruct zLoadBarrierSlowRegZmm(rRegP dst, memory src, rFlagsReg cr, instruct zLoadBarrierSlowRegZmm(rRegP dst, memory src, rFlagsReg cr,
rxmm0 x0, rxmm1 x1, rxmm2 x2,rxmm3 x3, rxmm0 x0, rxmm1 x1, rxmm2 x2, rxmm3 x3,
rxmm4 x4, rxmm5 x5, rxmm6 x6, rxmm7 x7, rxmm4 x4, rxmm5 x5, rxmm6 x6, rxmm7 x7,
rxmm8 x8, rxmm9 x9, rxmm10 x10, rxmm11 x11, rxmm8 x8, rxmm9 x9, rxmm10 x10, rxmm11 x11,
rxmm12 x12, rxmm13 x13, rxmm14 x14, rxmm15 x15, rxmm12 x12, rxmm13 x13, rxmm14 x14, rxmm15 x15,
@ -79,10 +78,10 @@ instruct zLoadBarrierSlowRegZmm(rRegP dst, memory src, rFlagsReg cr,
rxmm24 x24, rxmm25 x25, rxmm26 x26, rxmm27 x27, rxmm24 x24, rxmm25 x25, rxmm26 x26, rxmm27 x27,
rxmm28 x28, rxmm29 x29, rxmm30 x30, rxmm31 x31) %{ rxmm28 x28, rxmm29 x29, rxmm30 x30, rxmm31 x31) %{
match(Set dst (LoadBarrierSlowReg src)); match(Set dst (LoadBarrierSlowReg src dst));
predicate((UseAVX == 3) && !n->as_LoadBarrierSlowReg()->is_weak()); predicate(UseAVX == 3 && !n->as_LoadBarrierSlowReg()->is_weak());
effect(DEF dst, KILL cr, effect(KILL cr,
KILL x0, KILL x1, KILL x2, KILL x3, KILL x0, KILL x1, KILL x2, KILL x3,
KILL x4, KILL x5, KILL x6, KILL x7, KILL x4, KILL x5, KILL x6, KILL x7,
KILL x8, KILL x9, KILL x10, KILL x11, KILL x8, KILL x9, KILL x10, KILL x11,
@ -92,43 +91,42 @@ instruct zLoadBarrierSlowRegZmm(rRegP dst, memory src, rFlagsReg cr,
KILL x24, KILL x25, KILL x26, KILL x27, KILL x24, KILL x25, KILL x26, KILL x27,
KILL x28, KILL x29, KILL x30, KILL x31); KILL x28, KILL x29, KILL x30, KILL x31);
format %{ "zLoadBarrierSlowRegZmm $dst, $src" %} format %{ "lea $dst, $src\n\t"
"call #ZLoadBarrierSlowPath" %}
ins_encode %{ ins_encode %{
z_load_barrier_slow_reg(_masm, $dst$$Register, $src$$Address, false /* weak */); z_load_barrier_slow_reg(_masm, $dst$$Register, $src$$Address, false /* weak */);
%} %}
ins_pipe(pipe_slow); ins_pipe(pipe_slow);
%} %}
// For XMM and YMM enabled processors // For XMM and YMM enabled processors
instruct zLoadBarrierWeakSlowRegXmmAndYmm(rRegP dst, memory src, rFlagsReg cr, instruct zLoadBarrierWeakSlowRegXmmAndYmm(rRegP dst, memory src, rFlagsReg cr,
rxmm0 x0, rxmm1 x1, rxmm2 x2,rxmm3 x3, rxmm0 x0, rxmm1 x1, rxmm2 x2, rxmm3 x3,
rxmm4 x4, rxmm5 x5, rxmm6 x6, rxmm7 x7, rxmm4 x4, rxmm5 x5, rxmm6 x6, rxmm7 x7,
rxmm8 x8, rxmm9 x9, rxmm10 x10, rxmm11 x11, rxmm8 x8, rxmm9 x9, rxmm10 x10, rxmm11 x11,
rxmm12 x12, rxmm13 x13, rxmm14 x14, rxmm15 x15) %{ rxmm12 x12, rxmm13 x13, rxmm14 x14, rxmm15 x15) %{
match(Set dst (LoadBarrierSlowReg src dst));
predicate(UseAVX <= 2 && n->as_LoadBarrierSlowReg()->is_weak());
match(Set dst (LoadBarrierSlowReg src)); effect(KILL cr,
predicate((UseAVX <= 2) && n->as_LoadBarrierSlowReg()->is_weak());
effect(DEF dst, KILL cr,
KILL x0, KILL x1, KILL x2, KILL x3, KILL x0, KILL x1, KILL x2, KILL x3,
KILL x4, KILL x5, KILL x6, KILL x7, KILL x4, KILL x5, KILL x6, KILL x7,
KILL x8, KILL x9, KILL x10, KILL x11, KILL x8, KILL x9, KILL x10, KILL x11,
KILL x12, KILL x13, KILL x14, KILL x15); KILL x12, KILL x13, KILL x14, KILL x15);
format %{ "zLoadBarrierWeakSlowRegXmmAndYmm $dst, $src" %} format %{ "lea $dst, $src\n\t"
"call #ZLoadBarrierSlowPath" %}
ins_encode %{ ins_encode %{
z_load_barrier_slow_reg(_masm, $dst$$Register, $src$$Address, true /* weak */); z_load_barrier_slow_reg(_masm, $dst$$Register, $src$$Address, true /* weak */);
%} %}
ins_pipe(pipe_slow); ins_pipe(pipe_slow);
%} %}
// For ZMM enabled processors // For ZMM enabled processors
instruct zLoadBarrierWeakSlowRegZmm(rRegP dst, memory src, rFlagsReg cr, instruct zLoadBarrierWeakSlowRegZmm(rRegP dst, memory src, rFlagsReg cr,
rxmm0 x0, rxmm1 x1, rxmm2 x2,rxmm3 x3, rxmm0 x0, rxmm1 x1, rxmm2 x2, rxmm3 x3,
rxmm4 x4, rxmm5 x5, rxmm6 x6, rxmm7 x7, rxmm4 x4, rxmm5 x5, rxmm6 x6, rxmm7 x7,
rxmm8 x8, rxmm9 x9, rxmm10 x10, rxmm11 x11, rxmm8 x8, rxmm9 x9, rxmm10 x10, rxmm11 x11,
rxmm12 x12, rxmm13 x13, rxmm14 x14, rxmm15 x15, rxmm12 x12, rxmm13 x13, rxmm14 x14, rxmm15 x15,
@ -137,10 +135,10 @@ instruct zLoadBarrierWeakSlowRegZmm(rRegP dst, memory src, rFlagsReg cr,
rxmm24 x24, rxmm25 x25, rxmm26 x26, rxmm27 x27, rxmm24 x24, rxmm25 x25, rxmm26 x26, rxmm27 x27,
rxmm28 x28, rxmm29 x29, rxmm30 x30, rxmm31 x31) %{ rxmm28 x28, rxmm29 x29, rxmm30 x30, rxmm31 x31) %{
match(Set dst (LoadBarrierSlowReg src)); match(Set dst (LoadBarrierSlowReg src dst));
predicate((UseAVX == 3) && n->as_LoadBarrierSlowReg()->is_weak()); predicate(UseAVX == 3 && n->as_LoadBarrierSlowReg()->is_weak());
effect(DEF dst, KILL cr, effect(KILL cr,
KILL x0, KILL x1, KILL x2, KILL x3, KILL x0, KILL x1, KILL x2, KILL x3,
KILL x4, KILL x5, KILL x6, KILL x7, KILL x4, KILL x5, KILL x6, KILL x7,
KILL x8, KILL x9, KILL x10, KILL x11, KILL x8, KILL x9, KILL x10, KILL x11,
@ -150,12 +148,12 @@ instruct zLoadBarrierWeakSlowRegZmm(rRegP dst, memory src, rFlagsReg cr,
KILL x24, KILL x25, KILL x26, KILL x27, KILL x24, KILL x25, KILL x26, KILL x27,
KILL x28, KILL x29, KILL x30, KILL x31); KILL x28, KILL x29, KILL x30, KILL x31);
format %{ "zLoadBarrierWeakSlowRegZmm $dst, $src" %} format %{ "lea $dst, $src\n\t"
"call #ZLoadBarrierSlowPath" %}
ins_encode %{ ins_encode %{
z_load_barrier_slow_reg(_masm, $dst$$Register, $src$$Address, true /* weak */); z_load_barrier_slow_reg(_masm, $dst$$Register, $src$$Address, true /* weak */);
%} %}
ins_pipe(pipe_slow); ins_pipe(pipe_slow);
%} %}

2
src/hotspot/share/adlc/formssel.cpp
View file

@ -3513,7 +3513,7 @@ int MatchNode::needs_ideal_memory_edge(FormDict &globals) const {
"GetAndSetB", "GetAndSetS", "GetAndAddI", "GetAndSetI", "GetAndSetP", "GetAndSetB", "GetAndSetS", "GetAndAddI", "GetAndSetI", "GetAndSetP",
"GetAndAddB", "GetAndAddS", "GetAndAddL", "GetAndSetL", "GetAndSetN", "GetAndAddB", "GetAndAddS", "GetAndAddL", "GetAndSetL", "GetAndSetN",
#if INCLUDE_ZGC #if INCLUDE_ZGC
"LoadBarrierSlowReg", "ZGetAndSetP", "ZCompareAndSwapP", "ZCompareAndExchangeP", "ZWeakCompareAndSwapP", "ZGetAndSetP", "ZCompareAndSwapP", "ZCompareAndExchangeP", "ZWeakCompareAndSwapP",
#endif #endif
"ClearArray" "ClearArray"
}; };

5
src/hotspot/share/gc/z/c2/zBarrierSetC2.cpp
View file

@ -540,8 +540,8 @@ void ZBarrierSetC2::expand_loadbarrier_node(PhaseMacroExpand* phase, LoadBarrier
Node* then = igvn.transform(new IfTrueNode(iff)); Node* then = igvn.transform(new IfTrueNode(iff));
Node* elsen = igvn.transform(new IfFalseNode(iff)); Node* elsen = igvn.transform(new IfFalseNode(iff));
Node* new_loadp = igvn.transform(new LoadBarrierSlowRegNode(then, in_mem, in_adr, in_val->adr_type(), Node* new_loadp = igvn.transform(new LoadBarrierSlowRegNode(then, in_adr, in_val,
(const TypePtr*) in_val->bottom_type(), MemNode::unordered, barrier->is_weak())); (const TypePtr*) in_val->bottom_type(), barrier->is_weak()));
// Create the final region/phi pair to converge cntl/data paths to downstream code // Create the final region/phi pair to converge cntl/data paths to downstream code
Node* result_region = igvn.transform(new RegionNode(3)); Node* result_region = igvn.transform(new RegionNode(3));
@ -667,7 +667,6 @@ bool ZBarrierSetC2::final_graph_reshaping(Compile* compile, Node* n, uint opcode
case Op_ZCompareAndExchangeP: case Op_ZCompareAndExchangeP:
case Op_ZCompareAndSwapP: case Op_ZCompareAndSwapP:
case Op_ZWeakCompareAndSwapP: case Op_ZWeakCompareAndSwapP:
case Op_LoadBarrierSlowReg:
#ifdef ASSERT #ifdef ASSERT
if (VerifyOptoOopOffsets) { if (VerifyOptoOopOffsets) {
MemNode *mem = n->as_Mem(); MemNode *mem = n->as_Mem();

19
src/hotspot/share/gc/z/c2/zBarrierSetC2.hpp
View file

@ -104,22 +104,25 @@ public:
} }
}; };
class LoadBarrierSlowRegNode : public LoadPNode { class LoadBarrierSlowRegNode : public TypeNode {
private: private:
bool _is_weak; bool _is_weak;
public: public:
LoadBarrierSlowRegNode(Node *c, LoadBarrierSlowRegNode(Node *c,
Node *mem,
Node *adr, Node *adr,
const TypePtr *at, Node *src,
const TypePtr* t, const TypePtr* t,
MemOrd mo, bool weak) :
bool weak = false, TypeNode(t, 3), _is_weak(weak) {
ControlDependency control_dependency = DependsOnlyOnTest) : init_req(1, adr);
LoadPNode(c, mem, adr, at, t, mo, control_dependency), _is_weak(weak) { init_req(2, src);
init_class_id(Class_LoadBarrierSlowReg); init_class_id(Class_LoadBarrierSlowReg);
} }
virtual uint size_of() const {
return sizeof(*this);
}
virtual const char * name() { virtual const char * name() {
return "LoadBarrierSlowRegNode"; return "LoadBarrierSlowRegNode";
} }

1
src/hotspot/share/opto/lcm.cpp
View file

@ -170,7 +170,6 @@ void PhaseCFG::implicit_null_check(Block* block, Node *proj, Node *val, int allo
case Op_LoadI: case Op_LoadI:
case Op_LoadL: case Op_LoadL:
case Op_LoadP: case Op_LoadP:
case Op_LoadBarrierSlowReg:
case Op_LoadN: case Op_LoadN:
case Op_LoadS: case Op_LoadS:
case Op_LoadKlass: case Op_LoadKlass:

1
src/hotspot/share/opto/loopnode.cpp
View file

@ -4294,7 +4294,6 @@ void PhaseIdealLoop::build_loop_late_post_work(Node *n, bool pinned) {
case Op_LoadL: case Op_LoadL:
case Op_LoadS: case Op_LoadS:
case Op_LoadP: case Op_LoadP:
case Op_LoadBarrierSlowReg:
case Op_LoadN: case Op_LoadN:
case Op_LoadRange: case Op_LoadRange:
case Op_LoadD_unaligned: case Op_LoadD_unaligned:

2
src/hotspot/share/opto/node.hpp
View file

@ -675,6 +675,7 @@ public:
DEFINE_CLASS_ID(EncodeNarrowPtr, Type, 6) DEFINE_CLASS_ID(EncodeNarrowPtr, Type, 6)
DEFINE_CLASS_ID(EncodeP, EncodeNarrowPtr, 0) DEFINE_CLASS_ID(EncodeP, EncodeNarrowPtr, 0)
DEFINE_CLASS_ID(EncodePKlass, EncodeNarrowPtr, 1) DEFINE_CLASS_ID(EncodePKlass, EncodeNarrowPtr, 1)
DEFINE_CLASS_ID(LoadBarrierSlowReg, Type, 7)
DEFINE_CLASS_ID(Proj, Node, 3) DEFINE_CLASS_ID(Proj, Node, 3)
DEFINE_CLASS_ID(CatchProj, Proj, 0) DEFINE_CLASS_ID(CatchProj, Proj, 0)
@ -688,7 +689,6 @@ public:
DEFINE_CLASS_ID(Mem, Node, 4) DEFINE_CLASS_ID(Mem, Node, 4)
DEFINE_CLASS_ID(Load, Mem, 0) DEFINE_CLASS_ID(Load, Mem, 0)
DEFINE_CLASS_ID(LoadVector, Load, 0) DEFINE_CLASS_ID(LoadVector, Load, 0)
DEFINE_CLASS_ID(LoadBarrierSlowReg, Load, 1)
DEFINE_CLASS_ID(Store, Mem, 1) DEFINE_CLASS_ID(Store, Mem, 1)
DEFINE_CLASS_ID(StoreVector, Store, 0) DEFINE_CLASS_ID(StoreVector, Store, 0)
DEFINE_CLASS_ID(LoadStore, Mem, 2) DEFINE_CLASS_ID(LoadStore, Mem, 2)

1
src/hotspot/share/opto/vectornode.cpp
View file

@ -297,7 +297,6 @@ void VectorNode::vector_operands(Node* n, uint* start, uint* end) {
case Op_LoadI: case Op_LoadL: case Op_LoadI: case Op_LoadL:
case Op_LoadF: case Op_LoadD: case Op_LoadF: case Op_LoadD:
case Op_LoadP: case Op_LoadN: case Op_LoadP: case Op_LoadN:
case Op_LoadBarrierSlowReg:
*start = 0; *start = 0;
*end = 0; // no vector operands *end = 0; // no vector operands
break; break;