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7133857: exp() and pow() should use the x87 ISA on x86
Use x87 instructions to implement exp() and pow() in interpreter/c1/c2. Reviewed-by: kvn, never, twisti
This commit is contained in:
Roland Westrelin
parent
eb4a860bc3
commit
b305cf722e
26 changed files with 783 additions and 279 deletions
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@ -3578,6 +3578,21 @@ void Assembler::fyl2x() {
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emit_byte(0xF1);
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}
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void Assembler::frndint() {
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emit_byte(0xD9);
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emit_byte(0xFC);
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}
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void Assembler::f2xm1() {
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emit_byte(0xD9);
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emit_byte(0xF0);
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}
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void Assembler::fldl2e() {
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emit_byte(0xD9);
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emit_byte(0xEA);
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}
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// SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
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static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
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// SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
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@ -6868,6 +6883,242 @@ void MacroAssembler::fldcw(AddressLiteral src) {
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Assembler::fldcw(as_Address(src));
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}
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void MacroAssembler::pow_exp_core_encoding() {
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// kills rax, rcx, rdx
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subptr(rsp,sizeof(jdouble));
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// computes 2^X. Stack: X ...
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// f2xm1 computes 2^X-1 but only operates on -1<=X<=1. Get int(X) and
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// keep it on the thread's stack to compute 2^int(X) later
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// then compute 2^(X-int(X)) as (2^(X-int(X)-1+1)
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// final result is obtained with: 2^X = 2^int(X) * 2^(X-int(X))
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fld_s(0); // Stack: X X ...
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frndint(); // Stack: int(X) X ...
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fsuba(1); // Stack: int(X) X-int(X) ...
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fistp_s(Address(rsp,0)); // move int(X) as integer to thread's stack. Stack: X-int(X) ...
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f2xm1(); // Stack: 2^(X-int(X))-1 ...
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fld1(); // Stack: 1 2^(X-int(X))-1 ...
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faddp(1); // Stack: 2^(X-int(X))
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// computes 2^(int(X)): add exponent bias (1023) to int(X), then
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// shift int(X)+1023 to exponent position.
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// Exponent is limited to 11 bits if int(X)+1023 does not fit in 11
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// bits, set result to NaN. 0x000 and 0x7FF are reserved exponent
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// values so detect them and set result to NaN.
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movl(rax,Address(rsp,0));
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movl(rcx, -2048); // 11 bit mask and valid NaN binary encoding
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addl(rax, 1023);
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movl(rdx,rax);
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shll(rax,20);
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// Check that 0 < int(X)+1023 < 2047. Otherwise set rax to NaN.
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addl(rdx,1);
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// Check that 1 < int(X)+1023+1 < 2048
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// in 3 steps:
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// 1- (int(X)+1023+1)&-2048 == 0 => 0 <= int(X)+1023+1 < 2048
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// 2- (int(X)+1023+1)&-2048 != 0
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// 3- (int(X)+1023+1)&-2048 != 1
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// Do 2- first because addl just updated the flags.
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cmov32(Assembler::equal,rax,rcx);
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cmpl(rdx,1);
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cmov32(Assembler::equal,rax,rcx);
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testl(rdx,rcx);
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cmov32(Assembler::notEqual,rax,rcx);
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movl(Address(rsp,4),rax);
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movl(Address(rsp,0),0);
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fmul_d(Address(rsp,0)); // Stack: 2^X ...
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addptr(rsp,sizeof(jdouble));
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}
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void MacroAssembler::fast_pow() {
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// computes X^Y = 2^(Y * log2(X))
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// if fast computation is not possible, result is NaN. Requires
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// fallback from user of this macro.
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fyl2x(); // Stack: (Y*log2(X)) ...
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pow_exp_core_encoding(); // Stack: exp(X) ...
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}
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void MacroAssembler::fast_exp() {
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// computes exp(X) = 2^(X * log2(e))
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// if fast computation is not possible, result is NaN. Requires
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// fallback from user of this macro.
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fldl2e(); // Stack: log2(e) X ...
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fmulp(1); // Stack: (X*log2(e)) ...
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pow_exp_core_encoding(); // Stack: exp(X) ...
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}
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void MacroAssembler::pow_or_exp(bool is_exp, int num_fpu_regs_in_use) {
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// kills rax, rcx, rdx
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// pow and exp needs 2 extra registers on the fpu stack.
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Label slow_case, done;
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Register tmp = noreg;
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if (!VM_Version::supports_cmov()) {
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// fcmp needs a temporary so preserve rdx,
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tmp = rdx;
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}
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Register tmp2 = rax;
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NOT_LP64(Register tmp3 = rcx;)
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if (is_exp) {
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// Stack: X
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fld_s(0); // duplicate argument for runtime call. Stack: X X
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fast_exp(); // Stack: exp(X) X
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fcmp(tmp, 0, false, false); // Stack: exp(X) X
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// exp(X) not equal to itself: exp(X) is NaN go to slow case.
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jcc(Assembler::parity, slow_case);
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// get rid of duplicate argument. Stack: exp(X)
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if (num_fpu_regs_in_use > 0) {
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fxch();
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fpop();
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} else {
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ffree(1);
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}
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jmp(done);
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} else {
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// Stack: X Y
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Label x_negative, y_odd;
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fldz(); // Stack: 0 X Y
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fcmp(tmp, 1, true, false); // Stack: X Y
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jcc(Assembler::above, x_negative);
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// X >= 0
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fld_s(1); // duplicate arguments for runtime call. Stack: Y X Y
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fld_s(1); // Stack: X Y X Y
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fast_pow(); // Stack: X^Y X Y
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fcmp(tmp, 0, false, false); // Stack: X^Y X Y
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// X^Y not equal to itself: X^Y is NaN go to slow case.
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jcc(Assembler::parity, slow_case);
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// get rid of duplicate arguments. Stack: X^Y
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if (num_fpu_regs_in_use > 0) {
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fxch(); fpop();
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fxch(); fpop();
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} else {
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ffree(2);
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ffree(1);
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}
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jmp(done);
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// X <= 0
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bind(x_negative);
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fld_s(1); // Stack: Y X Y
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frndint(); // Stack: int(Y) X Y
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fcmp(tmp, 2, false, false); // Stack: int(Y) X Y
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jcc(Assembler::notEqual, slow_case);
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subptr(rsp, 8);
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// For X^Y, when X < 0, Y has to be an integer and the final
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// result depends on whether it's odd or even. We just checked
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// that int(Y) == Y. We move int(Y) to gp registers as a 64 bit
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// integer to test its parity. If int(Y) is huge and doesn't fit
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// in the 64 bit integer range, the integer indefinite value will
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// end up in the gp registers. Huge numbers are all even, the
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// integer indefinite number is even so it's fine.
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#ifdef ASSERT
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// Let's check we don't end up with an integer indefinite number
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// when not expected. First test for huge numbers: check whether
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// int(Y)+1 == int(Y) which is true for very large numbers and
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// those are all even. A 64 bit integer is guaranteed to not
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// overflow for numbers where y+1 != y (when precision is set to
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// double precision).
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Label y_not_huge;
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fld1(); // Stack: 1 int(Y) X Y
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fadd(1); // Stack: 1+int(Y) int(Y) X Y
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#ifdef _LP64
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// trip to memory to force the precision down from double extended
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// precision
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fstp_d(Address(rsp, 0));
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fld_d(Address(rsp, 0));
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#endif
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fcmp(tmp, 1, true, false); // Stack: int(Y) X Y
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#endif
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// move int(Y) as 64 bit integer to thread's stack
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fistp_d(Address(rsp,0)); // Stack: X Y
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#ifdef ASSERT
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jcc(Assembler::notEqual, y_not_huge);
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// Y is huge so we know it's even. It may not fit in a 64 bit
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// integer and we don't want the debug code below to see the
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// integer indefinite value so overwrite int(Y) on the thread's
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// stack with 0.
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movl(Address(rsp, 0), 0);
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movl(Address(rsp, 4), 0);
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bind(y_not_huge);
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#endif
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fld_s(1); // duplicate arguments for runtime call. Stack: Y X Y
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fld_s(1); // Stack: X Y X Y
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fabs(); // Stack: abs(X) Y X Y
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fast_pow(); // Stack: abs(X)^Y X Y
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fcmp(tmp, 0, false, false); // Stack: abs(X)^Y X Y
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// abs(X)^Y not equal to itself: abs(X)^Y is NaN go to slow case.
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pop(tmp2);
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NOT_LP64(pop(tmp3));
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jcc(Assembler::parity, slow_case);
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#ifdef ASSERT
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// Check that int(Y) is not integer indefinite value (int
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// overflow). Shouldn't happen because for values that would
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// overflow, 1+int(Y)==Y which was tested earlier.
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#ifndef _LP64
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{
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Label integer;
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testl(tmp2, tmp2);
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jcc(Assembler::notZero, integer);
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cmpl(tmp3, 0x80000000);
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jcc(Assembler::notZero, integer);
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stop("integer indefinite value shouldn't be seen here");
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bind(integer);
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}
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#else
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{
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Label integer;
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shlq(tmp2, 1);
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jcc(Assembler::carryClear, integer);
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jcc(Assembler::notZero, integer);
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stop("integer indefinite value shouldn't be seen here");
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bind(integer);
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}
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#endif
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#endif
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// get rid of duplicate arguments. Stack: X^Y
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if (num_fpu_regs_in_use > 0) {
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fxch(); fpop();
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fxch(); fpop();
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} else {
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ffree(2);
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ffree(1);
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}
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testl(tmp2, 1);
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jcc(Assembler::zero, done); // X <= 0, Y even: X^Y = abs(X)^Y
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// X <= 0, Y even: X^Y = -abs(X)^Y
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fchs(); // Stack: -abs(X)^Y Y
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jmp(done);
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}
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// slow case: runtime call
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bind(slow_case);
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fpop(); // pop incorrect result or int(Y)
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fp_runtime_fallback(is_exp ? CAST_FROM_FN_PTR(address, SharedRuntime::dexp) : CAST_FROM_FN_PTR(address, SharedRuntime::dpow),
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is_exp ? 1 : 2, num_fpu_regs_in_use);
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// Come here with result in F-TOS
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bind(done);
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}
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void MacroAssembler::fpop() {
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ffree();
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fincstp();
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@ -8045,6 +8296,144 @@ void MacroAssembler::incr_allocated_bytes(Register thread,
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#endif
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}
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void MacroAssembler::fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use) {
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pusha();
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// if we are coming from c1, xmm registers may be live
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if (UseSSE >= 1) {
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subptr(rsp, sizeof(jdouble)* LP64_ONLY(16) NOT_LP64(8));
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}
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int off = 0;
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if (UseSSE == 1) {
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movflt(Address(rsp,off++*sizeof(jdouble)),xmm0);
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movflt(Address(rsp,off++*sizeof(jdouble)),xmm1);
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movflt(Address(rsp,off++*sizeof(jdouble)),xmm2);
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movflt(Address(rsp,off++*sizeof(jdouble)),xmm3);
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movflt(Address(rsp,off++*sizeof(jdouble)),xmm4);
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movflt(Address(rsp,off++*sizeof(jdouble)),xmm5);
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movflt(Address(rsp,off++*sizeof(jdouble)),xmm6);
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movflt(Address(rsp,off++*sizeof(jdouble)),xmm7);
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} else if (UseSSE >= 2) {
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movdbl(Address(rsp,off++*sizeof(jdouble)),xmm0);
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movdbl(Address(rsp,off++*sizeof(jdouble)),xmm1);
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movdbl(Address(rsp,off++*sizeof(jdouble)),xmm2);
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movdbl(Address(rsp,off++*sizeof(jdouble)),xmm3);
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movdbl(Address(rsp,off++*sizeof(jdouble)),xmm4);
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movdbl(Address(rsp,off++*sizeof(jdouble)),xmm5);
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movdbl(Address(rsp,off++*sizeof(jdouble)),xmm6);
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movdbl(Address(rsp,off++*sizeof(jdouble)),xmm7);
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#ifdef _LP64
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movdbl(Address(rsp,off++*sizeof(jdouble)),xmm8);
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movdbl(Address(rsp,off++*sizeof(jdouble)),xmm9);
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movdbl(Address(rsp,off++*sizeof(jdouble)),xmm10);
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movdbl(Address(rsp,off++*sizeof(jdouble)),xmm11);
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movdbl(Address(rsp,off++*sizeof(jdouble)),xmm12);
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movdbl(Address(rsp,off++*sizeof(jdouble)),xmm13);
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movdbl(Address(rsp,off++*sizeof(jdouble)),xmm14);
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movdbl(Address(rsp,off++*sizeof(jdouble)),xmm15);
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#endif
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}
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// Preserve registers across runtime call
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int incoming_argument_and_return_value_offset = -1;
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if (num_fpu_regs_in_use > 1) {
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// Must preserve all other FPU regs (could alternatively convert
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// SharedRuntime::dsin, dcos etc. into assembly routines known not to trash
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// FPU state, but can not trust C compiler)
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NEEDS_CLEANUP;
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// NOTE that in this case we also push the incoming argument(s) to
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// the stack and restore it later; we also use this stack slot to
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// hold the return value from dsin, dcos etc.
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for (int i = 0; i < num_fpu_regs_in_use; i++) {
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subptr(rsp, sizeof(jdouble));
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fstp_d(Address(rsp, 0));
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}
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incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1);
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for (int i = nb_args-1; i >= 0; i--) {
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fld_d(Address(rsp, incoming_argument_and_return_value_offset-i*sizeof(jdouble)));
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}
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}
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subptr(rsp, nb_args*sizeof(jdouble));
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for (int i = 0; i < nb_args; i++) {
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fstp_d(Address(rsp, i*sizeof(jdouble)));
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}
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#ifdef _LP64
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if (nb_args > 0) {
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movdbl(xmm0, Address(rsp, 0));
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}
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if (nb_args > 1) {
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movdbl(xmm1, Address(rsp, sizeof(jdouble)));
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}
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assert(nb_args <= 2, "unsupported number of args");
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#endif // _LP64
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// NOTE: we must not use call_VM_leaf here because that requires a
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// complete interpreter frame in debug mode -- same bug as 4387334
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// MacroAssembler::call_VM_leaf_base is perfectly safe and will
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// do proper 64bit abi
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NEEDS_CLEANUP;
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// Need to add stack banging before this runtime call if it needs to
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// be taken; however, there is no generic stack banging routine at
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// the MacroAssembler level
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MacroAssembler::call_VM_leaf_base(runtime_entry, 0);
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#ifdef _LP64
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movsd(Address(rsp, 0), xmm0);
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fld_d(Address(rsp, 0));
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#endif // _LP64
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addptr(rsp, sizeof(jdouble) * nb_args);
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if (num_fpu_regs_in_use > 1) {
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// Must save return value to stack and then restore entire FPU
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// stack except incoming arguments
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fstp_d(Address(rsp, incoming_argument_and_return_value_offset));
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for (int i = 0; i < num_fpu_regs_in_use - nb_args; i++) {
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fld_d(Address(rsp, 0));
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addptr(rsp, sizeof(jdouble));
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}
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fld_d(Address(rsp, (nb_args-1)*sizeof(jdouble)));
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addptr(rsp, sizeof(jdouble) * nb_args);
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}
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off = 0;
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if (UseSSE == 1) {
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movflt(xmm0, Address(rsp,off++*sizeof(jdouble)));
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movflt(xmm1, Address(rsp,off++*sizeof(jdouble)));
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movflt(xmm2, Address(rsp,off++*sizeof(jdouble)));
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movflt(xmm3, Address(rsp,off++*sizeof(jdouble)));
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movflt(xmm4, Address(rsp,off++*sizeof(jdouble)));
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movflt(xmm5, Address(rsp,off++*sizeof(jdouble)));
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movflt(xmm6, Address(rsp,off++*sizeof(jdouble)));
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movflt(xmm7, Address(rsp,off++*sizeof(jdouble)));
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} else if (UseSSE >= 2) {
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movdbl(xmm0, Address(rsp,off++*sizeof(jdouble)));
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movdbl(xmm1, Address(rsp,off++*sizeof(jdouble)));
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movdbl(xmm2, Address(rsp,off++*sizeof(jdouble)));
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movdbl(xmm3, Address(rsp,off++*sizeof(jdouble)));
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movdbl(xmm4, Address(rsp,off++*sizeof(jdouble)));
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movdbl(xmm5, Address(rsp,off++*sizeof(jdouble)));
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movdbl(xmm6, Address(rsp,off++*sizeof(jdouble)));
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movdbl(xmm7, Address(rsp,off++*sizeof(jdouble)));
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#ifdef _LP64
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movdbl(xmm8, Address(rsp,off++*sizeof(jdouble)));
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movdbl(xmm9, Address(rsp,off++*sizeof(jdouble)));
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movdbl(xmm10, Address(rsp,off++*sizeof(jdouble)));
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movdbl(xmm11, Address(rsp,off++*sizeof(jdouble)));
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movdbl(xmm12, Address(rsp,off++*sizeof(jdouble)));
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movdbl(xmm13, Address(rsp,off++*sizeof(jdouble)));
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movdbl(xmm14, Address(rsp,off++*sizeof(jdouble)));
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movdbl(xmm15, Address(rsp,off++*sizeof(jdouble)));
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#endif
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}
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if (UseSSE >= 1) {
|
||||
addptr(rsp, sizeof(jdouble)* LP64_ONLY(16) NOT_LP64(8));
|
||||
}
|
||||
popa();
|
||||
}
|
||||
|
||||
static const double pi_4 = 0.7853981633974483;
|
||||
|
||||
void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) {
|
||||
|
|
@ -8092,73 +8481,27 @@ void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) {
|
|||
|
||||
// slow case: runtime call
|
||||
bind(slow_case);
|
||||
// Preserve registers across runtime call
|
||||
pusha();
|
||||
int incoming_argument_and_return_value_offset = -1;
|
||||
if (num_fpu_regs_in_use > 1) {
|
||||
// Must preserve all other FPU regs (could alternatively convert
|
||||
// SharedRuntime::dsin and dcos into assembly routines known not to trash
|
||||
// FPU state, but can not trust C compiler)
|
||||
NEEDS_CLEANUP;
|
||||
// NOTE that in this case we also push the incoming argument to
|
||||
// the stack and restore it later; we also use this stack slot to
|
||||
// hold the return value from dsin or dcos.
|
||||
for (int i = 0; i < num_fpu_regs_in_use; i++) {
|
||||
subptr(rsp, sizeof(jdouble));
|
||||
fstp_d(Address(rsp, 0));
|
||||
}
|
||||
incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1);
|
||||
fld_d(Address(rsp, incoming_argument_and_return_value_offset));
|
||||
}
|
||||
subptr(rsp, sizeof(jdouble));
|
||||
fstp_d(Address(rsp, 0));
|
||||
#ifdef _LP64
|
||||
movdbl(xmm0, Address(rsp, 0));
|
||||
#endif // _LP64
|
||||
|
||||
// NOTE: we must not use call_VM_leaf here because that requires a
|
||||
// complete interpreter frame in debug mode -- same bug as 4387334
|
||||
// MacroAssembler::call_VM_leaf_base is perfectly safe and will
|
||||
// do proper 64bit abi
|
||||
|
||||
NEEDS_CLEANUP;
|
||||
// Need to add stack banging before this runtime call if it needs to
|
||||
// be taken; however, there is no generic stack banging routine at
|
||||
// the MacroAssembler level
|
||||
switch(trig) {
|
||||
case 's':
|
||||
{
|
||||
MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 0);
|
||||
fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 1, num_fpu_regs_in_use);
|
||||
}
|
||||
break;
|
||||
case 'c':
|
||||
{
|
||||
MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 0);
|
||||
fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 1, num_fpu_regs_in_use);
|
||||
}
|
||||
break;
|
||||
case 't':
|
||||
{
|
||||
MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 0);
|
||||
fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 1, num_fpu_regs_in_use);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
assert(false, "bad intrinsic");
|
||||
break;
|
||||
}
|
||||
#ifdef _LP64
|
||||
movsd(Address(rsp, 0), xmm0);
|
||||
fld_d(Address(rsp, 0));
|
||||
#endif // _LP64
|
||||
addptr(rsp, sizeof(jdouble));
|
||||
if (num_fpu_regs_in_use > 1) {
|
||||
// Must save return value to stack and then restore entire FPU stack
|
||||
fstp_d(Address(rsp, incoming_argument_and_return_value_offset));
|
||||
for (int i = 0; i < num_fpu_regs_in_use; i++) {
|
||||
fld_d(Address(rsp, 0));
|
||||
addptr(rsp, sizeof(jdouble));
|
||||
}
|
||||
}
|
||||
popa();
|
||||
|
||||
// Come here with result in F-TOS
|
||||
bind(done);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue