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8295967: RISC-V: Support negVI/negVL instructions for Vector API

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Reviewed-by: yadongwang, fyang
This commit is contained in:
Dingli Zhang 2022-11-04 09:08:26 +00:00 • committed by Fei Yang
parent 9d3b4ef2ad
commit c116ae75a7
3 changed files with 29 additions and 0 deletions
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4
src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
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@ -725,6 +725,10 @@ void MacroAssembler::vncvt_x_x_w(VectorRegister vd, VectorRegister vs, VectorMas
vnsrl_wx(vd, vs, x0, vm);
}
void MacroAssembler::vneg_v(VectorRegister vd, VectorRegister vs) {
vrsub_vx(vd, x0, vs);
}
void MacroAssembler::vfneg_v(VectorRegister vd, VectorRegister vs) {
vfsgnjn_vv(vd, vs, vs);
}