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8296916: RISC-V: Move some small macro-assembler functions to header file
Reviewed-by: fjiang, yadongwang, shade
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parent
720c3d08c6
commit
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3 changed files with 146 additions and 186 deletions
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@ -345,7 +345,8 @@ class MacroAssembler: public Assembler {
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void membar(uint32_t order_constraint);
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static void membar_mask_to_pred_succ(uint32_t order_constraint, uint32_t& predecessor, uint32_t& successor) {
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static void membar_mask_to_pred_succ(uint32_t order_constraint,
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uint32_t& predecessor, uint32_t& successor) {
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predecessor = (order_constraint >> 2) & 0x3;
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successor = order_constraint & 0x3;
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@ -410,25 +411,86 @@ class MacroAssembler: public Assembler {
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public:
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// Standard pseudo instructions
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void nop();
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void mv(Register Rd, Register Rs);
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void notr(Register Rd, Register Rs);
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void neg(Register Rd, Register Rs);
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void negw(Register Rd, Register Rs);
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void sext_w(Register Rd, Register Rs);
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void zext_b(Register Rd, Register Rs);
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void seqz(Register Rd, Register Rs); // set if = zero
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void snez(Register Rd, Register Rs); // set if != zero
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void sltz(Register Rd, Register Rs); // set if < zero
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void sgtz(Register Rd, Register Rs); // set if > zero
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inline void nop() {
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addi(x0, x0, 0);
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}
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inline void mv(Register Rd, Register Rs) {
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if (Rd != Rs) {
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addi(Rd, Rs, 0);
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}
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}
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inline void notr(Register Rd, Register Rs) {
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xori(Rd, Rs, -1);
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}
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inline void neg(Register Rd, Register Rs) {
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sub(Rd, x0, Rs);
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}
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inline void negw(Register Rd, Register Rs) {
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subw(Rd, x0, Rs);
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}
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inline void sext_w(Register Rd, Register Rs) {
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addiw(Rd, Rs, 0);
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}
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inline void zext_b(Register Rd, Register Rs) {
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andi(Rd, Rs, 0xFF);
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}
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inline void seqz(Register Rd, Register Rs) {
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sltiu(Rd, Rs, 1);
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}
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inline void snez(Register Rd, Register Rs) {
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sltu(Rd, x0, Rs);
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}
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inline void sltz(Register Rd, Register Rs) {
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slt(Rd, Rs, x0);
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}
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inline void sgtz(Register Rd, Register Rs) {
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slt(Rd, x0, Rs);
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}
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// Bit-manipulation extension pseudo instructions
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// zero extend word
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inline void zext_w(Register Rd, Register Rs) {
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add_uw(Rd, Rs, zr);
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}
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// Floating-point data-processing pseudo instructions
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void fmv_s(FloatRegister Rd, FloatRegister Rs);
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void fabs_s(FloatRegister Rd, FloatRegister Rs);
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void fneg_s(FloatRegister Rd, FloatRegister Rs);
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void fmv_d(FloatRegister Rd, FloatRegister Rs);
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void fabs_d(FloatRegister Rd, FloatRegister Rs);
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void fneg_d(FloatRegister Rd, FloatRegister Rs);
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inline void fmv_s(FloatRegister Rd, FloatRegister Rs) {
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if (Rd != Rs) {
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fsgnj_s(Rd, Rs, Rs);
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}
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}
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inline void fabs_s(FloatRegister Rd, FloatRegister Rs) {
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fsgnjx_s(Rd, Rs, Rs);
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}
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inline void fneg_s(FloatRegister Rd, FloatRegister Rs) {
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fsgnjn_s(Rd, Rs, Rs);
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}
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inline void fmv_d(FloatRegister Rd, FloatRegister Rs) {
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if (Rd != Rs) {
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fsgnj_d(Rd, Rs, Rs);
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}
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}
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inline void fabs_d(FloatRegister Rd, FloatRegister Rs) {
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fsgnjx_d(Rd, Rs, Rs);
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}
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inline void fneg_d(FloatRegister Rd, FloatRegister Rs) {
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fsgnjn_d(Rd, Rs, Rs);
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}
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// Control and status pseudo instructions
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void rdinstret(Register Rd); // read instruction-retired counter
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@ -627,12 +689,32 @@ public:
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inline void mvw(Register Rd, int32_t imm32) { mv(Rd, imm32); }
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void mv(Register Rd, Address dest);
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void mv(Register Rd, RegisterOrConstant src);
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void mv(Register Rd, Address dest) {
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assert(dest.getMode() == Address::literal, "Address mode should be Address::literal");
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relocate(dest.rspec(), [&] {
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movptr(Rd, dest.target());
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});
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}
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void mv(Register Rd, RegisterOrConstant src) {
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if (src.is_register()) {
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mv(Rd, src.as_register());
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} else {
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mv(Rd, src.as_constant());
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}
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}
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void movptr(Register Rd, address addr);
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void movptr(Register Rd, address addr, int32_t &offset);
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void movptr(Register Rd, uintptr_t imm64);
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void movptr(Register Rd, address addr) {
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int offset = 0;
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movptr(Rd, addr, offset);
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addi(Rd, Rd, offset);
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}
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inline void movptr(Register Rd, uintptr_t imm64) {
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movptr(Rd, (address)imm64);
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}
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// arith
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void add (Register Rd, Register Rn, int64_t increment, Register temp = t0);
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@ -1158,6 +1240,23 @@ public:
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}
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}
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// vector pseudo instructions
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inline void vmnot_m(VectorRegister vd, VectorRegister vs) {
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vmnand_mm(vd, vs, vs);
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}
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inline void vncvt_x_x_w(VectorRegister vd, VectorRegister vs, VectorMask vm) {
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vnsrl_wx(vd, vs, x0, vm);
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}
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inline void vneg_v(VectorRegister vd, VectorRegister vs) {
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vrsub_vx(vd, vs, x0);
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}
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inline void vfneg_v(VectorRegister vd, VectorRegister vs) {
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vfsgnjn_vv(vd, vs, vs);
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}
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static const int zero_words_block_size;
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void cast_primitive_type(BasicType type, Register Rt) {
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@ -1199,13 +1298,6 @@ public:
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// if [src1 < src2], dst = -1;
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void cmp_l2i(Register dst, Register src1, Register src2, Register tmp = t0);
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// vext
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void vmnot_m(VectorRegister vd, VectorRegister vs);
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void vncvt_x_x_w(VectorRegister vd, VectorRegister vs, VectorMask vm = unmasked);
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void vneg_v(VectorRegister vd, VectorRegister vs);
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void vfneg_v(VectorRegister vd, VectorRegister vs);
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// support for argument shuffling
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void move32_64(VMRegPair src, VMRegPair dst, Register tmp = t0);
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void float_move(VMRegPair src, VMRegPair dst, Register tmp = t0);
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@ -1229,7 +1321,7 @@ public:
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jalr(x1, temp, offset);
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}
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void ret() {
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inline void ret() {
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jalr(x0, x1, 0);
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}
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