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8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
Reviewed-by: kvn, jrose
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7c7b91845f
commit
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24 changed files with 636 additions and 8 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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@ -129,6 +129,7 @@ class Assembler : public AbstractAssembler {
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flog3_op3 = 0x36,
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edge_op3 = 0x36,
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fsrc_op3 = 0x36,
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xmulx_op3 = 0x36,
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impdep2_op3 = 0x37,
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stpartialf_op3 = 0x37,
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jmpl_op3 = 0x38,
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@ -220,6 +221,8 @@ class Assembler : public AbstractAssembler {
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mdtox_opf = 0x110,
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mstouw_opf = 0x111,
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mstosw_opf = 0x113,
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xmulx_opf = 0x115,
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xmulxhi_opf = 0x116,
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mxtod_opf = 0x118,
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mwtos_opf = 0x119,
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@ -1212,6 +1215,9 @@ public:
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void movwtos( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(mftoi_op3) | opf(mwtos_opf) | rs2(s)); }
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void movxtod( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(mftoi_op3) | opf(mxtod_opf) | rs2(s)); }
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void xmulx(Register s1, Register s2, Register d) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(xmulx_op3) | rs1(s1) | opf(xmulx_opf) | rs2(s2)); }
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void xmulxhi(Register s1, Register s2, Register d) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(xmulx_op3) | rs1(s1) | opf(xmulxhi_opf) | rs2(s2)); }
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// Crypto SHA instructions
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void sha1() { sha1_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha1_opf)); }
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