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8222090: Add Hygon Dhyana processor support

Browse source 
Reviewed-by: kvn, dholmes, coleenp, rwestberg
This commit is contained in:
Jinke Fan 2019-04-11 19:36:00 -04:00 • committed by David Holmes
parent 528c411de7
commit d03cf75344
4 changed files with 56 additions and 43 deletions
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2
src/hotspot/cpu/x86/assembler_x86.cpp
View file

@ -3099,7 +3099,7 @@ void Assembler::nop(int i) {
}
return;
}
if (UseAddressNop && VM_Version::is_amd()) {
if (UseAddressNop && VM_Version::is_amd_family()) {
//
// Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
// 1: 0x90

13
src/hotspot/cpu/x86/vm_version_ext_x86.cpp
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013, 2018, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2013, 2019, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -340,6 +340,10 @@ bool VM_Version_Ext::supports_tscinv_ext(void) {
return !is_amd_Barcelona();
}
if (is_hygon()) {
return true;
}
return false;
}
@ -407,6 +411,10 @@ const char* VM_Version_Ext::cpu_family_description(void) {
}
return _family_id_intel[cpu_family_id];
}
if (is_hygon()) {
return "Dhyana";
}
return "Unknown x86";
}
@ -423,6 +431,9 @@ int VM_Version_Ext::cpu_type_description(char* const buf, size_t buf_len) {
} else if (is_amd()) {
cpu_type = "AMD";
x64 = cpu_is_em64t() ? " AMD64" : "";
} else if (is_hygon()) {
cpu_type = "Hygon";
x64 = cpu_is_em64t() ? " AMD64" : "";
} else {
cpu_type = "Unknown x86";
x64 = cpu_is_em64t() ? " x86_64" : "";

52
src/hotspot/cpu/x86/vm_version_x86.cpp
View file

@ -680,7 +680,7 @@ void VM_Version::get_processor_features() {
_features &= ~CPU_HT;
}
if( is_intel() ) { // Intel cpus specific settings
if (is_intel()) { // Intel cpus specific settings
if (is_knights_family()) {
_features &= ~CPU_VZEROUPPER;
}
@ -781,7 +781,7 @@ void VM_Version::get_processor_features() {
FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
}
} else {
if(supports_sse4_1()) {
if (supports_sse4_1()) {
if (FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
FLAG_SET_DEFAULT(UseAESCTRIntrinsics, true);
}
@ -1001,7 +1001,7 @@ void VM_Version::get_processor_features() {
} else if (UseAVX == 1 || UseAVX == 2) {
// 32 bytes vectors (in YMM) are only supported with AVX+
max_vector_size = 32;
} else if (UseAVX > 2 ) {
} else if (UseAVX > 2) {
// 64 bytes vectors (in ZMM) are only supported with AVX 3
max_vector_size = 64;
}
@ -1165,38 +1165,38 @@ void VM_Version::get_processor_features() {
}
}
if( is_amd() ) { // AMD cpus specific settings
if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
if (is_amd_family()) { // AMD cpus specific settings
if (supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop)) {
// Use it on new AMD cpus starting from Opteron.
UseAddressNop = true;
}
if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) {
if (supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift)) {
// Use it on new AMD cpus starting from Opteron.
UseNewLongLShift = true;
}
if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
if (FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper)) {
if (supports_sse4a()) {
UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
} else {
UseXmmLoadAndClearUpper = false;
}
}
if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
if( supports_sse4a() ) {
if (FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll)) {
if (supports_sse4a()) {
UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
} else {
UseXmmRegToRegMoveAll = false;
}
}
if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
if( supports_sse4a() ) {
if (FLAG_IS_DEFAULT(UseXmmI2F)) {
if (supports_sse4a()) {
UseXmmI2F = true;
} else {
UseXmmI2F = false;
}
}
if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
if( supports_sse4a() ) {
if (FLAG_IS_DEFAULT(UseXmmI2D)) {
if (supports_sse4a()) {
UseXmmI2D = true;
} else {
UseXmmI2D = false;
@ -1214,7 +1214,7 @@ void VM_Version::get_processor_features() {
}
// some defaults for AMD family 15h
if ( cpu_family() == 0x15 ) {
if (cpu_family() == 0x15) {
// On family 15h processors default is no sw prefetch
if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
FLAG_SET_DEFAULT(AllocatePrefetchStyle, 0);
@ -1239,8 +1239,8 @@ void VM_Version::get_processor_features() {
}
#endif // COMPILER2
// Some defaults for AMD family 17h
if ( cpu_family() == 0x17 ) {
// Some defaults for AMD family 17h || Hygon family 18h
if (cpu_family() == 0x17 || cpu_family() == 0x18) {
// On family 17h processors use XMM and UnalignedLoadStores for Array Copy
if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
FLAG_SET_DEFAULT(UseXMMForArrayCopy, true);
@ -1256,29 +1256,29 @@ void VM_Version::get_processor_features() {
}
}
if( is_intel() ) { // Intel cpus specific settings
if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
if (is_intel()) { // Intel cpus specific settings
if (FLAG_IS_DEFAULT(UseStoreImmI16)) {
UseStoreImmI16 = false; // don't use it on Intel cpus
}
if( cpu_family() == 6 || cpu_family() == 15 ) {
if( FLAG_IS_DEFAULT(UseAddressNop) ) {
if (cpu_family() == 6 || cpu_family() == 15) {
if (FLAG_IS_DEFAULT(UseAddressNop)) {
// Use it on all Intel cpus starting from PentiumPro
UseAddressNop = true;
}
}
if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
if (FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper)) {
UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
}
if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
if( supports_sse3() ) {
if (FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll)) {
if (supports_sse3()) {
UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
} else {
UseXmmRegToRegMoveAll = false;
}
}
if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
if (cpu_family() == 6 && supports_sse3()) { // New Intel cpus
#ifdef COMPILER2
if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
if (FLAG_IS_DEFAULT(MaxLoopPad)) {
// For new Intel cpus do the next optimization:
// don't align the beginning of a loop if there are enough instructions
// left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
@ -1324,7 +1324,7 @@ void VM_Version::get_processor_features() {
FLAG_SET_DEFAULT(UseIncDec, false);
}
}
if(FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) {
if (FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) {
FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
}
}

32
src/hotspot/cpu/x86/vm_version_x86.hpp
View file

@ -495,13 +495,13 @@ protected:
result |= CPU_CX8;
if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0)
result |= CPU_CMOV;
if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd() &&
if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd_family() &&
_cpuid_info.ext_cpuid1_edx.bits.fxsr != 0))
result |= CPU_FXSR;
// HT flag is set for multi-core processors also.
if (threads_per_core() > 1)
result |= CPU_HT;
if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd() &&
if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd_family() &&
_cpuid_info.ext_cpuid1_edx.bits.mmx != 0))
result |= CPU_MMX;
if (_cpuid_info.std_cpuid1_edx.bits.sse != 0)
@ -553,7 +553,7 @@ protected:
result |= CPU_VNNI;
}
}
if(_cpuid_info.sef_cpuid7_ebx.bits.bmi1 != 0)
if (_cpuid_info.sef_cpuid7_ebx.bits.bmi1 != 0)
result |= CPU_BMI1;
if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0)
result |= CPU_TSC;
@ -567,17 +567,17 @@ protected:
result |= CPU_CLMUL;
if (_cpuid_info.sef_cpuid7_ebx.bits.rtm != 0)
result |= CPU_RTM;
if(_cpuid_info.sef_cpuid7_ebx.bits.adx != 0)
if (_cpuid_info.sef_cpuid7_ebx.bits.adx != 0)
result |= CPU_ADX;
if(_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0)
if (_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0)
result |= CPU_BMI2;
if (_cpuid_info.sef_cpuid7_ebx.bits.sha != 0)
result |= CPU_SHA;
if (_cpuid_info.std_cpuid1_ecx.bits.fma != 0)
result |= CPU_FMA;
// AMD features.
if (is_amd()) {
// AMD|Hygon features.
if (is_amd_family()) {
if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) ||
(_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0))
result |= CPU_3DNOW_PREFETCH;
@ -587,8 +587,8 @@ protected:
result |= CPU_SSE4A;
}
// Intel features.
if(is_intel()) {
if(_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
if (is_intel()) {
if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
result |= CPU_LZCNT;
// for Intel, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw
if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) {
@ -714,6 +714,8 @@ public:
static int cpu_family() { return _cpu;}
static bool is_P6() { return cpu_family() >= 6; }
static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA'
static bool is_hygon() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x6F677948; } // 'ogyH'
static bool is_amd_family() { return is_amd() || is_hygon(); }
static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG'
static bool is_zx() { assert_is_initialized(); return (_cpuid_info.std_vendor_name_0 == 0x746e6543) || (_cpuid_info.std_vendor_name_0 == 0x68532020); } // 'tneC'||'hS '
static bool is_atom_family() { return ((cpu_family() == 0x06) && ((extended_cpu_model() == 0x36) || (extended_cpu_model() == 0x37) || (extended_cpu_model() == 0x4D))); } //Silvermont and Centerton
@ -737,7 +739,7 @@ public:
if (!supports_topology || result == 0) {
result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1);
}
} else if (is_amd()) {
} else if (is_amd_family()) {
result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1);
} else if (is_zx()) {
bool supports_topology = supports_processor_topology();
@ -773,7 +775,7 @@ public:
intx result = 0;
if (is_intel()) {
result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
} else if (is_amd()) {
} else if (is_amd_family()) {
result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size;
} else if (is_zx()) {
result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
@ -860,7 +862,7 @@ public:
// AMD features
static bool supports_3dnow_prefetch() { return (_features & CPU_3DNOW_PREFETCH) != 0; }
static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; }
static bool supports_mmx_ext() { return is_amd_family() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; }
static bool supports_lzcnt() { return (_features & CPU_LZCNT) != 0; }
static bool supports_sse4a() { return (_features & CPU_SSE4A) != 0; }
@ -873,8 +875,8 @@ public:
}
static bool supports_tscinv() {
return supports_tscinv_bit() &&
( (is_amd() && !is_amd_Barcelona()) ||
is_intel_tsc_synched_at_init() );
((is_amd_family() && !is_amd_Barcelona()) ||
is_intel_tsc_synched_at_init());
}
// Intel Core and newer cpus have fast IDIV instruction (excluding Atom).
@ -899,7 +901,7 @@ public:
// Core - 256 / prefetchnta
// It will be used only when AllocatePrefetchStyle > 0
if (is_amd()) { // AMD
if (is_amd_family()) { // AMD | Hygon
if (supports_sse2()) {
return 256; // Opteron
} else {