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8002074: Support for AES on SPARC
Add intrinsics/stub routines support for single-block and multi-block (as used by Cipher Block Chaining mode) AES encryption and decryption operations on the SPARC platform. Reviewed-by: kvn, roland
This commit is contained in:
Shrinivas Joshi
Vladimir Kozlov
parent
b1c92a140b
commit
d4c9d3889b
14 changed files with 1022 additions and 54 deletions
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@ -88,6 +88,7 @@ class Assembler : public AbstractAssembler {
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orncc_op3 = 0x16,
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xnorcc_op3 = 0x17,
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addccc_op3 = 0x18,
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aes4_op3 = 0x19,
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umulcc_op3 = 0x1a,
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smulcc_op3 = 0x1b,
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subccc_op3 = 0x1c,
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@ -121,6 +122,8 @@ class Assembler : public AbstractAssembler {
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fpop1_op3 = 0x34,
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fpop2_op3 = 0x35,
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impdep1_op3 = 0x36,
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aes3_op3 = 0x36,
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flog3_op3 = 0x36,
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impdep2_op3 = 0x37,
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jmpl_op3 = 0x38,
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rett_op3 = 0x39,
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@ -172,41 +175,56 @@ class Assembler : public AbstractAssembler {
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enum opfs {
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// selected opfs
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fmovs_opf = 0x01,
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fmovd_opf = 0x02,
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fmovs_opf = 0x01,
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fmovd_opf = 0x02,
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fnegs_opf = 0x05,
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fnegd_opf = 0x06,
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fnegs_opf = 0x05,
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fnegd_opf = 0x06,
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fadds_opf = 0x41,
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faddd_opf = 0x42,
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fsubs_opf = 0x45,
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fsubd_opf = 0x46,
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fadds_opf = 0x41,
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faddd_opf = 0x42,
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fsubs_opf = 0x45,
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fsubd_opf = 0x46,
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fmuls_opf = 0x49,
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fmuld_opf = 0x4a,
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fdivs_opf = 0x4d,
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fdivd_opf = 0x4e,
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fmuls_opf = 0x49,
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fmuld_opf = 0x4a,
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fdivs_opf = 0x4d,
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fdivd_opf = 0x4e,
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fcmps_opf = 0x51,
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fcmpd_opf = 0x52,
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fcmps_opf = 0x51,
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fcmpd_opf = 0x52,
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fstox_opf = 0x81,
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fdtox_opf = 0x82,
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fxtos_opf = 0x84,
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fxtod_opf = 0x88,
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fitos_opf = 0xc4,
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fdtos_opf = 0xc6,
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fitod_opf = 0xc8,
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fstod_opf = 0xc9,
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fstoi_opf = 0xd1,
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fdtoi_opf = 0xd2,
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fstox_opf = 0x81,
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fdtox_opf = 0x82,
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fxtos_opf = 0x84,
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fxtod_opf = 0x88,
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fitos_opf = 0xc4,
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fdtos_opf = 0xc6,
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fitod_opf = 0xc8,
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fstod_opf = 0xc9,
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fstoi_opf = 0xd1,
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fdtoi_opf = 0xd2,
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mdtox_opf = 0x110,
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mstouw_opf = 0x111,
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mstosw_opf = 0x113,
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mxtod_opf = 0x118,
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mwtos_opf = 0x119
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mdtox_opf = 0x110,
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mstouw_opf = 0x111,
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mstosw_opf = 0x113,
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mxtod_opf = 0x118,
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mwtos_opf = 0x119,
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aes_kexpand0_opf = 0x130,
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aes_kexpand2_opf = 0x131
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};
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enum op5s {
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aes_eround01_op5 = 0x00,
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aes_eround23_op5 = 0x01,
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aes_dround01_op5 = 0x02,
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aes_dround23_op5 = 0x03,
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aes_eround01_l_op5 = 0x04,
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aes_eround23_l_op5 = 0x05,
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aes_dround01_l_op5 = 0x06,
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aes_dround23_l_op5 = 0x07,
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aes_kexpand1_op5 = 0x08
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};
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enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7, rc_last = rc_gez };
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@ -427,6 +445,7 @@ class Assembler : public AbstractAssembler {
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static int immed( bool i) { return u_field(i ? 1 : 0, 13, 13); }
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static int opf_low6( int w) { return u_field(w, 10, 5); }
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static int opf_low5( int w) { return u_field(w, 9, 5); }
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static int op5( int x) { return u_field(x, 8, 5); }
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static int trapcc( CC cc) { return u_field(cc, 12, 11); }
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static int sx( int i) { return u_field(i, 12, 12); } // shift x=1 means 64-bit
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static int opf( int x) { return u_field(x, 13, 5); }
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@ -451,6 +470,7 @@ class Assembler : public AbstractAssembler {
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static int fd( FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); };
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static int fs1(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); };
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static int fs2(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 4, 0); };
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static int fs3(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 13, 9); };
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// some float instructions use this encoding on the op3 field
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static int alt_op3(int op, FloatRegisterImpl::Width w) {
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@ -559,6 +579,12 @@ class Assembler : public AbstractAssembler {
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return x & ((1 << 10) - 1);
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}
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// AES crypto instructions supported only on certain processors
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static void aes_only() { assert( VM_Version::has_aes(), "This instruction only works on SPARC with AES instructions support"); }
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// instruction only in VIS1
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static void vis1_only() { assert( VM_Version::has_vis1(), "This instruction only works on SPARC with VIS1"); }
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// instruction only in VIS3
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static void vis3_only() { assert( VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); }
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@ -682,6 +708,24 @@ public:
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void addccc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
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// 4-operand AES instructions
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void aes_eround01( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround01_op5) | fs2(s2, FloatRegisterImpl::D) ); }
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void aes_eround23( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround23_op5) | fs2(s2, FloatRegisterImpl::D) ); }
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void aes_dround01( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround01_op5) | fs2(s2, FloatRegisterImpl::D) ); }
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void aes_dround23( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround23_op5) | fs2(s2, FloatRegisterImpl::D) ); }
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void aes_eround01_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround01_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
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void aes_eround23_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround23_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
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void aes_dround01_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround01_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
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void aes_dround23_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround23_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
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void aes_kexpand1( FloatRegister s1, FloatRegister s2, int imm5a, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | u_field(imm5a, 13, 9) | op5(aes_kexpand1_op5) | fs2(s2, FloatRegisterImpl::D) ); }
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// 3-operand AES instructions
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void aes_kexpand0( FloatRegister s1, FloatRegister s2, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes3_op3) | fs1(s1, FloatRegisterImpl::D) | opf(aes_kexpand0_opf) | fs2(s2, FloatRegisterImpl::D) ); }
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void aes_kexpand2( FloatRegister s1, FloatRegister s2, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes3_op3) | fs1(s1, FloatRegisterImpl::D) | opf(aes_kexpand2_opf) | fs2(s2, FloatRegisterImpl::D) ); }
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// pp 136
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inline void bpr(RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none);
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@ -784,6 +828,10 @@ public:
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void fmul( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | fs1(s1, sw) | opf(0x60 + sw + dw*4) | fs2(s2, sw)); }
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void fdiv( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x4c + w) | fs2(s2, w)); }
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// FXORs/FXORd instructions
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void fxor( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(flog3_op3) | fs1(s1, w) | opf(0x6E - w) | fs2(s2, w)); }
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// pp 164
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void fsqrt( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x28 + w) | fs2(s, w)); }
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