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https://github.com/openjdk/jdk.git
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6985015: C1 needs to support compressed oops
This change implements compressed oops for C1 for x64 and sparc. The changes are mostly on the codegen level, with a few exceptions when we do access things outside of the heap that are uncompressed from the IR. Compressed oops are now also enabled with tiered. Reviewed-by: twisti, kvn, never, phh
This commit is contained in:
Igor Veresov
parent
8006fe8f75
commit
d59d7ffc4a
30 changed files with 493 additions and 429 deletions
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@ -100,6 +100,11 @@ bool LIR_Assembler::is_single_instruction(LIR_Op* op) {
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return false;
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}
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if (UseCompressedOops) {
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if (dst->is_address() && !dst->is_stack() && (dst->type() == T_OBJECT || dst->type() == T_ARRAY)) return false;
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if (src->is_address() && !src->is_stack() && (src->type() == T_OBJECT || src->type() == T_ARRAY)) return false;
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}
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if (dst->is_register()) {
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if (src->is_address() && Assembler::is_simm13(src->as_address_ptr()->disp())) {
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return !PatchALot;
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@ -253,7 +258,7 @@ void LIR_Assembler::emit_string_compare(LIR_Opr left, LIR_Opr right, LIR_Opr dst
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int offset_offset = java_lang_String::offset_offset_in_bytes(); // first character position
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int count_offset = java_lang_String:: count_offset_in_bytes();
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__ ld_ptr(str0, value_offset, tmp0);
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__ load_heap_oop(str0, value_offset, tmp0);
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__ ld(str0, offset_offset, tmp2);
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__ add(tmp0, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp0);
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__ ld(str0, count_offset, str0);
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@ -262,7 +267,7 @@ void LIR_Assembler::emit_string_compare(LIR_Opr left, LIR_Opr right, LIR_Opr dst
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// str1 may be null
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add_debug_info_for_null_check_here(info);
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__ ld_ptr(str1, value_offset, tmp1);
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__ load_heap_oop(str1, value_offset, tmp1);
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__ add(tmp0, tmp2, tmp0);
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__ ld(str1, offset_offset, tmp2);
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@ -766,7 +771,7 @@ void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
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void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
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add_debug_info_for_null_check_here(op->info());
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__ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), G3_scratch);
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__ load_klass(O0, G3_scratch);
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if (__ is_simm13(op->vtable_offset())) {
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__ ld_ptr(G3_scratch, op->vtable_offset(), G5_method);
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} else {
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@ -780,138 +785,17 @@ void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
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// the peephole pass fills the delay slot
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}
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// load with 32-bit displacement
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int LIR_Assembler::load(Register s, int disp, Register d, BasicType ld_type, CodeEmitInfo *info) {
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int load_offset = code_offset();
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if (Assembler::is_simm13(disp)) {
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if (info != NULL) add_debug_info_for_null_check_here(info);
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switch(ld_type) {
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case T_BOOLEAN: // fall through
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case T_BYTE : __ ldsb(s, disp, d); break;
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case T_CHAR : __ lduh(s, disp, d); break;
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case T_SHORT : __ ldsh(s, disp, d); break;
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case T_INT : __ ld(s, disp, d); break;
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case T_ADDRESS:// fall through
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case T_ARRAY : // fall through
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case T_OBJECT: __ ld_ptr(s, disp, d); break;
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default : ShouldNotReachHere();
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}
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} else {
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__ set(disp, O7);
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if (info != NULL) add_debug_info_for_null_check_here(info);
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load_offset = code_offset();
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switch(ld_type) {
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case T_BOOLEAN: // fall through
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case T_BYTE : __ ldsb(s, O7, d); break;
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case T_CHAR : __ lduh(s, O7, d); break;
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case T_SHORT : __ ldsh(s, O7, d); break;
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case T_INT : __ ld(s, O7, d); break;
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case T_ADDRESS:// fall through
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case T_ARRAY : // fall through
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case T_OBJECT: __ ld_ptr(s, O7, d); break;
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default : ShouldNotReachHere();
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}
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}
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if (ld_type == T_ARRAY || ld_type == T_OBJECT) __ verify_oop(d);
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return load_offset;
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}
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// store with 32-bit displacement
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void LIR_Assembler::store(Register value, Register base, int offset, BasicType type, CodeEmitInfo *info) {
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if (Assembler::is_simm13(offset)) {
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if (info != NULL) add_debug_info_for_null_check_here(info);
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switch (type) {
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case T_BOOLEAN: // fall through
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case T_BYTE : __ stb(value, base, offset); break;
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case T_CHAR : __ sth(value, base, offset); break;
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case T_SHORT : __ sth(value, base, offset); break;
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case T_INT : __ stw(value, base, offset); break;
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case T_ADDRESS:// fall through
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case T_ARRAY : // fall through
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case T_OBJECT: __ st_ptr(value, base, offset); break;
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default : ShouldNotReachHere();
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}
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} else {
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__ set(offset, O7);
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if (info != NULL) add_debug_info_for_null_check_here(info);
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switch (type) {
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case T_BOOLEAN: // fall through
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case T_BYTE : __ stb(value, base, O7); break;
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case T_CHAR : __ sth(value, base, O7); break;
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case T_SHORT : __ sth(value, base, O7); break;
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case T_INT : __ stw(value, base, O7); break;
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case T_ADDRESS:// fall through
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case T_ARRAY : //fall through
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case T_OBJECT: __ st_ptr(value, base, O7); break;
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default : ShouldNotReachHere();
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}
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}
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// Note: Do the store before verification as the code might be patched!
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if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(value);
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}
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// load float with 32-bit displacement
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void LIR_Assembler::load(Register s, int disp, FloatRegister d, BasicType ld_type, CodeEmitInfo *info) {
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FloatRegisterImpl::Width w;
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switch(ld_type) {
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case T_FLOAT : w = FloatRegisterImpl::S; break;
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case T_DOUBLE: w = FloatRegisterImpl::D; break;
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default : ShouldNotReachHere();
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}
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if (Assembler::is_simm13(disp)) {
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if (info != NULL) add_debug_info_for_null_check_here(info);
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if (disp % BytesPerLong != 0 && w == FloatRegisterImpl::D) {
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__ ldf(FloatRegisterImpl::S, s, disp + BytesPerWord, d->successor());
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__ ldf(FloatRegisterImpl::S, s, disp , d);
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} else {
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__ ldf(w, s, disp, d);
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}
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} else {
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__ set(disp, O7);
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if (info != NULL) add_debug_info_for_null_check_here(info);
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__ ldf(w, s, O7, d);
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}
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}
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// store float with 32-bit displacement
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void LIR_Assembler::store(FloatRegister value, Register base, int offset, BasicType type, CodeEmitInfo *info) {
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FloatRegisterImpl::Width w;
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switch(type) {
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case T_FLOAT : w = FloatRegisterImpl::S; break;
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case T_DOUBLE: w = FloatRegisterImpl::D; break;
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default : ShouldNotReachHere();
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}
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if (Assembler::is_simm13(offset)) {
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if (info != NULL) add_debug_info_for_null_check_here(info);
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if (w == FloatRegisterImpl::D && offset % BytesPerLong != 0) {
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__ stf(FloatRegisterImpl::S, value->successor(), base, offset + BytesPerWord);
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__ stf(FloatRegisterImpl::S, value , base, offset);
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} else {
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__ stf(w, value, base, offset);
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}
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} else {
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__ set(offset, O7);
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if (info != NULL) add_debug_info_for_null_check_here(info);
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__ stf(w, value, O7, base);
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}
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}
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int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool unaligned) {
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int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned) {
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int store_offset;
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if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
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assert(!unaligned, "can't handle this");
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// for offsets larger than a simm13 we setup the offset in O7
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__ set(offset, O7);
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store_offset = store(from_reg, base, O7, type);
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store_offset = store(from_reg, base, O7, type, wide);
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} else {
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if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(from_reg->as_register());
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if (type == T_ARRAY || type == T_OBJECT) {
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__ verify_oop(from_reg->as_register());
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}
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store_offset = code_offset();
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switch (type) {
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case T_BOOLEAN: // fall through
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@ -934,9 +818,22 @@ int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType
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__ stw(from_reg->as_register_hi(), base, offset + hi_word_offset_in_bytes);
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#endif
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break;
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case T_ADDRESS:// fall through
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case T_ADDRESS:
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__ st_ptr(from_reg->as_register(), base, offset);
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break;
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case T_ARRAY : // fall through
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case T_OBJECT: __ st_ptr(from_reg->as_register(), base, offset); break;
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case T_OBJECT:
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{
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if (UseCompressedOops && !wide) {
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__ encode_heap_oop(from_reg->as_register(), G3_scratch);
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store_offset = code_offset();
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__ stw(G3_scratch, base, offset);
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} else {
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__ st_ptr(from_reg->as_register(), base, offset);
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}
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break;
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}
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case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, offset); break;
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case T_DOUBLE:
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{
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@ -958,8 +855,10 @@ int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType
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}
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int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type) {
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if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(from_reg->as_register());
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int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) {
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if (type == T_ARRAY || type == T_OBJECT) {
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__ verify_oop(from_reg->as_register());
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}
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int store_offset = code_offset();
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switch (type) {
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case T_BOOLEAN: // fall through
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@ -975,9 +874,21 @@ int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicTy
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__ std(from_reg->as_register_hi(), base, disp);
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#endif
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break;
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case T_ADDRESS:// fall through
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case T_ADDRESS:
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__ st_ptr(from_reg->as_register(), base, disp);
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break;
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case T_ARRAY : // fall through
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case T_OBJECT: __ st_ptr(from_reg->as_register(), base, disp); break;
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case T_OBJECT:
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{
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if (UseCompressedOops && !wide) {
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__ encode_heap_oop(from_reg->as_register(), G3_scratch);
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store_offset = code_offset();
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__ stw(G3_scratch, base, disp);
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} else {
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__ st_ptr(from_reg->as_register(), base, disp);
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}
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break;
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}
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case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, disp); break;
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case T_DOUBLE: __ stf(FloatRegisterImpl::D, from_reg->as_double_reg(), base, disp); break;
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default : ShouldNotReachHere();
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@ -986,14 +897,14 @@ int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicTy
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}
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int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool unaligned) {
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int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned) {
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int load_offset;
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if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
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assert(base != O7, "destroying register");
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assert(!unaligned, "can't handle this");
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// for offsets larger than a simm13 we setup the offset in O7
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__ set(offset, O7);
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load_offset = load(base, O7, to_reg, type);
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load_offset = load(base, O7, to_reg, type, wide);
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} else {
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load_offset = code_offset();
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switch(type) {
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@ -1030,9 +941,18 @@ int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType typ
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#endif
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}
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break;
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case T_ADDRESS:// fall through
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case T_ADDRESS: __ ld_ptr(base, offset, to_reg->as_register()); break;
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case T_ARRAY : // fall through
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case T_OBJECT: __ ld_ptr(base, offset, to_reg->as_register()); break;
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case T_OBJECT:
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{
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if (UseCompressedOops && !wide) {
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__ lduw(base, offset, to_reg->as_register());
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__ decode_heap_oop(to_reg->as_register());
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} else {
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__ ld_ptr(base, offset, to_reg->as_register());
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}
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break;
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}
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case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, offset, to_reg->as_float_reg()); break;
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case T_DOUBLE:
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{
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@ -1048,23 +968,34 @@ int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType typ
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}
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default : ShouldNotReachHere();
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}
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if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(to_reg->as_register());
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if (type == T_ARRAY || type == T_OBJECT) {
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__ verify_oop(to_reg->as_register());
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}
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}
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return load_offset;
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}
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int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type) {
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int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) {
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int load_offset = code_offset();
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switch(type) {
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case T_BOOLEAN: // fall through
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case T_BYTE : __ ldsb(base, disp, to_reg->as_register()); break;
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case T_CHAR : __ lduh(base, disp, to_reg->as_register()); break;
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case T_SHORT : __ ldsh(base, disp, to_reg->as_register()); break;
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case T_INT : __ ld(base, disp, to_reg->as_register()); break;
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case T_ADDRESS:// fall through
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case T_BYTE : __ ldsb(base, disp, to_reg->as_register()); break;
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case T_CHAR : __ lduh(base, disp, to_reg->as_register()); break;
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case T_SHORT : __ ldsh(base, disp, to_reg->as_register()); break;
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case T_INT : __ ld(base, disp, to_reg->as_register()); break;
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case T_ADDRESS: __ ld_ptr(base, disp, to_reg->as_register()); break;
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case T_ARRAY : // fall through
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case T_OBJECT: __ ld_ptr(base, disp, to_reg->as_register()); break;
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case T_OBJECT:
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{
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if (UseCompressedOops && !wide) {
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__ lduw(base, disp, to_reg->as_register());
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__ decode_heap_oop(to_reg->as_register());
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} else {
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__ ld_ptr(base, disp, to_reg->as_register());
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}
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break;
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}
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case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, disp, to_reg->as_float_reg()); break;
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case T_DOUBLE: __ ldf(FloatRegisterImpl::D, base, disp, to_reg->as_double_reg()); break;
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case T_LONG :
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@ -1078,61 +1009,17 @@ int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType
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break;
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default : ShouldNotReachHere();
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}
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if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(to_reg->as_register());
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if (type == T_ARRAY || type == T_OBJECT) {
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__ verify_oop(to_reg->as_register());
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}
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return load_offset;
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}
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// load/store with an Address
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void LIR_Assembler::load(const Address& a, Register d, BasicType ld_type, CodeEmitInfo *info, int offset) {
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load(a.base(), a.disp() + offset, d, ld_type, info);
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}
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void LIR_Assembler::store(Register value, const Address& dest, BasicType type, CodeEmitInfo *info, int offset) {
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store(value, dest.base(), dest.disp() + offset, type, info);
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}
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// loadf/storef with an Address
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void LIR_Assembler::load(const Address& a, FloatRegister d, BasicType ld_type, CodeEmitInfo *info, int offset) {
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load(a.base(), a.disp() + offset, d, ld_type, info);
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}
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void LIR_Assembler::store(FloatRegister value, const Address& dest, BasicType type, CodeEmitInfo *info, int offset) {
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store(value, dest.base(), dest.disp() + offset, type, info);
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}
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// load/store with an Address
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void LIR_Assembler::load(LIR_Address* a, Register d, BasicType ld_type, CodeEmitInfo *info) {
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load(as_Address(a), d, ld_type, info);
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}
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void LIR_Assembler::store(Register value, LIR_Address* dest, BasicType type, CodeEmitInfo *info) {
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store(value, as_Address(dest), type, info);
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}
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// loadf/storef with an Address
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void LIR_Assembler::load(LIR_Address* a, FloatRegister d, BasicType ld_type, CodeEmitInfo *info) {
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load(as_Address(a), d, ld_type, info);
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}
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void LIR_Assembler::store(FloatRegister value, LIR_Address* dest, BasicType type, CodeEmitInfo *info) {
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store(value, as_Address(dest), type, info);
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}
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||||
|
||||
|
||||
void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
|
||||
LIR_Const* c = src->as_constant_ptr();
|
||||
switch (c->type()) {
|
||||
case T_INT:
|
||||
case T_FLOAT:
|
||||
case T_ADDRESS: {
|
||||
case T_FLOAT: {
|
||||
Register src_reg = O7;
|
||||
int value = c->as_jint_bits();
|
||||
if (value == 0) {
|
||||
|
|
@ -1144,6 +1031,18 @@ void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
|
|||
__ stw(src_reg, addr.base(), addr.disp());
|
||||
break;
|
||||
}
|
||||
case T_ADDRESS: {
|
||||
Register src_reg = O7;
|
||||
int value = c->as_jint_bits();
|
||||
if (value == 0) {
|
||||
src_reg = G0;
|
||||
} else {
|
||||
__ set(value, O7);
|
||||
}
|
||||
Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
|
||||
__ st_ptr(src_reg, addr.base(), addr.disp());
|
||||
break;
|
||||
}
|
||||
case T_OBJECT: {
|
||||
Register src_reg = O7;
|
||||
jobject2reg(c->as_jobject(), src_reg);
|
||||
|
|
@ -1178,14 +1077,12 @@ void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
|
|||
}
|
||||
|
||||
|
||||
void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info ) {
|
||||
void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
|
||||
LIR_Const* c = src->as_constant_ptr();
|
||||
LIR_Address* addr = dest->as_address_ptr();
|
||||
Register base = addr->base()->as_pointer_register();
|
||||
int offset = -1;
|
||||
|
||||
if (info != NULL) {
|
||||
add_debug_info_for_null_check_here(info);
|
||||
}
|
||||
switch (c->type()) {
|
||||
case T_INT:
|
||||
case T_FLOAT:
|
||||
|
|
@ -1199,10 +1096,10 @@ void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmi
|
|||
}
|
||||
if (addr->index()->is_valid()) {
|
||||
assert(addr->disp() == 0, "must be zero");
|
||||
store(tmp, base, addr->index()->as_pointer_register(), type);
|
||||
offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
|
||||
} else {
|
||||
assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
|
||||
store(tmp, base, addr->disp(), type);
|
||||
offset = store(tmp, base, addr->disp(), type, wide, false);
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
|
@ -1212,21 +1109,21 @@ void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmi
|
|||
assert(Assembler::is_simm13(addr->disp()) &&
|
||||
Assembler::is_simm13(addr->disp() + 4), "can't handle larger addresses");
|
||||
|
||||
Register tmp = O7;
|
||||
LIR_Opr tmp = FrameMap::O7_opr;
|
||||
int value_lo = c->as_jint_lo_bits();
|
||||
if (value_lo == 0) {
|
||||
tmp = G0;
|
||||
tmp = FrameMap::G0_opr;
|
||||
} else {
|
||||
__ set(value_lo, O7);
|
||||
}
|
||||
store(tmp, base, addr->disp() + lo_word_offset_in_bytes, T_INT);
|
||||
offset = store(tmp, base, addr->disp() + lo_word_offset_in_bytes, T_INT, wide, false);
|
||||
int value_hi = c->as_jint_hi_bits();
|
||||
if (value_hi == 0) {
|
||||
tmp = G0;
|
||||
tmp = FrameMap::G0_opr;
|
||||
} else {
|
||||
__ set(value_hi, O7);
|
||||
}
|
||||
store(tmp, base, addr->disp() + hi_word_offset_in_bytes, T_INT);
|
||||
offset = store(tmp, base, addr->disp() + hi_word_offset_in_bytes, T_INT, wide, false);
|
||||
break;
|
||||
}
|
||||
case T_OBJECT: {
|
||||
|
|
@ -1241,10 +1138,10 @@ void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmi
|
|||
// handle either reg+reg or reg+disp address
|
||||
if (addr->index()->is_valid()) {
|
||||
assert(addr->disp() == 0, "must be zero");
|
||||
store(tmp, base, addr->index()->as_pointer_register(), type);
|
||||
offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
|
||||
} else {
|
||||
assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
|
||||
store(tmp, base, addr->disp(), type);
|
||||
offset = store(tmp, base, addr->disp(), type, wide, false);
|
||||
}
|
||||
|
||||
break;
|
||||
|
|
@ -1252,6 +1149,10 @@ void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmi
|
|||
default:
|
||||
Unimplemented();
|
||||
}
|
||||
if (info != NULL) {
|
||||
assert(offset != -1, "offset should've been set");
|
||||
add_debug_info_for_null_check(offset, info);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1336,7 +1237,7 @@ void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_cod
|
|||
assert(to_reg->is_single_cpu(), "Must be a cpu register.");
|
||||
|
||||
__ set(const_addrlit, O7);
|
||||
load(O7, 0, to_reg->as_register(), T_INT);
|
||||
__ ld(O7, 0, to_reg->as_register());
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
|
@ -1429,7 +1330,7 @@ Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
|
|||
|
||||
|
||||
void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
|
||||
LIR_PatchCode patch_code, CodeEmitInfo* info, bool unaligned) {
|
||||
LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool unaligned) {
|
||||
|
||||
LIR_Address* addr = src_opr->as_address_ptr();
|
||||
LIR_Opr to_reg = dest;
|
||||
|
|
@ -1475,16 +1376,15 @@ void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
|
|||
|
||||
assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
|
||||
if (disp_reg == noreg) {
|
||||
offset = load(src, disp_value, to_reg, type, unaligned);
|
||||
offset = load(src, disp_value, to_reg, type, wide, unaligned);
|
||||
} else {
|
||||
assert(!unaligned, "can't handle this");
|
||||
offset = load(src, disp_reg, to_reg, type);
|
||||
offset = load(src, disp_reg, to_reg, type, wide);
|
||||
}
|
||||
|
||||
if (patch != NULL) {
|
||||
patching_epilog(patch, patch_code, src, info);
|
||||
}
|
||||
|
||||
if (info != NULL) add_debug_info_for_null_check(offset, info);
|
||||
}
|
||||
|
||||
|
|
@ -1518,7 +1418,7 @@ void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
|
|||
}
|
||||
|
||||
bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
|
||||
load(addr.base(), addr.disp(), dest, dest->type(), unaligned);
|
||||
load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/, unaligned);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1530,7 +1430,7 @@ void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bo
|
|||
addr = frame_map()->address_for_slot(dest->double_stack_ix());
|
||||
}
|
||||
bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
|
||||
store(from_reg, addr.base(), addr.disp(), from_reg->type(), unaligned);
|
||||
store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/, unaligned);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1578,7 +1478,7 @@ void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
|
|||
|
||||
void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
|
||||
LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
|
||||
bool unaligned) {
|
||||
bool wide, bool unaligned) {
|
||||
LIR_Address* addr = dest->as_address_ptr();
|
||||
|
||||
Register src = addr->base()->as_pointer_register();
|
||||
|
|
@ -1622,10 +1522,10 @@ void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
|
|||
|
||||
assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
|
||||
if (disp_reg == noreg) {
|
||||
offset = store(from_reg, src, disp_value, type, unaligned);
|
||||
offset = store(from_reg, src, disp_value, type, wide, unaligned);
|
||||
} else {
|
||||
assert(!unaligned, "can't handle this");
|
||||
offset = store(from_reg, src, disp_reg, type);
|
||||
offset = store(from_reg, src, disp_reg, type, wide);
|
||||
}
|
||||
|
||||
if (patch != NULL) {
|
||||
|
|
@ -2184,13 +2084,13 @@ void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
|
|||
// make sure src and dst are non-null and load array length
|
||||
if (flags & LIR_OpArrayCopy::src_null_check) {
|
||||
__ tst(src);
|
||||
__ br(Assembler::equal, false, Assembler::pn, *stub->entry());
|
||||
__ brx(Assembler::equal, false, Assembler::pn, *stub->entry());
|
||||
__ delayed()->nop();
|
||||
}
|
||||
|
||||
if (flags & LIR_OpArrayCopy::dst_null_check) {
|
||||
__ tst(dst);
|
||||
__ br(Assembler::equal, false, Assembler::pn, *stub->entry());
|
||||
__ brx(Assembler::equal, false, Assembler::pn, *stub->entry());
|
||||
__ delayed()->nop();
|
||||
}
|
||||
|
||||
|
|
@ -2232,10 +2132,18 @@ void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
|
|||
}
|
||||
|
||||
if (flags & LIR_OpArrayCopy::type_check) {
|
||||
__ ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp);
|
||||
__ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
|
||||
__ cmp(tmp, tmp2);
|
||||
__ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
|
||||
if (UseCompressedOops) {
|
||||
// We don't need decode because we just need to compare
|
||||
__ lduw(src, oopDesc::klass_offset_in_bytes(), tmp);
|
||||
__ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2);
|
||||
__ cmp(tmp, tmp2);
|
||||
__ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
|
||||
} else {
|
||||
__ ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp);
|
||||
__ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
|
||||
__ cmp(tmp, tmp2);
|
||||
__ brx(Assembler::notEqual, false, Assembler::pt, *stub->entry());
|
||||
}
|
||||
__ delayed()->nop();
|
||||
}
|
||||
|
||||
|
|
@ -2250,20 +2158,44 @@ void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
|
|||
// but not necessarily exactly of type default_type.
|
||||
Label known_ok, halt;
|
||||
jobject2reg(op->expected_type()->constant_encoding(), tmp);
|
||||
__ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
|
||||
if (basic_type != T_OBJECT) {
|
||||
__ cmp(tmp, tmp2);
|
||||
__ br(Assembler::notEqual, false, Assembler::pn, halt);
|
||||
__ delayed()->ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp2);
|
||||
__ cmp(tmp, tmp2);
|
||||
__ br(Assembler::equal, false, Assembler::pn, known_ok);
|
||||
__ delayed()->nop();
|
||||
if (UseCompressedOops) {
|
||||
// tmp holds the default type. It currently comes uncompressed after the
|
||||
// load of a constant, so encode it.
|
||||
__ encode_heap_oop(tmp);
|
||||
// load the raw value of the dst klass, since we will be comparing
|
||||
// uncompressed values directly.
|
||||
__ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2);
|
||||
if (basic_type != T_OBJECT) {
|
||||
__ cmp(tmp, tmp2);
|
||||
__ br(Assembler::notEqual, false, Assembler::pn, halt);
|
||||
// load the raw value of the src klass.
|
||||
__ delayed()->lduw(src, oopDesc::klass_offset_in_bytes(), tmp2);
|
||||
__ cmp(tmp, tmp2);
|
||||
__ br(Assembler::equal, false, Assembler::pn, known_ok);
|
||||
__ delayed()->nop();
|
||||
} else {
|
||||
__ cmp(tmp, tmp2);
|
||||
__ br(Assembler::equal, false, Assembler::pn, known_ok);
|
||||
__ delayed()->cmp(src, dst);
|
||||
__ brx(Assembler::equal, false, Assembler::pn, known_ok);
|
||||
__ delayed()->nop();
|
||||
}
|
||||
} else {
|
||||
__ cmp(tmp, tmp2);
|
||||
__ br(Assembler::equal, false, Assembler::pn, known_ok);
|
||||
__ delayed()->cmp(src, dst);
|
||||
__ br(Assembler::equal, false, Assembler::pn, known_ok);
|
||||
__ delayed()->nop();
|
||||
__ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
|
||||
if (basic_type != T_OBJECT) {
|
||||
__ cmp(tmp, tmp2);
|
||||
__ brx(Assembler::notEqual, false, Assembler::pn, halt);
|
||||
__ delayed()->ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp2);
|
||||
__ cmp(tmp, tmp2);
|
||||
__ brx(Assembler::equal, false, Assembler::pn, known_ok);
|
||||
__ delayed()->nop();
|
||||
} else {
|
||||
__ cmp(tmp, tmp2);
|
||||
__ brx(Assembler::equal, false, Assembler::pn, known_ok);
|
||||
__ delayed()->cmp(src, dst);
|
||||
__ brx(Assembler::equal, false, Assembler::pn, known_ok);
|
||||
__ delayed()->nop();
|
||||
}
|
||||
}
|
||||
__ bind(halt);
|
||||
__ stop("incorrect type information in arraycopy");
|
||||
|
|
@ -2471,7 +2403,7 @@ void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
|
|||
Label next_test;
|
||||
Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
|
||||
mdo_offset_bias);
|
||||
load(recv_addr, tmp1, T_OBJECT);
|
||||
__ ld_ptr(recv_addr, tmp1);
|
||||
__ br_notnull(tmp1, false, Assembler::pt, next_test);
|
||||
__ delayed()->nop();
|
||||
__ st_ptr(recv, recv_addr);
|
||||
|
|
@ -2563,7 +2495,7 @@ void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, L
|
|||
|
||||
// get object class
|
||||
// not a safepoint as obj null check happens earlier
|
||||
load(obj, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL);
|
||||
__ load_klass(obj, klass_RInfo);
|
||||
if (op->fast_check()) {
|
||||
assert_different_registers(klass_RInfo, k_RInfo);
|
||||
__ cmp(k_RInfo, klass_RInfo);
|
||||
|
|
@ -2605,7 +2537,7 @@ void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, L
|
|||
__ set(mdo_offset_bias, tmp1);
|
||||
__ add(mdo, tmp1, mdo);
|
||||
}
|
||||
load(Address(obj, oopDesc::klass_offset_in_bytes()), recv, T_OBJECT);
|
||||
__ load_klass(obj, recv);
|
||||
type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, success);
|
||||
// Jump over the failure case
|
||||
__ ba(false, *success);
|
||||
|
|
@ -2674,11 +2606,12 @@ void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
|
|||
__ br_null(value, false, Assembler::pn, done);
|
||||
__ delayed()->nop();
|
||||
}
|
||||
load(array, oopDesc::klass_offset_in_bytes(), k_RInfo, T_OBJECT, op->info_for_exception());
|
||||
load(value, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL);
|
||||
add_debug_info_for_null_check_here(op->info_for_exception());
|
||||
__ load_klass(array, k_RInfo);
|
||||
__ load_klass(value, klass_RInfo);
|
||||
|
||||
// get instance klass
|
||||
load(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc), k_RInfo, T_OBJECT, NULL);
|
||||
__ ld_ptr(Address(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc)), k_RInfo);
|
||||
// perform the fast part of the checking logic
|
||||
__ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target, failure_target, NULL);
|
||||
|
||||
|
|
@ -2700,7 +2633,7 @@ void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
|
|||
__ set(mdo_offset_bias, tmp1);
|
||||
__ add(mdo, tmp1, mdo);
|
||||
}
|
||||
load(Address(value, oopDesc::klass_offset_in_bytes()), recv, T_OBJECT);
|
||||
__ load_klass(value, recv);
|
||||
type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &done);
|
||||
__ ba(false, done);
|
||||
__ delayed()->nop();
|
||||
|
|
@ -2781,14 +2714,17 @@ void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
|
|||
Register t2 = op->tmp2()->as_register();
|
||||
__ mov(cmp_value, t1);
|
||||
__ mov(new_value, t2);
|
||||
#ifdef _LP64
|
||||
if (op->code() == lir_cas_obj) {
|
||||
__ casx(addr, t1, t2);
|
||||
} else
|
||||
#endif
|
||||
{
|
||||
if (UseCompressedOops) {
|
||||
__ encode_heap_oop(t1);
|
||||
__ encode_heap_oop(t2);
|
||||
__ cas(addr, t1, t2);
|
||||
} else {
|
||||
__ casx(addr, t1, t2);
|
||||
}
|
||||
} else {
|
||||
__ cas(addr, t1, t2);
|
||||
}
|
||||
__ cmp(t1, t2);
|
||||
} else {
|
||||
Unimplemented();
|
||||
|
|
@ -2966,7 +2902,7 @@ void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
|
|||
}
|
||||
}
|
||||
} else {
|
||||
load(Address(recv, oopDesc::klass_offset_in_bytes()), recv, T_OBJECT);
|
||||
__ load_klass(recv, recv);
|
||||
Label update_done;
|
||||
type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
|
||||
// Receiver did not match any saved receiver and there is no empty row for it.
|
||||
|
|
@ -3160,7 +3096,7 @@ void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type,
|
|||
} else {
|
||||
// use normal move for all other volatiles since they don't need
|
||||
// special handling to remain atomic.
|
||||
move_op(src, dest, type, lir_patch_none, info, false, false);
|
||||
move_op(src, dest, type, lir_patch_none, info, false, false, false);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue