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8132160: support for AVX 512 call frames and stack management
Simplify save/restore frame on x86 systems which support EVEX. Reviewed-by: kvn, iveresov
This commit is contained in:
Michael Berg
parent
9f9739c156
commit
d67924dc8e
17 changed files with 1578 additions and 1257 deletions
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@ -69,7 +69,9 @@ class SimpleRuntimeFrame {
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class RegisterSaver {
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// Capture info about frame layout. Layout offsets are in jint
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// units because compiler frame slots are jints.
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#define HALF_ZMM_BANK_WORDS 128
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#define DEF_XMM_OFFS(regnum) xmm ## regnum ## _off = xmm_off + (regnum)*16/BytesPerInt, xmm ## regnum ## H_off
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#define DEF_ZMM_OFFS(regnum) zmm ## regnum ## _off = zmm_off + (regnum-16)*64/BytesPerInt, zmm ## regnum ## H_off
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enum layout {
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fpu_state_off = frame::arg_reg_save_area_bytes/BytesPerInt, // fxsave save area
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xmm_off = fpu_state_off + 160/BytesPerInt, // offset in fxsave save area
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@ -89,23 +91,24 @@ class RegisterSaver {
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DEF_XMM_OFFS(13),
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DEF_XMM_OFFS(14),
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DEF_XMM_OFFS(15),
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DEF_XMM_OFFS(16),
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DEF_XMM_OFFS(17),
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DEF_XMM_OFFS(18),
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DEF_XMM_OFFS(19),
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DEF_XMM_OFFS(20),
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DEF_XMM_OFFS(21),
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DEF_XMM_OFFS(22),
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DEF_XMM_OFFS(23),
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DEF_XMM_OFFS(24),
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DEF_XMM_OFFS(25),
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DEF_XMM_OFFS(26),
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DEF_XMM_OFFS(27),
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DEF_XMM_OFFS(28),
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DEF_XMM_OFFS(29),
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DEF_XMM_OFFS(30),
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DEF_XMM_OFFS(31),
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fpu_state_end = fpu_state_off + ((FPUStateSizeInWords - 1)*wordSize / BytesPerInt),
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zmm_off = fpu_state_off + ((FPUStateSizeInWords - (HALF_ZMM_BANK_WORDS + 1))*wordSize / BytesPerInt),
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DEF_ZMM_OFFS(16),
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DEF_ZMM_OFFS(17),
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DEF_ZMM_OFFS(18),
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DEF_ZMM_OFFS(19),
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DEF_ZMM_OFFS(20),
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DEF_ZMM_OFFS(21),
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DEF_ZMM_OFFS(22),
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DEF_ZMM_OFFS(23),
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DEF_ZMM_OFFS(24),
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DEF_ZMM_OFFS(25),
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DEF_ZMM_OFFS(26),
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DEF_ZMM_OFFS(27),
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DEF_ZMM_OFFS(28),
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DEF_ZMM_OFFS(29),
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DEF_ZMM_OFFS(30),
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DEF_ZMM_OFFS(31),
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fpu_state_end = fpu_state_off + ((FPUStateSizeInWords-1)*wordSize / BytesPerInt),
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fpu_stateH_end,
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r15_off, r15H_off,
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r14_off, r14H_off,
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@ -155,9 +158,10 @@ class RegisterSaver {
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OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words, bool save_vectors) {
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int vect_words = 0;
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int num_xmm_regs = 16;
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if (UseAVX > 2) {
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num_xmm_regs = 32;
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int off = 0;
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int num_xmm_regs = XMMRegisterImpl::number_of_registers;
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if (UseAVX < 3) {
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num_xmm_regs = num_xmm_regs/2;
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}
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#ifdef COMPILER2
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if (save_vectors) {
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@ -165,9 +169,7 @@ OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_
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assert(MaxVectorSize == 64, "only 512bit vectors are supported now");
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// Save upper half of YMM registers
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vect_words = 16 * num_xmm_regs / wordSize;
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additional_frame_words += vect_words;
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if (UseAVX > 2) {
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// Save upper half of ZMM registers as well
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if (UseAVX < 3) {
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additional_frame_words += vect_words;
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}
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}
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@ -195,77 +197,13 @@ OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_
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__ enter(); // rsp becomes 16-byte aligned here
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__ push_CPU_state(); // Push a multiple of 16 bytes
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if (vect_words > 0) {
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// push cpu state handles this on EVEX enabled targets
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if ((vect_words > 0) && (UseAVX < 3)) {
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assert(vect_words*wordSize >= 256, "");
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__ subptr(rsp, 256); // Save upper half of YMM registes(0..15)
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__ vextractf128h(Address(rsp, 0), xmm0);
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__ vextractf128h(Address(rsp, 16), xmm1);
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__ vextractf128h(Address(rsp, 32), xmm2);
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__ vextractf128h(Address(rsp, 48), xmm3);
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__ vextractf128h(Address(rsp, 64), xmm4);
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__ vextractf128h(Address(rsp, 80), xmm5);
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__ vextractf128h(Address(rsp, 96), xmm6);
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__ vextractf128h(Address(rsp, 112), xmm7);
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__ vextractf128h(Address(rsp, 128), xmm8);
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__ vextractf128h(Address(rsp, 144), xmm9);
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__ vextractf128h(Address(rsp, 160), xmm10);
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__ vextractf128h(Address(rsp, 176), xmm11);
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__ vextractf128h(Address(rsp, 192), xmm12);
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__ vextractf128h(Address(rsp, 208), xmm13);
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__ vextractf128h(Address(rsp, 224), xmm14);
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__ vextractf128h(Address(rsp, 240), xmm15);
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if (UseAVX > 2) {
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__ subptr(rsp, 256); // Save upper half of YMM registes(16..31)
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__ vextractf128h(Address(rsp, 0), xmm16);
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__ vextractf128h(Address(rsp, 16), xmm17);
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__ vextractf128h(Address(rsp, 32), xmm18);
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__ vextractf128h(Address(rsp, 48), xmm19);
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__ vextractf128h(Address(rsp, 64), xmm20);
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__ vextractf128h(Address(rsp, 80), xmm21);
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__ vextractf128h(Address(rsp, 96), xmm22);
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__ vextractf128h(Address(rsp, 112), xmm23);
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__ vextractf128h(Address(rsp, 128), xmm24);
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__ vextractf128h(Address(rsp, 144), xmm25);
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__ vextractf128h(Address(rsp, 160), xmm26);
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__ vextractf128h(Address(rsp, 176), xmm27);
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__ vextractf128h(Address(rsp, 192), xmm28);
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__ vextractf128h(Address(rsp, 208), xmm29);
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__ vextractf128h(Address(rsp, 224), xmm30);
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__ vextractf128h(Address(rsp, 240), xmm31);
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// Now handle the ZMM registers (0..31)
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__ subptr(rsp, 1024); // Save upper half of ZMM registes
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__ vextractf64x4h(Address(rsp, 0), xmm0);
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__ vextractf64x4h(Address(rsp, 32), xmm1);
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__ vextractf64x4h(Address(rsp, 64), xmm2);
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__ vextractf64x4h(Address(rsp, 96), xmm3);
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__ vextractf64x4h(Address(rsp, 128), xmm4);
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__ vextractf64x4h(Address(rsp, 160), xmm5);
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__ vextractf64x4h(Address(rsp, 192), xmm6);
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__ vextractf64x4h(Address(rsp, 224), xmm7);
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__ vextractf64x4h(Address(rsp, 256), xmm8);
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__ vextractf64x4h(Address(rsp, 288), xmm9);
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__ vextractf64x4h(Address(rsp, 320), xmm10);
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__ vextractf64x4h(Address(rsp, 352), xmm11);
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__ vextractf64x4h(Address(rsp, 384), xmm12);
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__ vextractf64x4h(Address(rsp, 416), xmm13);
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__ vextractf64x4h(Address(rsp, 448), xmm14);
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__ vextractf64x4h(Address(rsp, 480), xmm15);
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__ vextractf64x4h(Address(rsp, 512), xmm16);
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__ vextractf64x4h(Address(rsp, 544), xmm17);
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__ vextractf64x4h(Address(rsp, 576), xmm18);
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__ vextractf64x4h(Address(rsp, 608), xmm19);
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__ vextractf64x4h(Address(rsp, 640), xmm20);
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__ vextractf64x4h(Address(rsp, 672), xmm21);
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__ vextractf64x4h(Address(rsp, 704), xmm22);
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__ vextractf64x4h(Address(rsp, 736), xmm23);
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__ vextractf64x4h(Address(rsp, 768), xmm24);
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__ vextractf64x4h(Address(rsp, 800), xmm25);
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__ vextractf64x4h(Address(rsp, 832), xmm26);
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__ vextractf64x4h(Address(rsp, 864), xmm27);
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__ vextractf64x4h(Address(rsp, 896), xmm28);
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__ vextractf64x4h(Address(rsp, 928), xmm29);
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__ vextractf64x4h(Address(rsp, 960), xmm30);
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__ vextractf64x4h(Address(rsp, 992), xmm31);
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// Save upper half of YMM registes(0..num_xmm_regs)
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__ subptr(rsp, num_xmm_regs*16);
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for (int n = 0; n < num_xmm_regs; n++) {
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__ vextractf128h(Address(rsp, off++*16), as_XMMRegister(n));
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}
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}
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if (frame::arg_reg_save_area_bytes != 0) {
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@ -299,39 +237,24 @@ OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_
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map->set_callee_saved(STACK_OFFSET( r13_off ), r13->as_VMReg());
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map->set_callee_saved(STACK_OFFSET( r14_off ), r14->as_VMReg());
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map->set_callee_saved(STACK_OFFSET( r15_off ), r15->as_VMReg());
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map->set_callee_saved(STACK_OFFSET(xmm0_off ), xmm0->as_VMReg());
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map->set_callee_saved(STACK_OFFSET(xmm1_off ), xmm1->as_VMReg());
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map->set_callee_saved(STACK_OFFSET(xmm2_off ), xmm2->as_VMReg());
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map->set_callee_saved(STACK_OFFSET(xmm3_off ), xmm3->as_VMReg());
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map->set_callee_saved(STACK_OFFSET(xmm4_off ), xmm4->as_VMReg());
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map->set_callee_saved(STACK_OFFSET(xmm5_off ), xmm5->as_VMReg());
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map->set_callee_saved(STACK_OFFSET(xmm6_off ), xmm6->as_VMReg());
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map->set_callee_saved(STACK_OFFSET(xmm7_off ), xmm7->as_VMReg());
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map->set_callee_saved(STACK_OFFSET(xmm8_off ), xmm8->as_VMReg());
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map->set_callee_saved(STACK_OFFSET(xmm9_off ), xmm9->as_VMReg());
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map->set_callee_saved(STACK_OFFSET(xmm10_off), xmm10->as_VMReg());
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map->set_callee_saved(STACK_OFFSET(xmm11_off), xmm11->as_VMReg());
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map->set_callee_saved(STACK_OFFSET(xmm12_off), xmm12->as_VMReg());
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map->set_callee_saved(STACK_OFFSET(xmm13_off), xmm13->as_VMReg());
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map->set_callee_saved(STACK_OFFSET(xmm14_off), xmm14->as_VMReg());
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map->set_callee_saved(STACK_OFFSET(xmm15_off), xmm15->as_VMReg());
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if (UseAVX > 2) {
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map->set_callee_saved(STACK_OFFSET(xmm16_off), xmm16->as_VMReg());
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map->set_callee_saved(STACK_OFFSET(xmm17_off), xmm17->as_VMReg());
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map->set_callee_saved(STACK_OFFSET(xmm18_off), xmm18->as_VMReg());
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map->set_callee_saved(STACK_OFFSET(xmm19_off), xmm19->as_VMReg());
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map->set_callee_saved(STACK_OFFSET(xmm20_off), xmm20->as_VMReg());
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map->set_callee_saved(STACK_OFFSET(xmm21_off), xmm21->as_VMReg());
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map->set_callee_saved(STACK_OFFSET(xmm22_off), xmm22->as_VMReg());
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map->set_callee_saved(STACK_OFFSET(xmm23_off), xmm23->as_VMReg());
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map->set_callee_saved(STACK_OFFSET(xmm24_off), xmm24->as_VMReg());
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map->set_callee_saved(STACK_OFFSET(xmm25_off), xmm25->as_VMReg());
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map->set_callee_saved(STACK_OFFSET(xmm26_off), xmm26->as_VMReg());
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map->set_callee_saved(STACK_OFFSET(xmm27_off), xmm27->as_VMReg());
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map->set_callee_saved(STACK_OFFSET(xmm28_off), xmm28->as_VMReg());
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map->set_callee_saved(STACK_OFFSET(xmm29_off), xmm29->as_VMReg());
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map->set_callee_saved(STACK_OFFSET(xmm30_off), xmm30->as_VMReg());
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map->set_callee_saved(STACK_OFFSET(xmm31_off), xmm31->as_VMReg());
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// For both AVX and EVEX we will use the legacy FXSAVE area for xmm0..xmm15,
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// on EVEX enabled targets, we get it included in the xsave area
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off = xmm0_off;
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int delta = xmm1_off - off;
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for (int n = 0; n < 16; n++) {
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XMMRegister xmm_name = as_XMMRegister(n);
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map->set_callee_saved(STACK_OFFSET(off), xmm_name->as_VMReg());
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off += delta;
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}
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if(UseAVX > 2) {
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// Obtain xmm16..xmm31 from the XSAVE area on EVEX enabled targets
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off = zmm16_off;
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delta = zmm17_off - off;
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for (int n = 16; n < num_xmm_regs; n++) {
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XMMRegister xmm_name = as_XMMRegister(n);
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map->set_callee_saved(STACK_OFFSET(off), xmm_name->as_VMReg());
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off += delta;
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}
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}
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// %%% These should all be a waste but we'll keep things as they were for now
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@ -351,39 +274,24 @@ OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_
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map->set_callee_saved(STACK_OFFSET( r13H_off ), r13->as_VMReg()->next());
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map->set_callee_saved(STACK_OFFSET( r14H_off ), r14->as_VMReg()->next());
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map->set_callee_saved(STACK_OFFSET( r15H_off ), r15->as_VMReg()->next());
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map->set_callee_saved(STACK_OFFSET(xmm0H_off ), xmm0->as_VMReg()->next());
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map->set_callee_saved(STACK_OFFSET(xmm1H_off ), xmm1->as_VMReg()->next());
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map->set_callee_saved(STACK_OFFSET(xmm2H_off ), xmm2->as_VMReg()->next());
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map->set_callee_saved(STACK_OFFSET(xmm3H_off ), xmm3->as_VMReg()->next());
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map->set_callee_saved(STACK_OFFSET(xmm4H_off ), xmm4->as_VMReg()->next());
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map->set_callee_saved(STACK_OFFSET(xmm5H_off ), xmm5->as_VMReg()->next());
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map->set_callee_saved(STACK_OFFSET(xmm6H_off ), xmm6->as_VMReg()->next());
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map->set_callee_saved(STACK_OFFSET(xmm7H_off ), xmm7->as_VMReg()->next());
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map->set_callee_saved(STACK_OFFSET(xmm8H_off ), xmm8->as_VMReg()->next());
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map->set_callee_saved(STACK_OFFSET(xmm9H_off ), xmm9->as_VMReg()->next());
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map->set_callee_saved(STACK_OFFSET(xmm10H_off), xmm10->as_VMReg()->next());
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map->set_callee_saved(STACK_OFFSET(xmm11H_off), xmm11->as_VMReg()->next());
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map->set_callee_saved(STACK_OFFSET(xmm12H_off), xmm12->as_VMReg()->next());
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map->set_callee_saved(STACK_OFFSET(xmm13H_off), xmm13->as_VMReg()->next());
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map->set_callee_saved(STACK_OFFSET(xmm14H_off), xmm14->as_VMReg()->next());
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map->set_callee_saved(STACK_OFFSET(xmm15H_off), xmm15->as_VMReg()->next());
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// For both AVX and EVEX we will use the legacy FXSAVE area for xmm0..xmm15,
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// on EVEX enabled targets, we get it included in the xsave area
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off = xmm0H_off;
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delta = xmm1H_off - off;
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for (int n = 0; n < 16; n++) {
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XMMRegister xmm_name = as_XMMRegister(n);
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map->set_callee_saved(STACK_OFFSET(off), xmm_name->as_VMReg()->next());
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off += delta;
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}
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if (UseAVX > 2) {
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map->set_callee_saved(STACK_OFFSET(xmm16H_off), xmm16->as_VMReg()->next());
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map->set_callee_saved(STACK_OFFSET(xmm17H_off), xmm17->as_VMReg()->next());
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map->set_callee_saved(STACK_OFFSET(xmm18H_off), xmm18->as_VMReg()->next());
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map->set_callee_saved(STACK_OFFSET(xmm19H_off), xmm19->as_VMReg()->next());
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map->set_callee_saved(STACK_OFFSET(xmm20H_off), xmm20->as_VMReg()->next());
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map->set_callee_saved(STACK_OFFSET(xmm21H_off), xmm21->as_VMReg()->next());
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map->set_callee_saved(STACK_OFFSET(xmm22H_off), xmm22->as_VMReg()->next());
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map->set_callee_saved(STACK_OFFSET(xmm23H_off), xmm23->as_VMReg()->next());
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map->set_callee_saved(STACK_OFFSET(xmm24H_off), xmm24->as_VMReg()->next());
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map->set_callee_saved(STACK_OFFSET(xmm25H_off), xmm25->as_VMReg()->next());
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map->set_callee_saved(STACK_OFFSET(xmm26H_off), xmm26->as_VMReg()->next());
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map->set_callee_saved(STACK_OFFSET(xmm27H_off), xmm27->as_VMReg()->next());
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map->set_callee_saved(STACK_OFFSET(xmm28H_off), xmm28->as_VMReg()->next());
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map->set_callee_saved(STACK_OFFSET(xmm29H_off), xmm29->as_VMReg()->next());
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map->set_callee_saved(STACK_OFFSET(xmm30H_off), xmm30->as_VMReg()->next());
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map->set_callee_saved(STACK_OFFSET(xmm31H_off), xmm31->as_VMReg()->next());
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// Obtain xmm16..xmm31 from the XSAVE area on EVEX enabled targets
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off = zmm16H_off;
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delta = zmm17H_off - off;
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for (int n = 16; n < num_xmm_regs; n++) {
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XMMRegister xmm_name = as_XMMRegister(n);
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map->set_callee_saved(STACK_OFFSET(off), xmm_name->as_VMReg()->next());
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off += delta;
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}
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}
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}
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@ -391,86 +299,25 @@ OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_
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}
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void RegisterSaver::restore_live_registers(MacroAssembler* masm, bool restore_vectors) {
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int num_xmm_regs = XMMRegisterImpl::number_of_registers;
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if (UseAVX < 3) {
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num_xmm_regs = num_xmm_regs/2;
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}
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if (frame::arg_reg_save_area_bytes != 0) {
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// Pop arg register save area
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__ addptr(rsp, frame::arg_reg_save_area_bytes);
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}
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#ifdef COMPILER2
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if (restore_vectors) {
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// Restore upper half of YMM registes (0..15)
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assert(UseAVX > 0, "512bit vectors are supported only with AVX");
|
||||
assert(MaxVectorSize == 64, "only 512bit vectors are supported now");
|
||||
__ vinsertf128h(xmm0, Address(rsp, 0));
|
||||
__ vinsertf128h(xmm1, Address(rsp, 16));
|
||||
__ vinsertf128h(xmm2, Address(rsp, 32));
|
||||
__ vinsertf128h(xmm3, Address(rsp, 48));
|
||||
__ vinsertf128h(xmm4, Address(rsp, 64));
|
||||
__ vinsertf128h(xmm5, Address(rsp, 80));
|
||||
__ vinsertf128h(xmm6, Address(rsp, 96));
|
||||
__ vinsertf128h(xmm7, Address(rsp,112));
|
||||
__ vinsertf128h(xmm8, Address(rsp,128));
|
||||
__ vinsertf128h(xmm9, Address(rsp,144));
|
||||
__ vinsertf128h(xmm10, Address(rsp,160));
|
||||
__ vinsertf128h(xmm11, Address(rsp,176));
|
||||
__ vinsertf128h(xmm12, Address(rsp,192));
|
||||
__ vinsertf128h(xmm13, Address(rsp,208));
|
||||
__ vinsertf128h(xmm14, Address(rsp,224));
|
||||
__ vinsertf128h(xmm15, Address(rsp,240));
|
||||
__ addptr(rsp, 256);
|
||||
if (UseAVX > 2) {
|
||||
// Restore upper half of YMM registes (16..31)
|
||||
__ vinsertf128h(xmm16, Address(rsp, 0));
|
||||
__ vinsertf128h(xmm17, Address(rsp, 16));
|
||||
__ vinsertf128h(xmm18, Address(rsp, 32));
|
||||
__ vinsertf128h(xmm19, Address(rsp, 48));
|
||||
__ vinsertf128h(xmm20, Address(rsp, 64));
|
||||
__ vinsertf128h(xmm21, Address(rsp, 80));
|
||||
__ vinsertf128h(xmm22, Address(rsp, 96));
|
||||
__ vinsertf128h(xmm23, Address(rsp,112));
|
||||
__ vinsertf128h(xmm24, Address(rsp,128));
|
||||
__ vinsertf128h(xmm25, Address(rsp,144));
|
||||
__ vinsertf128h(xmm26, Address(rsp,160));
|
||||
__ vinsertf128h(xmm27, Address(rsp,176));
|
||||
__ vinsertf128h(xmm28, Address(rsp,192));
|
||||
__ vinsertf128h(xmm29, Address(rsp,208));
|
||||
__ vinsertf128h(xmm30, Address(rsp,224));
|
||||
__ vinsertf128h(xmm31, Address(rsp,240));
|
||||
__ addptr(rsp, 256);
|
||||
// Restore upper half of ZMM registes.
|
||||
__ vinsertf64x4h(xmm0, Address(rsp, 0));
|
||||
__ vinsertf64x4h(xmm1, Address(rsp, 32));
|
||||
__ vinsertf64x4h(xmm2, Address(rsp, 64));
|
||||
__ vinsertf64x4h(xmm3, Address(rsp, 96));
|
||||
__ vinsertf64x4h(xmm4, Address(rsp, 128));
|
||||
__ vinsertf64x4h(xmm5, Address(rsp, 160));
|
||||
__ vinsertf64x4h(xmm6, Address(rsp, 192));
|
||||
__ vinsertf64x4h(xmm7, Address(rsp, 224));
|
||||
__ vinsertf64x4h(xmm8, Address(rsp, 256));
|
||||
__ vinsertf64x4h(xmm9, Address(rsp, 288));
|
||||
__ vinsertf64x4h(xmm10, Address(rsp, 320));
|
||||
__ vinsertf64x4h(xmm11, Address(rsp, 352));
|
||||
__ vinsertf64x4h(xmm12, Address(rsp, 384));
|
||||
__ vinsertf64x4h(xmm13, Address(rsp, 416));
|
||||
__ vinsertf64x4h(xmm14, Address(rsp, 448));
|
||||
__ vinsertf64x4h(xmm15, Address(rsp, 480));
|
||||
__ vinsertf64x4h(xmm16, Address(rsp, 512));
|
||||
__ vinsertf64x4h(xmm17, Address(rsp, 544));
|
||||
__ vinsertf64x4h(xmm18, Address(rsp, 576));
|
||||
__ vinsertf64x4h(xmm19, Address(rsp, 608));
|
||||
__ vinsertf64x4h(xmm20, Address(rsp, 640));
|
||||
__ vinsertf64x4h(xmm21, Address(rsp, 672));
|
||||
__ vinsertf64x4h(xmm22, Address(rsp, 704));
|
||||
__ vinsertf64x4h(xmm23, Address(rsp, 736));
|
||||
__ vinsertf64x4h(xmm24, Address(rsp, 768));
|
||||
__ vinsertf64x4h(xmm25, Address(rsp, 800));
|
||||
__ vinsertf64x4h(xmm26, Address(rsp, 832));
|
||||
__ vinsertf64x4h(xmm27, Address(rsp, 864));
|
||||
__ vinsertf64x4h(xmm28, Address(rsp, 896));
|
||||
__ vinsertf64x4h(xmm29, Address(rsp, 928));
|
||||
__ vinsertf64x4h(xmm30, Address(rsp, 960));
|
||||
__ vinsertf64x4h(xmm31, Address(rsp, 992));
|
||||
__ addptr(rsp, 1024);
|
||||
// On EVEX enabled targets everything is handled in pop fpu state
|
||||
if ((restore_vectors) && (UseAVX < 3)) {
|
||||
assert(UseAVX > 0, "256/512-bit vectors are supported only with AVX");
|
||||
assert(MaxVectorSize == 64, "up to 512bit vectors are supported now");
|
||||
int off = 0;
|
||||
// Restore upper half of YMM registes (0..num_xmm_regs)
|
||||
for (int n = 0; n < num_xmm_regs; n++) {
|
||||
__ vinsertf128h(as_XMMRegister(n), Address(rsp, off++*16));
|
||||
}
|
||||
__ addptr(rsp, num_xmm_regs*16);
|
||||
}
|
||||
#else
|
||||
assert(!restore_vectors, "vectors are generated only by C2");
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue