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8214451: PPC64/s390: Clean up unused CRC32 prototype and function
Reviewed-by: mdoerr, lucy
This commit is contained in:
Gustavo Romero
parent
d92085431b
commit
d6b70fa2ab
5 changed files with 0 additions and 176 deletions
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@ -4013,105 +4013,6 @@ void MacroAssembler::update_1word_crc32(Register crc, Register buf, Register tab
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xorr(crc, t0, t2); // Now crc contains the final checksum value.
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xorr(crc, t0, t2); // Now crc contains the final checksum value.
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}
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}
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/**
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* @param crc register containing existing CRC (32-bit)
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* @param buf register pointing to input byte buffer (byte*)
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* @param len register containing number of bytes
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* @param table register pointing to CRC table
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*
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* Uses R9..R12 as work register. Must be saved/restored by caller!
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*/
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void MacroAssembler::kernel_crc32_2word(Register crc, Register buf, Register len, Register table,
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Register t0, Register t1, Register t2, Register t3,
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Register tc0, Register tc1, Register tc2, Register tc3,
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bool invertCRC) {
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assert_different_registers(crc, buf, len, table);
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Label L_mainLoop, L_tail;
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Register tmp = t0;
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Register data = t0;
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Register tmp2 = t1;
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const int mainLoop_stepping = 8;
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const int tailLoop_stepping = 1;
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const int log_stepping = exact_log2(mainLoop_stepping);
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const int mainLoop_alignment = 32; // InputForNewCode > 4 ? InputForNewCode : 32;
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const int complexThreshold = 2*mainLoop_stepping;
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// Don't test for len <= 0 here. This pathological case should not occur anyway.
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// Optimizing for it by adding a test and a branch seems to be a waste of CPU cycles
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// for all well-behaved cases. The situation itself is detected and handled correctly
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// within update_byteLoop_crc32.
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assert(tailLoop_stepping == 1, "check tailLoop_stepping!");
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BLOCK_COMMENT("kernel_crc32_2word {");
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if (invertCRC) {
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nand(crc, crc, crc); // 1s complement of crc
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}
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// Check for short (<mainLoop_stepping) buffer.
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cmpdi(CCR0, len, complexThreshold);
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blt(CCR0, L_tail);
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// Pre-mainLoop alignment did show a slight (1%) positive effect on performance.
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// We leave the code in for reference. Maybe we need alignment when we exploit vector instructions.
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{
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// Align buf addr to mainLoop_stepping boundary.
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neg(tmp2, buf); // Calculate # preLoop iterations for alignment.
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rldicl(tmp2, tmp2, 0, 64-log_stepping); // Rotate tmp2 0 bits, insert into tmp2, anding with mask with 1s from 62..63.
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if (complexThreshold > mainLoop_stepping) {
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sub(len, len, tmp2); // Remaining bytes for main loop (>=mainLoop_stepping is guaranteed).
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} else {
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sub(tmp, len, tmp2); // Remaining bytes for main loop.
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cmpdi(CCR0, tmp, mainLoop_stepping);
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blt(CCR0, L_tail); // For less than one mainloop_stepping left, do only tail processing
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mr(len, tmp); // remaining bytes for main loop (>=mainLoop_stepping is guaranteed).
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}
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update_byteLoop_crc32(crc, buf, tmp2, table, data, false);
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}
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srdi(tmp2, len, log_stepping); // #iterations for mainLoop
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andi(len, len, mainLoop_stepping-1); // remaining bytes for tailLoop
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mtctr(tmp2);
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#ifdef VM_LITTLE_ENDIAN
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Register crc_rv = crc;
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#else
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Register crc_rv = tmp; // Load_reverse needs separate registers to work on.
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// Occupies tmp, but frees up crc.
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load_reverse_32(crc_rv, crc); // Revert byte order because we are dealing with big-endian data.
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tmp = crc;
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#endif
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int reconstructTableOffset = crc32_table_columns(table, tc0, tc1, tc2, tc3);
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align(mainLoop_alignment); // Octoword-aligned loop address. Shows 2% improvement.
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BIND(L_mainLoop);
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update_1word_crc32(crc_rv, buf, table, 0, 0, crc_rv, t1, t2, t3, tc0, tc1, tc2, tc3);
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update_1word_crc32(crc_rv, buf, table, 4, mainLoop_stepping, crc_rv, t1, t2, t3, tc0, tc1, tc2, tc3);
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bdnz(L_mainLoop);
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#ifndef VM_LITTLE_ENDIAN
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load_reverse_32(crc, crc_rv); // Revert byte order because we are dealing with big-endian data.
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tmp = crc_rv; // Tmp uses it's original register again.
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#endif
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// Restore original table address for tailLoop.
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if (reconstructTableOffset != 0) {
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addi(table, table, -reconstructTableOffset);
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}
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// Process last few (<complexThreshold) bytes of buffer.
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BIND(L_tail);
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update_byteLoop_crc32(crc, buf, len, table, data, false);
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if (invertCRC) {
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nand(crc, crc, crc); // 1s complement of crc
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}
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BLOCK_COMMENT("} kernel_crc32_2word");
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}
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/**
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/**
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* @param crc register containing existing CRC (32-bit)
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* @param crc register containing existing CRC (32-bit)
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* @param buf register pointing to input byte buffer (byte*)
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* @param buf register pointing to input byte buffer (byte*)
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@ -835,10 +835,6 @@ class MacroAssembler: public Assembler {
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void update_1word_crc32(Register crc, Register buf, Register table, int bufDisp, int bufInc,
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void update_1word_crc32(Register crc, Register buf, Register table, int bufDisp, int bufInc,
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Register t0, Register t1, Register t2, Register t3,
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Register t0, Register t1, Register t2, Register t3,
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Register tc0, Register tc1, Register tc2, Register tc3);
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Register tc0, Register tc1, Register tc2, Register tc3);
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void kernel_crc32_2word(Register crc, Register buf, Register len, Register table,
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Register t0, Register t1, Register t2, Register t3,
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Register tc0, Register tc1, Register tc2, Register tc3,
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bool invertCRC);
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void kernel_crc32_1word(Register crc, Register buf, Register len, Register table,
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void kernel_crc32_1word(Register crc, Register buf, Register len, Register table,
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Register t0, Register t1, Register t2, Register t3,
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Register t0, Register t1, Register t2, Register t3,
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Register tc0, Register tc1, Register tc2, Register tc3,
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Register tc0, Register tc1, Register tc2, Register tc3,
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@ -62,7 +62,6 @@ class ppc64 {
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public:
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public:
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// CRC32 Intrinsics.
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// CRC32 Intrinsics.
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static void generate_load_table_addr(MacroAssembler* masm, Register table, address table_addr, uint64_t table_contents);
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static void generate_load_crc_table_addr(MacroAssembler* masm, Register table);
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static void generate_load_crc_table_addr(MacroAssembler* masm, Register table);
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static void generate_load_crc_constants_addr(MacroAssembler* masm, Register table);
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static void generate_load_crc_constants_addr(MacroAssembler* masm, Register table);
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static void generate_load_crc_barret_constants_addr(MacroAssembler* masm, Register table);
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static void generate_load_crc_barret_constants_addr(MacroAssembler* masm, Register table);
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@ -6325,75 +6325,6 @@ void MacroAssembler::update_1word_crc32(Register crc, Register buf, Register tab
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lgr_if_needed(crc, t0);
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lgr_if_needed(crc, t0);
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}
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}
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/**
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* @param crc register containing existing CRC (32-bit)
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* @param buf register pointing to input byte buffer (byte*)
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* @param len register containing number of bytes
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* @param table register pointing to CRC table
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*
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* uses Z_R10..Z_R13 as work register. Must be saved/restored by caller!
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*/
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void MacroAssembler::kernel_crc32_2word(Register crc, Register buf, Register len, Register table,
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Register t0, Register t1, Register t2, Register t3,
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bool invertCRC) {
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assert_different_registers(crc, buf, len, table);
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Label L_mainLoop, L_tail;
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Register data = t0;
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Register ctr = Z_R0;
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const int mainLoop_stepping = 8;
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const int tailLoop_stepping = 1;
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const int log_stepping = exact_log2(mainLoop_stepping);
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// Don't test for len <= 0 here. This pathological case should not occur anyway.
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// Optimizing for it by adding a test and a branch seems to be a waste of CPU cycles.
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// The situation itself is detected and handled correctly by the conditional branches
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// following aghi(len, -stepping) and aghi(len, +stepping).
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if (invertCRC) {
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not_(crc, noreg, false); // 1s complement of crc
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}
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#if 0
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{
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// Pre-mainLoop alignment did not show any positive effect on performance.
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// We leave the code in for reference. Maybe the vector instructions in z13 depend on alignment.
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z_cghi(len, mainLoop_stepping); // Alignment is useless for short data streams.
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z_brnh(L_tail);
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// Align buf to word (4-byte) boundary.
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z_lcr(ctr, buf);
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rotate_then_insert(ctr, ctr, 62, 63, 0, true); // TODO: should set cc
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z_sgfr(len, ctr); // Remaining len after alignment.
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update_byteLoop_crc32(crc, buf, ctr, table, data);
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}
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#endif
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// Check for short (<mainLoop_stepping bytes) buffer.
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z_srag(ctr, len, log_stepping);
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z_brnh(L_tail);
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z_lrvr(crc, crc); // Revert byte order because we are dealing with big-endian data.
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rotate_then_insert(len, len, 64-log_stepping, 63, 0, true); // #bytes for tailLoop
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BIND(L_mainLoop);
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update_1word_crc32(crc, buf, table, 0, 0, crc, t1, t2, t3);
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update_1word_crc32(crc, buf, table, 4, mainLoop_stepping, crc, t1, t2, t3);
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z_brct(ctr, L_mainLoop); // Iterate.
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z_lrvr(crc, crc); // Revert byte order back to original.
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// Process last few (<8) bytes of buffer.
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BIND(L_tail);
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update_byteLoop_crc32(crc, buf, len, table, data);
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if (invertCRC) {
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not_(crc, noreg, false); // 1s complement of crc
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}
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}
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/**
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/**
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* @param crc register containing existing CRC (32-bit)
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* @param crc register containing existing CRC (32-bit)
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* @param buf register pointing to input byte buffer (byte*)
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* @param buf register pointing to input byte buffer (byte*)
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@ -1056,9 +1056,6 @@ class MacroAssembler: public Assembler {
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void kernel_crc32_1word(Register crc, Register buf, Register len, Register table,
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void kernel_crc32_1word(Register crc, Register buf, Register len, Register table,
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Register t0, Register t1, Register t2, Register t3,
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Register t0, Register t1, Register t2, Register t3,
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bool invertCRC);
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bool invertCRC);
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void kernel_crc32_2word(Register crc, Register buf, Register len, Register table,
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Register t0, Register t1, Register t2, Register t3,
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bool invertCRC);
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// Emitters for BigInteger.multiplyToLen intrinsic
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// Emitters for BigInteger.multiplyToLen intrinsic
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// note: length of result array (zlen) is passed on the stack
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// note: length of result array (zlen) is passed on the stack
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