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8253183: Fragile memory barrier selection for some weak memory model platforms
Reviewed-by: dholmes, eosterlund, dcubed
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4 changed files with 23 additions and 21 deletions
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@ -1105,13 +1105,11 @@ intptr_t ObjectSynchronizer::FastHashCode(Thread* self, oop obj) {
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// Separate load of dmw/header above from the loads in
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// is_being_async_deflated().
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if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
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// A non-multiple copy atomic (nMCA) machine needs a bigger
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// hammer to separate the load above and the loads below.
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OrderAccess::fence();
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} else {
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OrderAccess::loadload();
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}
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// dmw/header and _contentions may get written by different threads.
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// Make sure to observe them in the same order when having several observers.
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OrderAccess::loadload_for_IRIW();
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if (monitor->is_being_async_deflated()) {
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// But we can't safely use the hash if we detect that async
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// deflation has occurred. So we attempt to restore the
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