diff --git a/.hgtags b/.hgtags
index 8d69e26cb9f..d63506837b5 100644
--- a/.hgtags
+++ b/.hgtags
@@ -7,3 +7,5 @@ bfe4572fd301a6fcd120373cdb2eff5d2da0c72c jdk7-b29
bee4731164a06ddece1297ae58db24aca6a1c626 jdk7-b30
cd8b8f500face60d1566d850857a7fccadbd383a jdk7-b31
a9f1805e3ba9ca520cad199d522c84af5433e85a jdk7-b32
+6838c1a3296aaa3572364d2ce7d70826cee96286 jdk7-b33
+90cf935adb353bb0af4b46fb0677e841fd24c000 jdk7-b34
diff --git a/.hgtags-top-repo b/.hgtags-top-repo
index 68910f18724..8366e3060e0 100644
--- a/.hgtags-top-repo
+++ b/.hgtags-top-repo
@@ -7,3 +7,5 @@ cbc8ad9dd0e085a607427ea35411990982f19a36 jdk7-b25
2dab2f712e1832c92acfa63ec0337048b9422c20 jdk7-b30
3300a35a0bd56d695b92fe0b34f03ebbfc939064 jdk7-b31
64da805be725721bf2004e7409a0d7a16fc8ddbc jdk7-b32
+bb1ef4ee3d2c8cbf43a37d372325a7952be590b9 jdk7-b33
+46a989ab932992b2084b946eeb322fa99b9fee6c jdk7-b34
diff --git a/Makefile b/Makefile
index 4181e29b9c4..54e5a256873 100644
--- a/Makefile
+++ b/Makefile
@@ -74,7 +74,7 @@ include ./make/deploy-rules.gmk
all::
@$(START_ECHO)
-all:: openjdk_check sanity all_product_build
+all:: openjdk_check sanity
ifeq ($(SKIP_FASTDEBUG_BUILD), false)
all:: fastdebug_build
@@ -88,6 +88,8 @@ ifneq ($(SKIP_OPENJDK_BUILD), true)
all:: openjdk_build
endif
+all:: all_product_build
+
all::
@$(FINISH_ECHO)
diff --git a/corba/.hgtags b/corba/.hgtags
index 69c0bcdfe96..d11eee86062 100644
--- a/corba/.hgtags
+++ b/corba/.hgtags
@@ -7,3 +7,5 @@ e84e9018bebbf3e5bafc5706e7882a15cb1c7d99 jdk7-b27
c0252adbb2abbfdd6c35595429ac6fbdd98e20ac jdk7-b30
ef6af34d75a7b44e77083f1d4ee47631fa09d3b4 jdk7-b31
80a0f46a6203e727012bd579fe38a609b83decce jdk7-b32
+6a5b9d2f8b20de54e3bfe33cd12bd0793caedc4e jdk7-b33
+0a812b9824e5d17b073765d1505594b49ff88a10 jdk7-b34
diff --git a/hotspot/.hgtags b/hotspot/.hgtags
index fbe09df39c2..0a20ba0d8e5 100644
--- a/hotspot/.hgtags
+++ b/hotspot/.hgtags
@@ -8,3 +8,4 @@ d1605aabd0a15ecf93787c47de63073c33fba52d jdk7-b30
9c2ecc2ffb125f14fab3857fe7689598956348a0 jdk7-b31
b727c32788a906c04839516ae7443a085185a300 jdk7-b32
585535ec8a14adafa6bfea65d6975e29094c8cec jdk7-b33
+5251a9cd8eb8743eee647365bee1c8afdc131556 jdk7-b34
diff --git a/hotspot/agent/make/build-pkglist b/hotspot/agent/make/build-pkglist
index 64d9a96cabb..c7cac3dfc05 100644
--- a/hotspot/agent/make/build-pkglist
+++ b/hotspot/agent/make/build-pkglist
@@ -8,4 +8,4 @@ FIND=$MKS_HOME/find
SED=$MKS_HOME/sed
SORT=$MKS_HOME/sort
-$CD ../src/share/classes; $FIND sun/jvm/hotspot \( -name SCCS -prune \) -o -type d -print | $SED -e 's/\//./g' | $SORT > ../../../make/pkglist.txt
+$CD ../src/share/classes; $FIND sun/jvm/hotspot com/sun/java/swing -type d -print | $SED -e 's/\//./g' | $SORT > ../../../make/pkglist.txt
diff --git a/hotspot/make/hotspot_version b/hotspot/make/hotspot_version
index 4ec4a92ff7a..bc6ca1e4f83 100644
--- a/hotspot/make/hotspot_version
+++ b/hotspot/make/hotspot_version
@@ -35,7 +35,7 @@ HOTSPOT_VM_COPYRIGHT=Copyright 2008
HS_MAJOR_VER=14
HS_MINOR_VER=0
-HS_BUILD_NUMBER=03
+HS_BUILD_NUMBER=04
JDK_MAJOR_VER=1
JDK_MINOR_VER=7
diff --git a/hotspot/make/linux/makefiles/sa.make b/hotspot/make/linux/makefiles/sa.make
index 94463d6a049..eca293bb8c0 100644
--- a/hotspot/make/linux/makefiles/sa.make
+++ b/hotspot/make/linux/makefiles/sa.make
@@ -41,8 +41,9 @@ GENERATED = $(TOPDIR)/../generated
SA_CLASSPATH = $(BOOT_JAVA_HOME)/lib/tools.jar
# gnumake 3.78.1 does not accept the *s that
-# are in AGENT_ALLFILES, so use the shell to expand them
-AGENT_ALLFILES := $(shell /usr/bin/test -d $(AGENT_DIR) && /bin/ls $(AGENT_ALLFILES))
+# are in AGENT_FILES1 and AGENT_FILES2, so use the shell to expand them
+AGENT_FILES1 := $(shell /usr/bin/test -d $(AGENT_DIR) && /bin/ls $(AGENT_FILES1))
+AGENT_FILES2 := $(shell /usr/bin/test -d $(AGENT_DIR) && /bin/ls $(AGENT_FILES2))
SA_CLASSDIR = $(GENERATED)/saclasses
@@ -58,7 +59,7 @@ all:
$(MAKE) -f sa.make $(GENERATED)/sa-jdi.jar; \
fi
-$(GENERATED)/sa-jdi.jar: $(AGENT_ALLFILES)
+$(GENERATED)/sa-jdi.jar: $(AGENT_FILES1) $(AGENT_FILES2)
$(QUIETLY) echo "Making $@"
$(QUIETLY) if [ "$(BOOT_JAVA_HOME)" = "" ]; then \
echo "ALT_BOOTDIR, BOOTDIR or JAVA_HOME needs to be defined to build SA"; \
@@ -72,9 +73,18 @@ $(GENERATED)/sa-jdi.jar: $(AGENT_ALLFILES)
$(QUIETLY) if [ ! -d $(SA_CLASSDIR) ] ; then \
mkdir -p $(SA_CLASSDIR); \
fi
- $(QUIETLY) $(REMOTE) $(COMPILE.JAVAC) -source 1.4 -classpath $(SA_CLASSPATH) -g -d $(SA_CLASSDIR) $(AGENT_ALLFILES)
+
+ $(QUIETLY) $(REMOTE) $(COMPILE.JAVAC) -source 1.4 -classpath $(SA_CLASSPATH) -sourcepath $(AGENT_SRC_DIR) -g -d $(SA_CLASSDIR) $(AGENT_FILES1)
+ $(QUIETLY) $(REMOTE) $(COMPILE.JAVAC) -source 1.4 -classpath $(SA_CLASSPATH) -sourcepath $(AGENT_SRC_DIR) -g -d $(SA_CLASSDIR) $(AGENT_FILES2)
+
$(QUIETLY) $(REMOTE) $(COMPILE.RMIC) -classpath $(SA_CLASSDIR) -d $(SA_CLASSDIR) sun.jvm.hotspot.debugger.remote.RemoteDebuggerServer
$(QUIETLY) echo "$(SA_BUILD_VERSION_PROP)" > $(SA_PROPERTIES)
+ $(QUIETLY) rm -f $(SA_CLASSDIR)/sun/jvm/hotspot/utilities/soql/sa.js
+ $(QUIETLY) cp $(AGENT_SRC_DIR)/sun/jvm/hotspot/utilities/soql/sa.js $(SA_CLASSDIR)/sun/jvm/hotspot/utilities/soql
+ $(QUIETLY) mkdir -p $(SA_CLASSDIR)/sun/jvm/hotspot/ui/resources
+ $(QUIETLY) rm -f $(SA_CLASSDIR)/sun/jvm/hotspot/ui/resources/*
+ $(QUIETLY) cp $(AGENT_SRC_DIR)/sun/jvm/hotspot/ui/resources/*.png $(SA_CLASSDIR)/sun/jvm/hotspot/ui/resources/
+ $(QUIETLY) cp -r $(AGENT_SRC_DIR)/images/* $(SA_CLASSDIR)/
$(QUIETLY) $(REMOTE) $(RUN.JAR) cf $@ -C $(SA_CLASSDIR)/ .
$(QUIETLY) $(REMOTE) $(RUN.JAR) uf $@ -C $(AGENT_SRC_DIR) META-INF/services/com.sun.jdi.connect.Connector
$(QUIETLY) $(REMOTE) $(RUN.JAVAH) -classpath $(SA_CLASSDIR) -d $(GENERATED) -jni sun.jvm.hotspot.debugger.x86.X86ThreadContext
diff --git a/hotspot/make/sa.files b/hotspot/make/sa.files
index 6f76f9d8faa..7040cf517e7 100644
--- a/hotspot/make/sa.files
+++ b/hotspot/make/sa.files
@@ -33,40 +33,23 @@
AGENT_SRC_DIR = $(AGENT_DIR)/src/share/classes
-AGENT_ALLFILES = \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/DebugServer.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/HelloWorld.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/HotSpotAgent.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/HotSpotSolarisVtblAccess.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/HotSpotTypeDataBase.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/LinuxVtblAccess.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/ObjectHistogram.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/RMIHelper.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/StackTrace.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/TestDebugger.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/Win32VtblAccess.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/Immediate.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/ImmediateOrRegister.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/Operand.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/Register.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/amd64/AMD64Register.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/amd64/AMD64Registers.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/ia64/IA64Register.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/ia64/IA64Registers.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/sparc/SPARCArgument.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/sparc/SPARCRegister.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/sparc/SPARCRegisterType.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/sparc/SPARCRegisters.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/x86/X86Register.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/x86/X86RegisterPart.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/x86/X86Registers.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/x86/X86SegmentRegister.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/x86/X86SegmentRegisters.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/bugspot/BugSpotAgent.java \
+# Splitted the set of files into two sets because on linux plaform
+# listing or compiling all the files results in 'Argument list too long' error.
+
+AGENT_FILES1 = \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/amd64/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/ia64/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/sparc/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/asm/x86/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/bugspot/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/bugspot/tree/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/c1/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/code/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/compiler/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/amd64/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/cdbg/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/cdbg/basic/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/cdbg/basic/x86/*.java \
@@ -75,7 +58,6 @@ $(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/dbx/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/dbx/sparc/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/dbx/x86/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/dummy/*.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/amd64/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/ia64/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/linux/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/debugger/linux/amd64/*.java \
@@ -107,7 +89,10 @@ $(AGENT_SRC_DIR)/sun/jvm/hotspot/interpreter/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/jdi/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/livejvm/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/memory/*.java \
-$(AGENT_SRC_DIR)/sun/jvm/hotspot/oops/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/oops/*.java
+
+
+AGENT_FILES2 = \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/runtime/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/runtime/amd64/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/runtime/ia64/*.java \
@@ -127,7 +112,17 @@ $(AGENT_SRC_DIR)/sun/jvm/hotspot/runtime/win32_x86/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/runtime/x86/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/tools/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/tools/jcore/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/tools/soql/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/types/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/types/basic/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/utilities/*.java \
$(AGENT_SRC_DIR)/sun/jvm/hotspot/utilities/memo/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/utilities/soql/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/ui/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/ui/action/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/ui/classbrowser/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/ui/table/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/ui/tree/*.java \
+$(AGENT_SRC_DIR)/sun/jvm/hotspot/ui/treetable/*.java \
+$(AGENT_SRC_DIR)/com/sun/java/swing/action/*.java \
+$(AGENT_SRC_DIR)/com/sun/java/swing/ui/*.java
diff --git a/hotspot/make/solaris/makefiles/reorder_COMPILER1_amd64 b/hotspot/make/solaris/makefiles/reorder_COMPILER1_amd64
new file mode 100644
index 00000000000..fdc435bbf27
--- /dev/null
+++ b/hotspot/make/solaris/makefiles/reorder_COMPILER1_amd64
@@ -0,0 +1,5450 @@
+data = R0x2000;
+text = LOAD ?RXO;
+
+
+# Test Null
+text: .text%__cplus_fini_at_exit: CCrti.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: arguments.o;
+text: .text%__1cQAgentLibraryList2t6M_v_: arguments.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_AllocTable.o;
+text: .text%__1cFRInfo2t6M_v_: c1_AllocTable.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_AllocTable_x86.o;
+text: .text%__1cFRInfo2t6M_v_: c1_AllocTable_x86.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_CacheLocals.o;
+text: .text%__1cFRInfo2t6M_v_: c1_CacheLocals.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_CacheLocals_x86.o;
+text: .text%__1cFRInfo2t6M_v_: c1_CacheLocals_x86.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_Canonicalizer.o;
+text: .text%__1cFRInfo2t6M_v_: c1_Canonicalizer.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_CodeGenerator.o;
+text: .text%__1cFRInfo2t6M_v_: c1_CodeGenerator.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_CodeGenerator_x86.o;
+text: .text%__1cFRInfo2t6M_v_: c1_CodeGenerator_x86.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_CodeStubs_x86.o;
+text: .text%__1cFRInfo2t6M_v_: c1_CodeStubs_x86.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_Compilation.o;
+text: .text%__1cFRInfo2t6M_v_: c1_Compilation.o;
+text: .text%__1cMelapsedTimer2t6M_v_: c1_Compilation.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_Compiler.o;
+text: .text%__1cFRInfo2t6M_v_: c1_Compiler.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_FrameMap.o;
+text: .text%__1cFRInfo2t6M_v_: c1_FrameMap.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_FrameMap_x86.o;
+text: .text%__1cFRInfo2t6M_v_: c1_FrameMap_x86.o;
+text: .text%__1cKc1_RegMask2t6M_v_: c1_FrameMap_x86.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_GraphBuilder.o;
+text: .text%__1cFRInfo2t6M_v_: c1_GraphBuilder.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_IR.o;
+text: .text%__1cFRInfo2t6M_v_: c1_IR.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_Instruction.o;
+text: .text%__1cFRInfo2t6M_v_: c1_Instruction.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_InstructionPrinter.o;
+text: .text%__1cFRInfo2t6M_v_: c1_InstructionPrinter.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_Items.o;
+text: .text%__1cFRInfo2t6M_v_: c1_Items.o;
+text: .text%__1cIHintItem2t6MpnJValueType_i_v_: c1_Items.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_Items_x86.o;
+text: .text%__1cFRInfo2t6M_v_: c1_Items_x86.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_LIR.o;
+text: .text%__1cFRInfo2t6M_v_: c1_LIR.o;
+text: .text%__1cLLIR_OprFactHillegal6F_pnLLIR_OprDesc__: c1_LIR.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_LIRAssembler.o;
+text: .text%__1cFRInfo2t6M_v_: c1_LIRAssembler.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_LIRAssembler_x86.o;
+text: .text%__1cFRInfo2t6M_v_: c1_LIRAssembler_x86.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_LIREmitter.o;
+text: .text%__1cFRInfo2t6M_v_: c1_LIREmitter.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_LIREmitter_x86.o;
+text: .text%__1cFRInfo2t6M_v_: c1_LIREmitter_x86.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_LIROptimizer.o;
+text: .text%__1cFRInfo2t6M_v_: c1_LIROptimizer.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_Loops.o;
+text: .text%__1cFRInfo2t6M_v_: c1_Loops.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_MacroAssembler_x86.o;
+text: .text%__1cFRInfo2t6M_v_: c1_MacroAssembler_x86.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_Optimizer.o;
+text: .text%__1cFRInfo2t6M_v_: c1_Optimizer.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_RInfo.o;
+text: .text%__1cFRInfo2t6M_v_: c1_RInfo.o;
+text: .text%__1cKc1_RegMask2t6M_v_: c1_RInfo.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_RInfo_x86.o;
+text: .text%__1cFRInfo2t6M_v_: c1_RInfo_x86.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_RegAlloc.o;
+text: .text%__1cFRInfo2t6M_v_: c1_RegAlloc.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_RegAlloc_x86.o;
+text: .text%__1cFRInfo2t6M_v_: c1_RegAlloc_x86.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_Runtime1.o;
+text: .text%__1cFRInfo2t6M_v_: c1_Runtime1.o;
+text: .text%__1cIiEntries2t6M_v_;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_Runtime1_x86.o;
+text: .text%__1cFRInfo2t6M_v_: c1_Runtime1_x86.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_ScanBlocks.o;
+text: .text%__1cFRInfo2t6M_v_: c1_ScanBlocks.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_ValueMap.o;
+text: .text%__1cFRInfo2t6M_v_: c1_ValueMap.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_ValueSet.o;
+text: .text%__1cFRInfo2t6M_v_: c1_ValueSet.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_ValueStack.o;
+text: .text%__1cFRInfo2t6M_v_: c1_ValueStack.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: codeBlob.o;
+text: .text%__1cFRInfo2t6M_v_: codeBlob.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: codeCache.o;
+text: .text%__1cICHeapObj2n6FI_pv_;
+text: .text%__1cCosGmalloc6FI_pv_;
+text: .text%__1cICodeHeap2t6M_v_;
+text: .text%__1cMVirtualSpace2t6M_v_;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: compilationPolicy.o;
+text: .text%__1cMelapsedTimer2t6M_v_: compilationPolicy.o;
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+text: .text%__1cNSharedRuntimeOresolve_helper6FpnKJavaThread_iipnGThread__nMmethodHandle__;
+text: .text%__1cNSharedRuntimeSresolve_sub_helper6FpnKJavaThread_iipnGThread__nMmethodHandle__;
+text: .text%__1cFframeZsender_for_compiled_frame6kMpnLRegisterMap_pnICodeBlob_i_0_;
+text: .text%__1cLRuntimeStubYcaller_must_gc_arguments6kMpnKJavaThread__i_: codeBlob.o;
+text: .text%__1cHnmethodJis_zombie6kM_i_: nmethod.o;
+text: .text%__1cNnmethodLocker2t6MpnHnmethod__v_;
+text: .text%__1cNSharedRuntimeQfind_callee_info6FpnKJavaThread_rnJBytecodesECode_rnICallInfo_pnGThread__nGHandle__;
+text: .text%__1cHnmethodQis_native_method6kM_i_: nmethod.o;
+text: .text%__1cHnmethodKpc_desc_at6MpCi_pnGPcDesc__;
+text: .text%__1cGPcDescHreal_pc6kMpknHnmethod__pC_;
+text: .text%__1cLPcDescCacheKpc_desc_at6kMpnHnmethod_pCi_pnGPcDesc__;
+text: .text%__1cLPcDescCacheLadd_pc_desc6MpnGPcDesc__v_;
+text: .text%__1cSvframeStreamCommonYfill_from_compiled_frame6MpnHnmethod_i_v_;
+text: .text%__1cUCompressedReadStreamMraw_read_int6FrpC_i_: vframe.o;
+text: .text%__1cICodeBlobLoop_addr_at6kMi_ppnHoopDesc__;
+text: .text%__1cNSharedRuntimeXfind_callee_info_helper6FpnKJavaThread_rnMvframeStream_rnJBytecodesECode_rnICallInfo_pnGThread__nGHandle__;
+text: .text%__1cPBytecode_invokeNstatic_target6MpnGThread__nMmethodHandle__;
+text: .text%__1cMLinkResolverOresolve_method6FrnMmethodHandle_rnLKlassHandle_nSconstantPoolHandle_ipnGThread__v_;
+text: .text%__1cKCompiledICZcompute_monomorphic_entry6FnMmethodHandle_nLKlassHandle_iirnOCompiledICInfo_pnGThread__v_;
+text: .text%__1cKCompiledIC2t6MpnKNativeCall__v_;
+text: .text%__1cXvirtual_call_RelocationIparse_ic6FrpnICodeBlob_rpC5rppnHoopDesc_pi_nNRelocIterator__;
+text: .text%__1cKCompiledICIis_clean6kM_i_;
+text: .text%__1cKCompiledICOic_destination6kM_pC_;
+text: .text%__1cKCompiledICWis_in_transition_state6kM_i_;
+text: .text%__1cRInlineCacheBufferIcontains6FpC_i_;
+text: .text%__1cKCompiledICSset_to_monomorphic6MrknOCompiledICInfo__v_;
+text: .text%__1cSCompiledStaticCallSset_to_interpreted6MnMmethodHandle_pC_v_;
+text: .text%__1cSCompiledStaticCallJfind_stub6M_pC_;
+text: .text%__1cNRelocIteratorEnext6M_i_: compiledIC.o;
+text: .text%__1cPBoundRelocationLunpack_data6MnJrelocInfoJrelocType__v_: compiledIC.o;
+text: .text%__1cbBopt_virtual_call_RelocationLstatic_stub6M_pC_;
+text: .text%__1cKNativeCallXset_destination_mt_safe6MpC_v_;
+text: .text%__1cNnmethodLocker2T6M_v_;
+text: .text%__1cNmethodOopDescTverified_code_entry6M_pC_;
+text: .text%jni_GetByteArrayRegion: jni.o;
+text: .text%JVM_DefineClassWithSource;
+text: .text%__1cXjvm_define_class_common6FpnHJNIEnv__pkcpnI_jobject_pkWi53pnGThread__pnH_jclass__: jvm.o;
+text: .text%__1cQSystemDictionaryTresolve_from_stream6FnMsymbolHandle_nGHandle_2pnPClassFileStream_pnGThread__pnMklassOopDesc__;
+text: .text%__1cPClassFileParserbDverify_legal_method_signature6MnMsymbolHandle_1pnGThread__i_;
+text: .text%__1cPClassFileParserZskip_over_field_signature6MpciIpnGThread__1_;
+text: .text%__1cPClassFileParserXverify_legal_class_name6MnMsymbolHandle_pnGThread__v_;
+text: .text%__1cQput_after_lookup6FnMsymbolHandle_0ppnLNameSigHash__i_;
+text: .text%__1cEhash6Fpkc1_I_;
+text: .text%__1cKDictionarybAis_valid_protection_domain6MiInMsymbolHandle_nGHandle_2_i_;
+text: .text%__1cPDictionaryEntrybAcontains_protection_domain6kMpnHoopDesc__i_;
+text: .text%__1cQSystemDictionarybAvalidate_protection_domain6FnTinstanceKlassHandle_nGHandle_2pnGThread__v_;
+text: .text%__1cKDictionaryVadd_protection_domain6MiInTinstanceKlassHandle_nGHandle_2pnGThread__v_;
+text: .text%__1cPDictionaryEntryVadd_protection_domain6MpnHoopDesc__v_;
+text: .text%__1cUverify_byte_codes_fn6F_pv_: verifier.o;
+text: .text%JVM_GetClassCPEntriesCount;
+text: .text%JVM_GetClassCPTypes;
+text: .text%JVM_GetClassNameUTF;
+text: .text%JVM_ReleaseUTF;
+text: .text%JVM_FindClassFromClass;
+text: .text%jni_IsSameObject: jni.o;
+text: .text%JVM_GetClassFieldsCount;
+text: .text%JVM_GetClassMethodsCount;
+text: .text%JVM_GetMethodIxModifiers;
+text: .text%JVM_GetMethodIxByteCodeLength;
+text: .text%JVM_GetMethodIxByteCode;
+text: .text%JVM_GetMethodIxExceptionTableLength;
+text: .text%JVM_GetMethodIxLocalsCount;
+text: .text%JVM_GetMethodIxArgsSize;
+text: .text%JVM_GetMethodIxSignatureUTF;
+text: .text%JVM_GetMethodIxMaxStack;
+text: .text%JVM_GetMethodIxExceptionsCount;
+text: .text%JVM_GetMethodIxExceptionIndexes;
+text: .text%JVM_GetCPMethodNameUTF;
+text: .text%JVM_GetCPMethodClassNameUTF;
+text: .text%jni_NewLocalRef: jni.o;
+text: .text%JVM_GetCPMethodModifiers;
+text: .text%JVM_IsConstructorIx;
+text: .text%JVM_GetCPMethodSignatureUTF;
+text: .text%jni_DeleteGlobalRef: jni.o;
+text: .text%__1cQSystemDictionaryVadd_loader_constraint6FnMsymbolHandle_nGHandle_2pnGThread__v_;
+text: .text%__1cVLoaderConstraintTableJadd_entry6MnMsymbolHandle_pnMklassOopDesc_nGHandle_34pnGThread__i_;
+text: .text%__1cVLoaderConstraintTableJnew_entry6MIpnNsymbolOopDesc_pnMklassOopDesc_ii_pnVLoaderConstraintEntry__;
+text: .text%jni_ToReflectedMethod: jni.o;
+text: .text%__1cKReflectionKnew_method6FnMmethodHandle_iipnGThread__pnHoopDesc__;
+text: .text%__1cNSignatureInfoIdo_array6Mii_v_: reflection.o;
+text: .text%__1cYjava_lang_reflect_MethodGcreate6FpnGThread__nGHandle__;
+text: .text%__1cYjava_lang_reflect_MethodJset_clazz6FpnHoopDesc_2_v_;
+text: .text%__1cYjava_lang_reflect_MethodIset_slot6FpnHoopDesc_i_v_;
+text: .text%__1cYjava_lang_reflect_MethodIset_name6FpnHoopDesc_2_v_;
+text: .text%__1cYjava_lang_reflect_MethodPset_return_type6FpnHoopDesc_2_v_;
+text: .text%__1cYjava_lang_reflect_MethodTset_parameter_types6FpnHoopDesc_2_v_;
+text: .text%__1cYjava_lang_reflect_MethodTset_exception_types6FpnHoopDesc_2_v_;
+text: .text%__1cYjava_lang_reflect_MethodNset_modifiers6FpnHoopDesc_i_v_;
+text: .text%__1cYjava_lang_reflect_MethodThas_signature_field6F_i_;
+text: .text%__1cYjava_lang_reflect_MethodVhas_annotations_field6F_i_;
+text: .text%__1cYjava_lang_reflect_MethodPset_annotations6FpnHoopDesc_2_v_;
+text: .text%__1cYjava_lang_reflect_MethodbFhas_parameter_annotations_field6F_i_;
+text: .text%__1cYjava_lang_reflect_MethodZset_parameter_annotations6FpnHoopDesc_2_v_;
+text: .text%__1cYjava_lang_reflect_MethodbChas_annotation_default_field6F_i_;
+text: .text%__1cNmethodOopDescSannotation_default6kM_pnQtypeArrayOopDesc__;
+text: .text%__1cYjava_lang_reflect_MethodWset_annotation_default6FpnHoopDesc_2_v_;
+text: .text%jni_CallIntMethod: jni.o;
+text: .text%jni_CallStaticVoidMethod: jni.o;
+text: .text%jni_DetachCurrentThread;
+text: .text%__1cKJavaThreadEexit6Mi_v_;
+text: .text%__1cQjava_lang_ThreadLthreadGroup6FpnHoopDesc__2_;
+text: .text%JVM_MonitorNotifyAll;
+text: .text%__1cNThreadServiceWcurrent_thread_exiting6FpnKJavaThread__v_;
+text: .text%__1cLensure_join6FpnKJavaThread__v_: thread.o;
+text: .text%__1cQjava_lang_ThreadNset_stillborn6FpnHoopDesc__v_;
+text: .text%__1cKJavaThreadYremove_stack_guard_pages6M_v_;
+text: .text%__1cWThreadLocalAllocBufferFclear6M_v_;
+text: .text%__1cHThreadsGremove6FpnKJavaThread__v_;
+text: .text%__1cNThreadServiceNremove_thread6FpnKJavaThread_i_v_;
+text: .text%__SLIP.DELETER__A: thread.o;
+text: .text%__1cKJavaThread2T6M_v_;
+text: .text%__1cGParker2T6M_v_;
+text: .text%__1cHMonitor2T6M_v_;
+text: .text%__1cFMutex2T6M_v_;
+text: .text%lwp_cond_destroy: os_solaris.o;
+text: .text%lwp_mutex_destroy: os_solaris.o;
+text: .text%__1cUThreadSafepointStateHdestroy6FpnKJavaThread__v_;
+text: .text%__1cUThreadSafepointState2T6M_v_;
+text: .text%__1cGThread2T5B6M_v_;
+text: .text%__1cCosLfree_thread6FpnIOSThread__v_;
+text: .text%__1cIOSThread2T6M_v_;
+text: .text%__1cIOSThreadKpd_destroy6M_v_;
+text: .text%jni_DestroyJavaVM;
+text: .text%jni_AttachCurrentThread;
+text: .text%attach_current_thread: jni.o;
+text: .text%__1cCosWcreate_attached_thread6FpnGThread__i_;
+text: .text%__1cKJavaThreadSallocate_threadObj6MnGHandle_pcipnGThread__v_;
+text: .text%__1cHThreadsKdestroy_vm6F_i_;
+text: .text%__1cKJavaThreadVinvoke_shutdown_hooks6M_v_;
+text: .text%__1cLbefore_exit6FpnKJavaThread__v_;
+text: .text%__1cNWatcherThreadEstop6F_v_;
+text: .text%__1cLStatSamplerJdisengage6F_v_;
+text: .text%__1cMPeriodicTaskJdisenroll6M_v_;
+text: .text%__1cMPeriodicTask2T5B6M_v_;
+text: .text%__1cMPeriodicTaskLis_enrolled6kM_i_;
+text: .text%__1cLStatSamplerHdestroy6F_v_;
+text: .text%__1cMPerfDataList2T6M_v_;
+text: .text%__1cLJvmtiExportNpost_vm_death6F_v_;
+text: .text%__1cUJvmtiEventControllerIvm_death6F_v_;
+text: .text%__1cCosXterminate_signal_thread6F_v_;
+text: .text%__1cCosNsigexitnum_pd6F_i_;
+text: .text%__1cCosNsignal_notify6Fi_v_;
+text: .text%__1cQprint_statistics6F_v_;
+text: .text%__1cFVTuneEexit6F_v_;
+text: .text%__1cIVMThreadXwait_for_vm_thread_exit6F_v_;
+text: .text%__1cUSafepointSynchronizeFbegin6F_v_;
+text: .text%__1cORuntimeServiceWrecord_safepoint_begin6F_v_;
+text: .text%__1cJTimeStampSticks_since_update6kM_x_;
+text: .text%__1cTAbstractInterpreterRnotice_safepoints6F_v_;
+text: .text%__1cKcopy_table6FppC1i_v_: interpreter.o;
+text: .text%__1cUSafepointSynchronizeFblock6FpnKJavaThread__v_;
+text: .text%__1cCosRcurrent_thread_id6F_i_;
+text: .text%__1cJttyLockerbCbreak_tty_lock_for_safepoint6Fi_v_;
+text: .text%__1cCosbCmake_polling_page_unreadable6F_v_;
+text: .text%__1cUThreadSafepointStateXexamine_state_of_thread6Mi_v_;
+text: .text%__1cUSafepointSynchronizeOsafepoint_safe6FpnKJavaThread_nPJavaThreadState__i_;
+text: .text%__1cUThreadSafepointStateMroll_forward6Mn0AMsuspend_type_pnHnmethod_i_v_;
+text: .text%__1cORuntimeServicebDrecord_safepoint_synchronized6F_v_;
+text: .text%__1cUSafepointSynchronizeQdo_cleanup_tasks6F_v_;
+text: .text%__1cSObjectSynchronizerVdeflate_idle_monitors6F_v_;
+text: .text%__1cNObjectMonitorHis_busy6kM_i_;
+text: .text%__1cRInlineCacheBufferUupdate_inline_caches6F_v_;
+text: .text%__1cMCounterDecayFdecay6F_v_;
+text: .text%__1cQSystemDictionaryRnumber_of_classes6F_i_;
+text: .text%__1cQSystemDictionaryStry_get_next_class6F_pnMklassOopDesc__;
+text: .text%__1cKDictionaryStry_get_next_class6M_pnMklassOopDesc__;
+text: .text%__1cNinstanceKlassKmethods_do6MpFpnNmethodOopDesc__v_v_;
+text: .text%__1cJdo_method6FpnNmethodOopDesc__v_: recompilationMonitor.o;
+text: .text%__1cONMethodSweeperFsweep6F_v_;
+text: .text%__1cNCompileBrokerQset_should_block6F_v_;
+text: .text%__1cHVM_ExitbJwait_for_threads_in_native_to_block6F_i_;
+text: .text%__1cURecompilationMonitorbFstop_recompilation_monitor_task6F_v_;
+text: .text%__1cIVMThreadHdestroy6F_v_;
+text: .text%__SLIP.DELETER__A: vmThread.o;
+text: .text%__1cSThreadLocalStorageRpd_invalidate_all6F_v_;
+text: .text%__1cHVM_ExitNset_vm_exited6F_i_;
+text: .text%__1cMexit_globals6F_v_;
+text: .text%__1cVverificationType_exit6F_v_;
+text: .text%__1cQVerificationTypeIfinalize6F_v_;
+text: .text%__1cPperfMemory_exit6F_v_;
+text: .text%__1cPPerfDataManagerHdestroy6F_v_;
+text: .text%__1cIPerfData2T6M_v_;
+text: .text%__1cKPerfMemoryHdestroy6F_v_;
+text: .text%__1cKPerfMemoryUdelete_memory_region6F_v_;
+text: .text%__1cUdelete_shared_memory6FpcI_v_: perfMemory_solaris.o;
+text: .text%__1cLremove_file6Fpkc_v_: perfMemory_solaris.o;
+text: .text%__1cMostream_exit6F_v_;
+text: .text%__SLIP.DELETER__C: ostream.o;
+text: .text%__SLIP.FINAL__A: c1_Items.o;
+# Test Exit
+text: .text%__1cPSignatureStreamHis_done6kM_i_;
+text: .text%JVM_Halt;
+text: .text%__1cHvm_exit6Fi_v_;
+text: .text%__1cIVMThreadHexecute6FpnMVM_Operation__v_;
+text: .text%__1cMVM_OperationNdoit_prologue6M_i_: vm_operations.o;
+text: .text%__1cGThreadMget_priority6Fkpk0_nOThreadPriority__;
+text: .text%__1cCosMget_priority6FkpknGThread_rnOThreadPriority__nIOSReturn__;
+text: .text%__1cCosTget_native_priority6FkpknGThread_pi_nIOSReturn__;
+text: .text%__1cMVM_OperationSset_calling_thread6MpnGThread_nOThreadPriority__v_;
+text: .text%__1cMVM_OperationPevaluation_mode6kM_n0AEMode__: vm_operations.o;
+text: .text%__1cMVM_OperationSis_cheap_allocated6kM_i_: vm_operations.o;
+text: .text%__1cQVMOperationQdDueueDadd6MpnMVM_Operation__i_;
+text: .text%__1cQVMOperationQdDueueOqueue_add_back6MipnMVM_Operation__v_;
+text: .text%__1cQVMOperationQdDueueGinsert6MpnMVM_Operation_2_v_;
+text: .text%__1cQVMOperationQdDueueGunlink6MpnMVM_Operation__v_;
+text: .text%__1cHVM_ExitEname6kM_pkc_: vm_operations.o;
+text: .text%__1cJEventMark2t6MpkcE_v_: vmThread.o;
+text: .text%__1cCosJyield_all6Fi_v_;
+text: .text%__1cGThreadRis_Watcher_thread6kM_i_: vmThread.o;
+text: .text%__1cSInterpreterRuntimeMat_safepoint6FpnKJavaThread__v_;
+text: .text%__1cIVMThreadSevaluate_operation6MpnMVM_Operation__v_;
+text: .text%__1cMVM_OperationIevaluate6M_v_;
+text: .text%__1cHVM_ExitEdoit6M_v_;
+# Test Hello
+text: .text%JVM_GetCPFieldSignatureUTF;
+text: .text%JVM_Write;
+text: .text%__1cDhpiFwrite6FipkvI_I_: jvm.o;
+# Test Sleep
+text: .text%JVM_GetMethodIxExceptionTableEntry;
+text: .text%JVM_GetCPClassNameUTF;
+text: .text%JVM_Sleep;
+text: .text%__1cCosHSolarisTsetup_interruptible6F_pnKJavaThread__;
+text: .text%__1cCosHSolarisTsetup_interruptible6FpnKJavaThread__v_;
+text: .text%__1cUSafepointSynchronizeRis_cleanup_needed6F_i_;
+text: .text%__1cRInlineCacheBufferIis_empty6F_i_;
+text: .text%__1cCosHSolarisVcleanup_interruptible6FpnKJavaThread__v_;
+text: .text%__1cCosOunguard_memory6FpcI_i_;
+# Test IntToString
+text: .text%__1cQChunkPoolCleanerEtask6M_v_: allocation.o;
+text: .text%__1cJChunkPoolMfree_all_but6MI_v_: allocation.o;
+# Test LoadToolkit
+text: .text%JVM_GetClassContext;
+text: .text%__1cNCollectedHeapMobj_allocate6FnLKlassHandle_ipnGThread__pnHoopDesc__: jvm.o;
+text: .text%jni_IsAssignableFrom: jni.o;
+text: .text%__1cOGenerateOopMapGdo_ldc6Mii_v_;
+text: .text%__1cQComputeCallStackIdo_array6Mii_v_: generateOopMap.o;
+text: .text%__1cMGraphBuilderNload_constant6M_v_;
+text: .text%__1cQciBytecodeStreamMget_constant6kM_nKciConstant__;
+text: .text%__1cQciBytecodeStreamSget_constant_index6kM_i_;
+text: .text%__1cFciEnvVget_constant_by_index6MpnPciInstanceKlass_i_nKciConstant__;
+text: .text%__1cFciEnvbAget_constant_by_index_impl6MpnPciInstanceKlass_i_nKciConstant__;
+text: .text%__1cMLinkResolverbBresolve_static_call_or_null6FnLKlassHandle_nMsymbolHandle_21_nMmethodHandle__;
+text: .text%__1cLInstructionMas_LoadLocal6M_pnJLoadLocal__: c1_Canonicalizer.o;
+text: .text%__1cTsort_by_start_block6FppnELoop_2_i_: c1_Loops.o;
+text: .text%__1cILIR_ListLcall_static6MpnLLIR_OprDesc_pCpnMCodeEmitInfo_pnOStaticCallStub__v_: c1_LIREmitter.o;
+text: .text%__1cLLIR_EmitterLcmp_mem_int6MnMLIR_OpBranchNLIR_Condition_nFRInfo_iipnMCodeEmitInfo__v_;
+text: .text%__1cILIR_ListLcmp_mem_int6MnMLIR_OpBranchNLIR_Condition_nFRInfo_iipnMCodeEmitInfo__v_;
+text: .text%__1cJValueTypeLas_VoidType6M_pnIVoidType__: c1_Canonicalizer.o;
+text: .text%__1cILIR_ListHint2reg6MinFRInfo__v_: c1_LIREmitter.o;
+text: .text%__1cWstatic_call_RelocationEtype6M_nJrelocInfoJrelocType__: relocInfo.o;
+text: .text%__1cRComputeEntryStackIdo_array6Mii_v_: generateOopMap.o;
+text: .text%__1cKValueStackEpush6MpnJValueType_pnLInstruction__v_: c1_Optimizer.o;
+text: .text%__1cEIfOpPinput_values_do6MpFppnLInstruction__v_v_: c1_Instruction.o;
+text: .text%__1cEIfOpFvisit6MpnSInstructionVisitor__v_: c1_Instruction.o;
+text: .text%__1cQNullCheckVisitorHdo_IfOp6MpnEIfOp__v_;
+text: .text%__1cIValueGenHdo_IfOp6MpnEIfOp__v_;
+text: .text%__1cLLIR_EmitterLifop_phase16MnLInstructionJCondition_pnLLIR_OprDesc_4_v_;
+text: .text%__1cLLIR_EmitterLifop_phase26MnFRInfo_pnLLIR_OprDesc_3nLInstructionJCondition__v_;
+text: .text%__1cILIR_ListGbranch6MnMLIR_OpBranchNLIR_Condition_pnFLabel__v_;
+text: .text%__1cRLIR_PeepholeStateUstart_forward_branch6MpnFLabel__v_;
+text: .text%__1cOGenerateOopMapMdo_checkcast6M_v_;
+text: .text%__1cMGraphBuilderLinstance_of6Mi_v_;
+text: .text%__1cKInstanceOfFvisit6MpnSInstructionVisitor__v_: c1_GraphBuilder.o;
+text: .text%__1cNCanonicalizerNdo_InstanceOf6MpnKInstanceOf__v_;
+text: .text%__1cJTypeCheckIcan_trap6kM_i_: c1_GraphBuilder.o;
+text: .text%__1cMGraphBuilderOdirect_compare6MpnHciKlass__i_;
+text: .text%__1cKInstanceOfNas_InstanceOf6M_p0_: c1_GraphBuilder.o;
+text: .text%__1cMGraphBuilderKcheck_cast6Mi_v_;
+text: .text%__1cJCheckCastFvisit6MpnSInstructionVisitor__v_: c1_GraphBuilder.o;
+text: .text%__1cNCanonicalizerMdo_CheckCast6MpnJCheckCast__v_;
+text: .text%__1cJValueTypeKas_IntType6M_pnHIntType__: c1_ValueType.o;
+text: .text%__1cJTypeCheckPinput_values_do6MpFppnLInstruction__v_v_: c1_GraphBuilder.o;
+text: .text%__1cQNullCheckVisitorNdo_InstanceOf6MpnKInstanceOf__v_;
+text: .text%__1cQNullCheckVisitorMdo_CheckCast6MpnJCheckCast__v_;
+text: .text%__1cIValueGenNdo_InstanceOf6MpnKInstanceOf__v_;
+text: .text%__1cLLIR_OprDescIsize_for6FnJBasicType__n0AHOprSize__: c1_CodeGenerator_x86.o;
+text: .text%__1cLLIR_EmitterNinstanceof_op6MpnLLIR_OprDesc_2pnHciKlass_nFRInfo_5ipnMCodeEmitInfo__v_;
+text: .text%__1cILIR_ListKinstanceof6MpnLLIR_OprDesc_2pnHciKlass_22ipnMCodeEmitInfo__v_;
+text: .text%__1cPLIR_OpTypeCheck2t6MnILIR_Code_pnLLIR_OprDesc_3pnHciKlass_33ipnMCodeEmitInfo_7pnICodeStub__v_;
+text: .text%__1cIValueGenMdo_CheckCast6MpnJCheckCast__v_;
+text: .text%__1cILIR_ListJcheckcast6MpnLLIR_OprDesc_2pnHciKlass_22ipnMCodeEmitInfo_6pnICodeStub__v_;
+text: .text%__1cILIR_ListJsafepoint6MnFRInfo_pnMCodeEmitInfo__v_: c1_CodeGenerator_x86.o;
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+text: .text%__1cICompilerMsupports_osr6M_i_: c1_Compiler.o;
+text: .text%__1cHciKlassOis_subclass_of6Mp0_i_;
+text: .text%__1cMGraphBuilderQnew_object_array6M_v_;
+text: .text%__1cONewObjectArrayFvisit6MpnSInstructionVisitor__v_: c1_Instruction.o;
+text: .text%__1cNCanonicalizerRdo_NewObjectArray6MpnONewObjectArray__v_;
+text: .text%__1cPciObjArrayKlass2t6MnLKlassHandle__v_;
+text: .text%__1cPciObjArrayKlassGloader6M_pnHoopDesc__: ciObjArrayKlass.o;
+text: .text%__1cMGraphBuilderIshift_op6MpnJValueType_nJBytecodesECode__v_;
+text: .text%__1cHShiftOpFvisit6MpnSInstructionVisitor__v_: c1_GraphBuilder.o;
+text: .text%__1cNCanonicalizerKdo_ShiftOp6MpnHShiftOp__v_;
+text: .text%__1cHShiftOpEhash6kM_i_: c1_GraphBuilder.o;
+text: .text%__1cHShiftOpEname6kM_pkc_: c1_GraphBuilder.o;
+text: .text%__1cLLoadIndexedOas_LoadIndexed6M_p0_: c1_Instruction.o;
+text: .text%__1cMArithmeticOpIis_equal6kMpnLInstruction__i_: c1_Instruction.o;
+text: .text%__1cDOp2Gas_Op26M_p0_: c1_Instruction.o;
+text: .text%__1cLInstructionMas_LoadField6M_pnJLoadField__: c1_GraphBuilder.o;
+text: .text%__1cQNullCheckVisitorRdo_NewObjectArray6MpnONewObjectArray__v_;
+text: .text%__1cDOp2Pinput_values_do6MpFppnLInstruction__v_v_: c1_GraphBuilder.o;
+text: .text%__1cQNullCheckVisitorKdo_ShiftOp6MpnHShiftOp__v_;
+text: .text%__1cHciKlassMaccess_flags6M_i_;
+text: .text%__1cILIR_ListPallocate_object6MnFRInfo_111ii1pnICodeStub__v_;
+text: .text%__1cLLIR_EmitterOmembar_release6M_v_;
+text: .text%__1cLLIR_EmitterGmembar6M_v_;
+text: .text%__1cIValueGenRdo_NewObjectArray6MpnONewObjectArray__v_;
+text: .text%__1cLLIR_EmitterQnew_object_array6MnFRInfo_pnHciKlass_pnLLIR_OprDesc_11111pnMCodeEmitInfo_7_v_;
+text: .text%__1cSNewObjectArrayStub2t6MnFRInfo_11pnMCodeEmitInfo__v_;
+text: .text%__1cPciObjArrayKlassEmake6FpnHciKlass__p0_;
+text: .text%__1cPciObjArrayKlassJmake_impl6FpnHciKlass__p0_;
+text: .text%__1cLLIR_EmitterOmembar_acquire6M_v_;
+text: .text%__1cIValueGenKdo_ShiftOp6MpnHShiftOp__v_;
+text: .text%__1cIValueGenPshiftCountRInfo6F_nFRInfo__;
+text: .text%__1cLLIR_EmitterIshift_op6MnJBytecodesECode_nFRInfo_pnLLIR_OprDesc_53_v_;
+text: .text%__1cILIR_ListKshift_left6MnFRInfo_i1_v_: c1_LIREmitter.o;
+text: .text%__1cILIR_ListKlogical_or6MnFRInfo_pnLLIR_OprDesc_1_v_: c1_LIREmitter.o;
+text: .text%__1cOLIR_OpAllocObjFvisit6MpnQLIR_OpVisitState__v_;
+text: .text%__1cSNewObjectArrayStubFvisit6MpnQLIR_OpVisitState__v_: c1_CodeStubs_x86.o;
+text: .text%__1cOLIR_OpAllocObjJemit_code6MpnVLIR_AbstractAssembler__v_;
+text: .text%__1cNLIR_OptimizerOemit_alloc_obj6MpnOLIR_OpAllocObj__v_;
+text: .text%__1cNLIR_AssemblerOemit_alloc_obj6MpnOLIR_OpAllocObj__v_;
+text: .text%__1cRC1_MacroAssemblerPallocate_object6MpnMRegisterImpl_22ii2rnFLabel__v_;
+text: .text%__1cNLIR_AssemblerOmembar_release6M_v_;
+text: .text%__1cNLIR_AssemblerGmembar6M_v_;
+text: .text%__1cSNewObjectArrayStubEinfo6kM_pnMCodeEmitInfo__: c1_CodeStubs_x86.o;
+text: .text%__1cNLIR_AssemblerOmembar_acquire6M_v_;
+text: .text%__1cEBaseHas_Base6M_p0_: c1_IR.o;
+text: .text%__1cNLIR_AssemblerOemit_osr_entry6MpnHIRScope_ipnFLabel_i_v_;
+text: .text%__1cSNewObjectArrayStubJemit_code6MpnNLIR_Assembler__v_;
+text: .text%__1cNinstanceKlassPadd_osr_nmethod6MpnHnmethod__v_;
+text: .text%__1cUGenericGrowableArrayLraw_at_grow6MipknEGrET__pv_;
+text: .text%__1cNSignatureInfoIdo_short6M_v_: bytecode.o;
+text: .text%jni_MonitorEnter: jni.o;
+text: .text%__1cSObjectSynchronizerJjni_enter6FnGHandle_pnGThread__v_;
+text: .text%jni_MonitorExit: jni.o;
+text: .text%__1cSObjectSynchronizerIjni_exit6FpnHoopDesc_pnGThread__v_;
+text: .text%jni_CallVoidMethod: jni.o;
+text: .text%__1cXJNI_ArgumentPusherVaArgHget_int6M_v_: jni.o;
+text: .text%jni_CallStaticBooleanMethodV: jni.o;
+text: .text%JVM_GetStackTraceDepth;
+text: .text%__1cTjava_lang_ThrowableVget_stack_trace_depth6FpnHoopDesc_pnGThread__i_;
+text: .text%__1cTjava_lang_ThrowableJbacktrace6FpnHoopDesc__2_;
+text: .text%JVM_GetStackTraceElement;
+text: .text%__1cTjava_lang_ThrowableXget_stack_trace_element6FpnHoopDesc_ipnGThread__2_;
+text: .text%__1cbBjava_lang_StackTraceElementGcreate6FnMmethodHandle_ipnGThread__pnHoopDesc__;
+text: .text%__1cbBjava_lang_StackTraceElementNset_className6FpnHoopDesc_2_v_;
+text: .text%__1cbBjava_lang_StackTraceElementOset_methodName6FpnHoopDesc_2_v_;
+text: .text%__1cbBjava_lang_StackTraceElementMset_fileName6FpnHoopDesc_2_v_;
+text: .text%__1cNmethodOopDescUline_number_from_bci6kMi_i_;
+text: .text%__1cbECompressedLineNumberReadStream2t6MpC_v_;
+text: .text%__1cbECompressedLineNumberReadStreamJread_pair6M_i_;
+text: .text%__1cUCompressedReadStreamIread_int6M_i_: methodOop.o;
+text: .text%__1cbBjava_lang_StackTraceElementOset_lineNumber6FpnHoopDesc_i_v_;
+text: .text%__1cFKlassNoop_is_method6kM_i_: typeArrayKlass.o;
+text: .text%__1cFKlassRoop_is_methodData6kM_i_: typeArrayKlass.o;
+text: .text%__1cIciObjectOis_null_object6kM_i_: ciObjectFactory.o;
+text: .text%__1cNObjectMonitorJnotifyAll6MpnGThread__v_;
+text: .text%__1cNObjectMonitorREntryQdDueue_insert6MpnMObjectWaiter_i_v_;
+text: .text%__1cNObjectMonitorbAEntryQdDueue_SelectSuccessor6M_pnMObjectWaiter__;
+text: .text%__1cLServiceUtilLvisible_oop6FpnHoopDesc__i_: objectMonitor_solaris.o;
+text: .text%__1cNObjectMonitorGEnterI6MpnGThread__v_;
+text: .text%JVM_EnableCompiler;
+text: .text%__1cCosHSolarisFEventEpark6Mx_i_: objectMonitor_solaris.o;
+text: .text%__1cJStubQdDueueKremove_all6M_v_;
+text: .text%__1cJStubQdDueueMremove_first6Mi_v_;
+text: .text%__1cJStubQdDueueMremove_first6M_v_;
+text: .text%__1cPICStubInterfaceIfinalize6MpnEStub__v_: icBuffer.o;
+text: .text%__1cGICStubIfinalize6M_v_;
+text: .text%__1cGICStubKcached_oop6kM_pnHoopDesc__;
+text: .text%__1cRInlineCacheBufferUic_buffer_cached_oop6FpC_pnHoopDesc__;
+text: .text%__1cKCompiledICOset_cached_oop6MpnHoopDesc__v_;
+text: .text%__1cOoop_RelocationSfix_oop_relocation6M_v_;
+text: .text%__1cGICStubLdestination6kM_pC_;
+text: .text%__1cRInlineCacheBufferVic_buffer_entry_point6FpC_1_;
+text: .text%__1cPICStubInterfaceEsize6kMpnEStub__i_: icBuffer.o;
+text: .text%__1cUSafepointSynchronizeDend6F_v_;
+text: .text%__1cCosbAmake_polling_page_readable6F_v_;
+text: .text%__1cTAbstractInterpreterRignore_safepoints6F_v_;
+text: .text%__1cGThreadQunboost_priority6Fp0_v_;
+text: .text%__1cUThreadSafepointStateHrestart6M_v_;
+text: .text%__1cORuntimeServiceUrecord_safepoint_end6F_v_;
+text: .text%__1cKJavaThreadbScheck_safepoint_and_suspend_for_native_trans6Fp0_v_;
+# Test LoadFrame
+text: .text%__1cNObjectMonitorGenter26MpnGThread__v_;
+text: .text%__1cICompilerPsupports_native6M_i_: c1_Compiler.o;
+text: .text%__1cLCompilationVcompile_native_method6MpnLCodeOffsets__i_;
+text: .text%__1cIciMethodMnative_entry6M_pC_;
+text: .text%__1cLCompilationUemit_code_for_native6MpCpnLCodeOffsets__v_;
+text: .text%__1cLCompilationXemit_code_prolog_native6MpnIFrameMap__v_;
+text: .text%__1cNLIR_AssemblerRemit_method_entry6MpnLLIR_Emitter_pnHIRScope__v_;
+text: .text%__1cOMacroAssemblerHfat_nop6M_v_;
+text: .text%__1cNLIR_AssemblerQemit_native_call6MpCpnMCodeEmitInfo__v_;
+text: .text%__1cMCodeEmitInfobGcreate_oop_map_for_own_signature6M_pnGOopMap__;
+text: .text%__1cNLIR_AssemblerXemit_native_method_exit6MpnMCodeEmitInfo__v_;
+text: .text%__1cNSignatureInfoHdo_char6M_v_: reflection.o;
+text: .text%__1cNSignatureInfoHdo_bool6M_v_: reflection.o;
+text: .text%jni_CallObjectMethodV: jni.o;
+text: .text%jni_SetObjectField: jni.o;
+text: .text%jni_IsInstanceOf: jni.o;
+text: .text%jni_GetStaticObjectField: jni.o;
+text: .text%__1cbCTwoGenerationCollectorPolicybMshould_try_older_generation_allocation6kMI_i_;
+text: .text%__1cQGenCollectedHeapSattempt_allocation6MIiii_pnIHeapWord__;
+text: .text%__1cQDefNewGenerationIallocate6MIii_pnIHeapWord__: defNewGeneration.o;
+text: .text%__1cKGenerationInext_gen6kM_p0_;
+text: .text%__1cKGenerationYallocation_limit_reached6MpnFSpace_pnIHeapWord_I_4_: tenuredGeneration.o;
+text: .text%__1cQDefNewGenerationTallocate_from_space6MI_pnIHeapWord__;
+text: .text%__1cPVM_GC_OperationNdoit_prologue6M_i_;
+text: .text%__1cPVM_GC_OperationZacquire_pending_list_lock6M_v_;
+text: .text%__1cQinstanceRefKlassZacquire_pending_list_lock6FpnJBasicLock__v_;
+text: .text%__1cXjava_lang_ref_ReferenceWpending_list_lock_addr6F_ppnHoopDesc__;
+text: .text%__1cPVM_GC_OperationQgc_count_changed6kM_i_;
+text: .text%__1cbAVM_GenCollectForAllocationEname6kM_pkc_: vm_operations.o;
+text: .text%__1cbAVM_GenCollectForAllocationEdoit6M_v_;
+text: .text%__1cNJvmtiGCMarker2t6Mi_v_;
+text: .text%__1cQGenCollectedHeapZsatisfy_failed_allocation6MIiipi_pnIHeapWord__;
+text: .text%__1cbCTwoGenerationCollectorPolicyZsatisfy_failed_allocation6MIiipi_pnIHeapWord__;
+text: .text%__1cQGenCollectedHeapNdo_collection6MiiIiiipi_v_;
+text: .text%__1cXTraceMemoryManagerStats2t6Mi_v_;
+text: .text%__1cNMemoryServiceIgc_begin6Fi_v_;
+text: .text%__1cPGCMemoryManagerIgc_begin6M_v_;
+text: .text%__1cKManagementJtimestamp6F_x_;
+text: .text%__1cKGCStatInfoMset_gc_usage6MinLMemoryUsage_i_v_;
+text: .text%__1cTContiguousSpacePoolQget_memory_usage6M_nLMemoryUsage__;
+text: .text%__1cTContiguousSpacePoolNused_in_bytes6M_I_: memoryPool.o;
+text: .text%__1cbBSurvivorContiguousSpacePoolQget_memory_usage6M_nLMemoryUsage__;
+text: .text%__1cbBSurvivorContiguousSpacePoolNused_in_bytes6M_I_: memoryPool.o;
+text: .text%__1cOGenerationPoolQget_memory_usage6M_nLMemoryUsage__;
+text: .text%__1cOGenerationPoolNused_in_bytes6M_I_: memoryPool.o;
+text: .text%__1cQGenCollectedHeapLgc_prologue6Mi_v_;
+text: .text%__1cNCollectedHeapbFaccumulate_statistics_all_tlabs6M_v_;
+text: .text%__1cWThreadLocalAllocBufferbFaccumulate_statistics_before_gc6F_v_;
+text: .text%__1cWThreadLocalAllocBufferVaccumulate_statistics6MIi_v_;
+text: .text%__1cPGlobalTLABStatsHpublish6M_v_;
+text: .text%__1cQGenCollectedHeapTensure_parseability6M_v_;
+text: .text%__1cNCollectedHeapTensure_parseability6M_v_;
+text: .text%__1cNCollectedHeapOfill_all_tlabs6M_v_;
+text: .text%__1cQGenCollectedHeapSgeneration_iterate6Mpn0AKGenClosure_i_v_;
+text: .text%__1cbCGenEnsureParseabilityClosureNdo_generation6MpnKGeneration__v_: genCollectedHeap.o;
+text: .text%__1cKGenerationTensure_parseability6M_v_: defNewGeneration.o;
+text: .text%__1cKGenerationTensure_parseability6M_v_: tenuredGeneration.o;
+text: .text%__1cKGenerationTensure_parseability6M_v_: compactingPermGenGen.o;
+text: .text%__1cSAllocationProfilerViterate_since_last_gc6F_v_;
+text: .text%__1cUGenGCPrologueClosureNdo_generation6MpnKGeneration__v_: genCollectedHeap.o;
+text: .text%__1cQDefNewGenerationLgc_prologue6Mi_v_: defNewGeneration.o;
+text: .text%__1cRTenuredGenerationLgc_prologue6Mi_v_;
+text: .text%__1cKGenerationLgc_prologue6Mi_v_: compactingPermGenGen.o;
+text: .text%__1cKGenerationOshould_collect6MiIii_i_: defNewGeneration.o;
+text: .text%__1cQDefNewGenerationKshort_name6kM_pkc_: defNewGeneration.o;
+text: .text%__1cKGenerationIcounters6M_pnRCollectorCounters__: defNewGeneration.o;
+text: .text%__1cQGenCollectedHeapKsave_marks6M_v_;
+text: .text%__1cQDefNewGenerationKsave_marks6M_v_;
+text: .text%__1cbCOneContigSpaceCardGenerationKsave_marks6M_v_;
+text: .text%__1cQDefNewGenerationHcollect6MiiIii_v_;
+text: .text%__1cQDefNewGenerationbAcollection_attempt_is_safe6M_i_;
+text: .text%__1cRTenuredGenerationZpromotion_attempt_is_safe6kMIi_i_;
+text: .text%__1cKGenerationYmax_contiguous_available6kM_I_;
+text: .text%__1cbCOneContigSpaceCardGenerationUcontiguous_available6kM_I_;
+text: .text%__1cQDefNewGenerationbIinit_assuming_no_promotion_failure6M_v_;
+text: .text%__1cQDefNewGenerationOIsAliveClosure2t6MpnKGeneration__v_;
+text: .text%__1cSScanWeakRefClosure2t6MpnQDefNewGeneration__v_;
+text: .text%__1cLCardTableRSbGprepare_for_younger_refs_iterate6Mi_v_;
+text: .text%__1cULRUCurrentHeapPolicy2t6M_v_;
+text: .text%__1cPCollectorPolicyPis_train_policy6M_i_: collectorPolicy.o;
+text: .text%__1cPFastScanClosure2t6MpnQDefNewGeneration_i_v_;
+text: .text%__1cQDefNewGenerationbCFastEvacuateFollowersClosure2t6MpnQGenCollectedHeap_ip0pnPFastScanClosure_6_v_;
+text: .text%__1cQGenCollectedHeapUprocess_strong_roots6Miiin0ATClassScanningOption_pnQOopsInGenClosure_3_v_;
+text: .text%__1cKSharedHeapbAchange_strong_roots_parity6M_v_;
+text: .text%__1cMSubTasksDonePis_task_claimed6Mi_i_;
+text: .text%__1cIUniverseHoops_do6FpnKOopClosure_i_v_;
+text: .text%__1cPFastScanClosureGdo_oop6MppnHoopDesc__v_: defNewGeneration.o;
+text: .text%__1cQDefNewGenerationWcopy_to_survivor_space6MpnHoopDesc_p2_2_;
+text: .text%__1cKJNIHandlesHoops_do6FpnKOopClosure__v_;
+text: .text%__1cOJNIHandleBlockHoops_do6MpnKOopClosure__v_;
+text: .text%__1cHThreadsHoops_do6FpnKOopClosure__v_;
+text: .text%__1cKJavaThreadHoops_do6MpnKOopClosure__v_;
+text: .text%__1cGThreadHoops_do6MpnKOopClosure__v_;
+text: .text%__1cKHandleAreaHoops_do6MpnKOopClosure__v_;
+text: .text%__1cNchunk_oops_do6FpnKOopClosure_pnFChunk_pc_I_: handles.o;
+text: .text%__1cQStackFrameStream2t6MpnKJavaThread_i_v_;
+text: .text%__1cFframeQoops_do_internal6MpnKOopClosure_pnLRegisterMap_i_v_;
+text: .text%__1cFframeToops_interpreted_do6MpnKOopClosure_pknLRegisterMap_i_v_;
+text: .text%__1cFframeVinterpreter_frame_bci6kM_i_;
+text: .text%__1cFframebDinterpreter_frame_monitor_end6kM_pnPBasicObjectLock__;
+text: .text%__1cFframebFinterpreter_frame_monitor_begin6kM_pnPBasicObjectLock__;
+text: .text%__1cRInterpreterOopMap2t6M_v_;
+text: .text%__1cRInterpreterOopMapKinitialize6M_v_;
+text: .text%__1cNmethodOopDescImask_for6MipnRInterpreterOopMap__v_;
+text: .text%__1cNinstanceKlassImask_for6MnMmethodHandle_ipnRInterpreterOopMap__v_;
+text: .text%__1cLOopMapCache2t6M_v_;
+text: .text%__1cLOopMapCacheGlookup6MnMmethodHandle_ipnRInterpreterOopMap__v_;
+text: .text%__1cLOopMapCacheIentry_at6kMi_pnQOopMapCacheEntry__;
+text: .text%__1cRInterpreterOopMapIis_empty6M_i_;
+text: .text%__1cQOopMapCacheEntryEfill6MnMmethodHandle_i_v_;
+text: .text%__1cQOopMapCacheEntryFflush6M_v_;
+text: .text%__1cQOopMapCacheEntryTdeallocate_bit_mask6M_v_;
+text: .text%__1cQOopMapCacheEntryPfill_for_native6M_v_;
+text: .text%__1cQOopMapCacheEntryRallocate_bit_mask6M_v_;
+text: .text%__1cTMaskFillerForNative2t6MnMmethodHandle_pIi_v_: oopMapCache.o;
+text: .text%__1cNFingerprinterLfingerprint6M_X_: oopMapCache.o;
+text: .text%__1cTMaskFillerForNativeLpass_object6M_v_: oopMapCache.o;
+text: .text%__1cRInterpreterOopMapNresource_copy6MpnQOopMapCacheEntry__v_;
+text: .text%__1cRInterpreterOopMapLiterate_oop6MpnNOffsetClosure__v_;
+text: .text%__1cXInterpreterFrameClosureJoffset_do6Mi_v_: frame.o;
+text: .text%__1cRInterpreterOopMap2T6M_v_;
+text: .text%__1cTOopMapForCacheEntry2t6MnMmethodHandle_ipnQOopMapCacheEntry__v_;
+text: .text%__1cTOopMapForCacheEntryLcompute_map6MpnGThread__v_;
+text: .text%__1cTOopMapForCacheEntryRpossible_gc_point6MpnOBytecodeStream__i_;
+text: .text%__1cTOopMapForCacheEntryOreport_results6kM_i_: oopMapCache.o;
+text: .text%__1cOGenerateOopMapVresult_for_basicblock6Mi_v_;
+text: .text%__1cTOopMapForCacheEntryZfill_stackmap_for_opcodes6MpnOBytecodeStream_pnNCellTypeState_4i_v_;
+text: .text%__1cQOopMapCacheEntryIset_mask6MpnNCellTypeState_2i_v_;
+text: .text%__1cFframeNoops_entry_do6MpnKOopClosure_pknLRegisterMap__v_;
+text: .text%__1cPJavaCallWrapperHoops_do6MpnKOopClosure__v_;
+text: .text%__1cXNativeSignatureIteratorHdo_long6M_v_: oopMapCache.o;
+text: .text%__1cTMaskFillerForNativeJpass_long6M_v_: oopMapCache.o;
+text: .text%__1cFframebHnext_monitor_in_interpreter_frame6kMpnPBasicObjectLock__2_;
+text: .text%__1cOGenerateOopMapPdo_monitorenter6Mi_v_;
+text: .text%__1cOGenerateOopMapXreplace_all_CTS_matches6MnNCellTypeState_1_v_;
+text: .text%__1cOGenerateOopMapMmonitor_push6MnNCellTypeState__v_;
+text: .text%__1cQComputeCallStackHdo_bool6M_v_: generateOopMap.o;
+text: .text%__1cQComputeCallStackHdo_long6M_v_: generateOopMap.o;
+text: .text%__1cOGenerateOopMapOdo_monitorexit6Mi_v_;
+text: .text%__1cOGenerateOopMapLmonitor_pop6M_nNCellTypeState__;
+text: .text%__1cRComputeEntryStackHdo_long6M_v_: generateOopMap.o;
+text: .text%__1cPBytecode_invokeIis_valid6kM_i_: frame.o;
+text: .text%__1cXNativeSignatureIteratorJdo_object6Mii_v_: oopMapCache.o;
+text: .text%__1cFframebDoops_interpreted_arguments_do6MnMsymbolHandle_ipnKOopClosure__v_;
+text: .text%__1cRArgumentOopFinderDset6MinJBasicType__v_: frame.o;
+text: .text%__1cIVMThreadHoops_do6MpnKOopClosure__v_;
+text: .text%__1cQVMOperationQdDueueHoops_do6MpnKOopClosure__v_;
+text: .text%__1cQVMOperationQdDueueNqueue_oops_do6MipnKOopClosure__v_;
+text: .text%__1cSObjectSynchronizerHoops_do6FpnKOopClosure__v_;
+text: .text%__1cMFlatProfilerHoops_do6FpnKOopClosure__v_;
+text: .text%__1cKManagementHoops_do6FpnKOopClosure__v_;
+text: .text%__1cNMemoryServiceHoops_do6FpnKOopClosure__v_;
+text: .text%__1cKMemoryPoolHoops_do6MpnKOopClosure__v_;
+text: .text%__1cNMemoryManagerHoops_do6MpnKOopClosure__v_;
+text: .text%__1cNThreadServiceHoops_do6FpnKOopClosure__v_;
+text: .text%__1cLJvmtiExportHoops_do6FpnKOopClosure__v_;
+text: .text%__1cXJvmtiCurrentBreakpointsHoops_do6FpnKOopClosure__v_;
+text: .text%__1cbGJvmtiVMObjectAllocEventCollectorXoops_do_for_all_threads6FpnKOopClosure__v_;
+text: .text%__1cQSystemDictionaryHoops_do6FpnKOopClosure__v_;
+text: .text%__1cQSystemDictionaryRpreloaded_oops_do6FpnKOopClosure__v_;
+text: .text%__1cKDictionaryHoops_do6MpnKOopClosure__v_;
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+text: .text%__1cLCardTableRSbDyounger_refs_in_space_iterate6MpnFSpace_pnQOopsInGenClosure__v_;
+text: .text%__1cPContiguousSpaceLnew_dcto_cl6MpnKOopClosure_nRCardTableModRefBSOPrecisionStyle_pnIHeapWord__pnVDirtyCardToOopClosure__;
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+text: .text%__1cRCardTableModRefBSWnon_clean_card_iterate6MpnFSpace_nJMemRegion_pnVDirtyCardToOopClosure_pnQMemRegionClosure_i_v_;
+text: .text%__1cRCardTableModRefBSbBnon_clean_card_iterate_work6MnJMemRegion_pnQMemRegionClosure_i_v_;
+text: .text%__1cJMemRegionMintersection6kMk0_0_;
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+text: .text%__1cYClearNoncleanCardWrapperKclear_card6MpW_i_: cardTableRS.o;
+text: .text%__1cVDirtyCardToOopClosureMdo_MemRegion6MnJMemRegion__v_;
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+text: .text%__1cbBBlockOffsetArrayContigSpaceSblock_start_unsafe6kMpkv_pnIHeapWord__;
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+text: .text%__1cFKlassSoop_oop_iterate_nv6MpnHoopDesc_pnQFilteringClosure__i_: typeArrayKlass.o;
+text: .text%__1cOtypeArrayKlassPoop_oop_iterate6MpnHoopDesc_pnKOopClosure__i_;
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+text: .text%__1cQconstMethodKlassPoop_oop_iterate6MpnHoopDesc_pnKOopClosure__i_;
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+text: .text%__1cRconstantPoolKlassRoop_oop_iterate_m6MpnHoopDesc_pnKOopClosure_nJMemRegion__i_;
+text: .text%__1cFKlassPoop_is_objArray6kM_i_: constMethodKlass.o;
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+text: .text%__1cRconstantPoolKlassPoop_oop_iterate6MpnHoopDesc_pnKOopClosure__i_;
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+text: .text%__1cWconstantPoolCacheKlassRoop_oop_iterate_m6MpnHoopDesc_pnKOopClosure_nJMemRegion__i_;
+text: .text%__1cWConstantPoolCacheEntryNoop_iterate_m6MpnKOopClosure_nJMemRegion__v_;
+text: .text%__1cFKlassPoop_is_objArray6kM_i_: cpCacheKlass.o;
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+text: .text%__1cSinstanceKlassKlassRoop_oop_iterate_m6MpnHoopDesc_pnKOopClosure_nJMemRegion__i_;
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+text: .text%__1cLklassVtableRoop_oop_iterate_m6MpnKOopClosure_nJMemRegion__v_;
+text: .text%__1cLklassItableRoop_oop_iterate_m6MpnKOopClosure_nJMemRegion__v_;
+text: .text%__1cKklassKlassRoop_oop_iterate_m6MpnHoopDesc_pnKOopClosure_nJMemRegion__i_;
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+text: .text%__1cKOopClosureIdo_oop_v6MppnHoopDesc__v_: space.o;
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+text: .text%__1cFKlassSoop_oop_iterate_nv6MpnHoopDesc_pnQFilteringClosure__i_: klassKlass.o;
+text: .text%__1cFKlassSoop_oop_iterate_nv6MpnHoopDesc_pnQFilteringClosure__i_: typeArrayKlassKlass.o;
+text: .text%__1cFKlassSoop_oop_iterate_nv6MpnHoopDesc_pnQFilteringClosure__i_: arrayKlassKlass.o;
+text: .text%__1cLCardTableRSUyounger_refs_iterate6MpnKGeneration_pnQOopsInGenClosure__v_;
+text: .text%__1cMSubTasksDoneTall_tasks_completed6M_v_;
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+text: .text%__1cQGenCollectedHeapbCoop_since_save_marks_iterate6MipnPFastScanClosure_2_v_;
+text: .text%__1cQDefNewGenerationbFoop_since_save_marks_iterate_nv6MpnPFastScanClosure__v_;
+text: .text%__1cPContiguousSpacebFoop_since_save_marks_iterate_nv6MpnPFastScanClosure__v_;
+text: .text%__1cNobjArrayKlassSoop_oop_iterate_nv6MpnHoopDesc_pnPFastScanClosure__i_;
+text: .text%__1cNinstanceKlassSoop_oop_iterate_nv6MpnHoopDesc_pnPFastScanClosure__i_;
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+text: .text%__1cQinstanceRefKlassSoop_oop_iterate_nv6MpnHoopDesc_pnPFastScanClosure__i_;
+text: .text%__1cXjava_lang_ref_ReferenceNreferent_addr6FpnHoopDesc__p2_;
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+text: .text%__1cXjava_lang_ref_ReferenceJnext_addr6FpnHoopDesc__p2_;
+text: .text%__1cXjava_lang_ref_ReferencePdiscovered_addr6FpnHoopDesc__p2_;
+text: .text%__1cSReferenceProcessorTget_discovered_list6MnNReferenceType__ppnHoopDesc__;
+text: .text%__1cKGenerationHpromote6MpnHoopDesc_Ip2_2_;
+text: .text%__1cbCOneContigSpaceCardGenerationIallocate6MIii_pnIHeapWord__: tenuredGeneration.o;
+text: .text%__1cbCOneContigSpaceCardGenerationbFoop_since_save_marks_iterate_nv6MpnPFastScanClosure__v_;
+text: .text%__1cQGenCollectedHeapbAno_allocs_since_save_marks6Mi_i_;
+text: .text%__1cQDefNewGenerationbAno_allocs_since_save_marks6M_i_;
+text: .text%__1cbCOneContigSpaceCardGenerationbAno_allocs_since_save_marks6M_i_;
+text: .text%__1cQDefNewGenerationUFastKeepAliveClosure2t6Mp0pnSScanWeakRefClosure__v_;
+text: .text%__1cQDefNewGenerationQKeepAliveClosure2t6MpnSScanWeakRefClosure__v_;
+text: .text%__1cbDReferenceProcessorInitializerIis_clean6kM_v_: concurrentMarkSweepGeneration.o;
+text: .text%__1cSReferenceProcessorbDprocess_discovered_references6M_v_;
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+text: .text%__1cSReferenceProcessorOprocess_phase16MppnHoopDesc_pnPReferencePolicy_pnRBoolObjectClosure_pnKOopClosure_pnLVoidClosure__v_;
+text: .text%__1cQDefNewGenerationOIsAliveClosureLdo_object_b6MpnHoopDesc__i_;
+text: .text%__1cULRUCurrentHeapPolicyWshould_clear_reference6MpnHoopDesc__i_;
+text: .text%__1cbBjava_lang_ref_SoftReferenceFclock6F_x_;
+text: .text%__1cbBjava_lang_ref_SoftReferenceJtimestamp6FpnHoopDesc__x_;
+text: .text%__1cXjava_lang_ref_ReferenceIset_next6FpnHoopDesc_2_v_;
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+text: .text%__1cSReferenceProcessorOprocess_phase36MppnHoopDesc_ipnRBoolObjectClosure_pnKOopClosure_pnLVoidClosure__v_;
+text: .text%__1cSReferenceProcessorQprocess_phaseJNI6M_v_;
+text: .text%__1cKJNIHandlesMweak_oops_do6FpnRBoolObjectClosure_pnKOopClosure__v_;
+text: .text%__1cOJNIHandleBlockMweak_oops_do6MpnRBoolObjectClosure_pnKOopClosure__v_;
+text: .text%__1cQDefNewGenerationLswap_spaces6M_v_;
+text: .text%__1cIageTablebAcompute_tenuring_threshold6MI_i_;
+text: .text%__1cKGenerationWupdate_time_of_last_gc6Mx_v_: defNewGeneration.o;
+text: .text%__1cSReferenceProcessorbDenqueue_discovered_references6M_i_;
+text: .text%__1cXjava_lang_ref_ReferenceRpending_list_addr6F_ppnHoopDesc__;
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+text: .text%__1cSReferenceProcessorbAenqueue_discovered_reflist6MpnHoopDesc_p2_v_;
+text: .text%__1cQGenCollectedHeapPupdate_gc_stats6Mii_v_: genCollectedHeap.o;
+text: .text%__1cKGenerationPupdate_gc_stats6Mii_v_: defNewGeneration.o;
+text: .text%__1cRTenuredGenerationPupdate_gc_stats6Mii_v_;
+text: .text%__1cVAdaptivePaddedAverageGsample6Mf_v_;
+text: .text%__1cKGenerationPupdate_gc_stats6Mii_v_: compactingPermGenGen.o;
+text: .text%__1cRTenuredGenerationOshould_collect6MiIii_i_;
+text: .text%__1cKGenerationPshould_allocate6MIii_i_: tenuredGeneration.o;
+text: .text%__1cbCOneContigSpaceCardGenerationEfree6kM_I_;
+text: .text%__1cQDefNewGenerationQcompute_new_size6M_v_;
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+text: .text%__1cRLowMemoryDetectorRdetect_low_memory6F_v_;
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+text: .text%__1cWThreadLocalAllocBufferQresize_all_tlabs6F_v_;
+text: .text%__1cWThreadLocalAllocBufferGresize6M_v_;
+text: .text%__1cUGenGCEpilogueClosureNdo_generation6MpnKGeneration__v_: genCollectedHeap.o;
+text: .text%__1cQDefNewGenerationLgc_epilogue6Mi_v_;
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+text: .text%__1cbCOneContigSpaceCardGenerationLgc_epilogue6Mi_v_;
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+text: .text%__1cXTraceMemoryManagerStats2T6M_v_;
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+text: .text%__1cPGCMemoryManagerGgc_end6M_v_;
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+text: .text%jni_SetIntArrayRegion: jni.o;
+text: .text%jni_PushLocalFrame: jni.o;
+text: .text%jni_PopLocalFrame: jni.o;
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+text: .text%__1cXArrayStoreExceptionStubEinfo6kM_pnMCodeEmitInfo__: c1_CodeStubs_x86.o;
+text: .text%__1cNLIR_AssemblerEleal6MpnLLIR_OprDesc_2_v_;
+text: .text%__1cNLIR_AssemblerGnegate6MpnLLIR_OprDesc_2_v_;
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+text: .text%__1cXArrayStoreExceptionStubJemit_code6MpnNLIR_Assembler__v_;
+text: .text%__1cIRuntime1Tresolve_static_call6FpnKJavaThread_pnHoopDesc__pC_;
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+text: .text%__1cSCompiledStaticCallIis_clean6kM_i_;
+text: .text%__1cSCompiledStaticCallDset6MrknOStaticCallInfo__v_;
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+text: .text%__1cHciKlassSsuper_check_offset6M_I_;
+text: .text%__1cIRuntime1Thandle_wrong_method6FpnKJavaThread_pnHoopDesc__pC_;
+text: .text%__1cNSharedRuntimeTreresolve_call_site6FpnKJavaThread_pnGThread__nMmethodHandle__;
+text: .text%__1cFframeRis_compiled_frame6kMpi_i_;
+text: .text%__1cHnmethodOis_java_method6kM_i_: nmethod.o;
+text: .text%__1cGEventsDlog6FpkcE_v_: sharedRuntime.o;
+text: .text%__1cJCodeCacheMfind_nmethod6Fpv_pnHnmethod__;
+text: .text%__1cNRelocIteratorEnext6M_i_: sharedRuntime.o;
+text: .text%__1cKCompiledICMset_to_clean6M_v_;
+text: .text%__1cKCompiledICMstub_address6kM_pC_;
+text: .text%__1cGICStubFclear6M_v_;
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+text: .text%__1cRInlineCacheBufferSic_destination_for6FpnKCompiledIC__pC_;
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+text: .text%__1cNinstanceKlassXmark_dependent_nmethods6MpnMklassOopDesc__i_;
+text: .text%jni_NewWeakGlobalRef: jni.o;
+text: .text%__1cKJNIHandlesQmake_weak_global6FnGHandle__pnI_jobject__;
+text: .text%__1cMLinkResolverbBlookup_method_in_interfaces6FrnMmethodHandle_nLKlassHandle_nMsymbolHandle_4pnGThread__v_;
+text: .text%jni_CallIntMethodV: jni.o;
+text: .text%Unsafe_GetObject;
+text: .text%jni_CallBooleanMethod: jni.o;
+text: .text%jni_CallVoidMethodV: jni.o;
+text: .text%JVM_GetClassDeclaredMethods;
+text: .text%JVM_InvokeMethod;
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+text: .text%__1cYjava_lang_reflect_MethodFclazz6FpnHoopDesc__2_;
+text: .text%__1cYjava_lang_reflect_MethodEslot6FpnHoopDesc__i_;
+text: .text%__1cYjava_lang_reflect_MethodPparameter_types6FpnHoopDesc__2_;
+text: .text%__1cYjava_lang_reflect_MethodLreturn_type6FpnHoopDesc__2_;
+text: .text%JVM_IsInterrupted;
+# Test LoadJFrame
+text: .text%__1cTresource_free_bytes6FpcI_v_;
+text: .text%__1cRComputeEntryStackHdo_bool6M_v_: generateOopMap.o;
+text: .text%__1cJFloatTypeDtag6kM_nIValueTag__: c1_ValueType.o;
+text: .text%__1cJFloatTypeEbase6kM_pnJValueType__: c1_ValueType.o;
+text: .text%__1cJFloatTypeMas_FloatType6M_p0_: c1_ValueType.o;
+text: .text%__1cIValueGenTdo_ArithmeticOp_FPU6MpnMArithmeticOp__v_;
+text: .text%__1cHLockRegIdo_float6Mi_v_: c1_RegAlloc.o;
+text: .text%__1cIRegAllocOset_locked_fpu6MipnLInstruction_i_v_;
+text: .text%__1cIValueGenNis_32bit_mode6M_i_;
+text: .text%__1cLGetRefCountIdo_float6Mi_v_: c1_RegAlloc.o;
+text: .text%__1cJFloatTypeEsize6kM_i_: c1_ValueType.o;
+text: .text%__1cHFreeRegIdo_float6Mi_v_: c1_RegAlloc.o;
+text: .text%__1cIRegAllocMset_free_fpu6Mi_v_;
+text: .text%__1cQChangeSpillCountIdo_float6Mi_v_: c1_RegAlloc.o;
+text: .text%__1cLLIR_EmitterRarithmetic_op_fpu6MnJBytecodesECode_pnLLIR_OprDesc_44i_v_;
+text: .text%__1cILIR_ListDmul6MpnLLIR_OprDesc_22_v_: c1_LIREmitter.o;
+text: .text%__1cIValueGenKround_item6MpnEItem__v_;
+text: .text%__1cLLIR_EmitterFround6MipnLLIR_OprDesc__v_;
+text: .text%__1cILIR_ListKround32bit6MnFRInfo_i_v_: c1_LIREmitter.o;
+text: .text%__1cIValueGenOspill_register6MnFRInfo__v_;
+text: .text%__1cIRegAllocTget_value_for_rinfo6kMnFRInfo__pnLInstruction__;
+text: .text%__1cLGetValueForGdo_cpu6Mi_v_: c1_RegAlloc.o;
+text: .text%__1cIValueGenKdivInRInfo6F_nFRInfo__;
+text: .text%__1cIValueGenLremOutRInfo6F_nFRInfo__;
+text: .text%__1cMArithmeticOpKlock_stack6kM_pnKValueStack__: c1_Instruction.o;
+text: .text%__1cLLIR_EmitterParithmetic_idiv6MnJBytecodesECode_pnLLIR_OprDesc_44nFRInfo_pnMCodeEmitInfo__v_;
+text: .text%__1cILIR_ListEirem6MnFRInfo_111pnMCodeEmitInfo__v_;
+text: .text%__1cHLIR_Op3Fvisit6MpnQLIR_OpVisitState__v_;
+text: .text%__1cHLIR_Op3Jemit_code6MpnVLIR_AbstractAssembler__v_;
+text: .text%__1cNLIR_OptimizerIemit_op36MpnHLIR_Op3__v_;
+text: .text%__1cNLIR_AssemblerIfpu_push6MnFRInfo__v_;
+text: .text%__1cIFrameMapLFpuStackSimEpush6Mi_v_;
+text: .text%__1cNLIR_AssemblerKfpu_on_tos6MnFRInfo__v_;
+text: .text%__1cIFrameMapLFpuStackSimPoffset_from_tos6kMi_i_;
+text: .text%__1cIintArrayIindex_of6kMki_i_: c1_FrameMap_x86.o;
+text: .text%__1cNLIR_AssemblerHfpu_pop6MnFRInfo__v_;
+text: .text%__1cIFrameMapLFpuStackSimDpop6Mi_i_;
+text: .text%__1cNLIR_AssemblerKround32_op6MpnLLIR_OprDesc_2_v_;
+text: .text%__1cJAssemblerGfist_s6MnHAddress__v_;
+text: .text%__1cNLIR_AssemblerJreset_FPU6M_v_;
+text: .text%__1cNLIR_AssemblerIemit_op36MpnHLIR_Op3__v_;
+text: .text%__1cNLIR_AssemblerParithmetic_idiv6MnILIR_Code_pnLLIR_OprDesc_333pnMCodeEmitInfo__v_;
+text: .text%__1cNLIR_AssemblerXadd_debug_info_for_div06MipnMCodeEmitInfo__v_;
+text: .text%__1cNDivByZeroStubEinfo6kM_pnMCodeEmitInfo__: c1_CodeStubs_x86.o;
+text: .text%__1cNDivByZeroStubJemit_code6MpnNLIR_Assembler__v_;
+text: .text%__1cIciObjectSis_obj_array_klass6M_i_: ciTypeArrayKlass.o;
+text: .text%__1cLInstructionOas_ArrayLength6M_pnLArrayLength__: c1_GraphBuilder.o;
+text: .text%__1cLInstructionKas_ShiftOp6M_pnHShiftOp__: c1_Instruction.o;
+text: .text%__1cILIR_ListLlogical_xor6MnFRInfo_pnLLIR_OprDesc_1_v_: c1_LIREmitter.o;
+text: .text%__1cILIR_ListUunsigned_shift_right6MnFRInfo_i1_v_: c1_LIREmitter.o;
+text: .text%__1cIRuntime1Ohandle_ic_miss6FpnKJavaThread_pnHoopDesc__pC_;
+text: .text%__1cNSharedRuntimeVhandle_ic_miss_helper6FpnKJavaThread_pnGThread__nMmethodHandle__;
+text: .text%__1cbEJvmtiDynamicCodeEventCollector2t6M_v_;
+text: .text%__1cKCompiledICOis_megamorphic6kM_i_;
+text: .text%__1cLVtableStubsOis_entry_point6FpC_i_;
+text: .text%__1cKCompiledICSset_to_megamorphic6MpnICallInfo_nJBytecodesECode_pnGThread__v_;
+text: .text%__1cLVtableStubsLcreate_stub6FiipnNmethodOopDesc__pC_;
+text: .text%__1cLVtableStubsGlookup6Fiii_pnKVtableStub__;
+text: .text%__1cLVtableStubsScreate_vtable_stub6Fii_pnKVtableStub__;
+text: .text%__1cKVtableStubSpd_code_size_limit6Fi_i_;
+text: .text%__1cKVtableStub2n6FIi_pv_;
+text: .text%__1cKVtableStubRpd_code_alignment6F_i_;
+text: .text%__1cLVtableStubsFenter6FiiipnKVtableStub__v_;
+text: .text%__1cGEventsDlog6FpkcE_v_: compiledIC.o;
+text: .text%__1cbEJvmtiDynamicCodeEventCollector2T6M_v_;
+text: .text%Unsafe_EnsureClassInitialized;
+text: .text%Unsafe_StaticFieldOffset;
+text: .text%Unsafe_StaticFieldBaseFromField;
+text: .text%Unsafe_GetIntVolatile;
+text: .text%__1cUBytecode_tableswitchGlength6M_i_: generateOopMap.o;
+text: .text%__1cUBytecode_tableswitchOdest_offset_at6kMi_i_;
+text: .text%__1cUBytecode_tableswitchGlength6M_i_: c1_GraphBuilder.o;
+text: .text%__1cLInstructionKas_ShiftOp6M_pnHShiftOp__: c1_GraphBuilder.o;
+text: .text%__1cMGraphBuilderMtable_switch6M_v_;
+text: .text%__1cLTableSwitchFvisit6MpnSInstructionVisitor__v_: c1_GraphBuilder.o;
+text: .text%__1cNCanonicalizerOdo_TableSwitch6MpnLTableSwitch__v_;
+text: .text%__1cLInstructionJas_Return6M_pnGReturn__: c1_GraphBuilder.o;
+text: .text%__1cGSwitchPinput_values_do6MpFppnLInstruction__v_v_: c1_GraphBuilder.o;
+text: .text%__1cQNullCheckVisitorOdo_TableSwitch6MpnLTableSwitch__v_;
+text: .text%__1cIValueGenOdo_TableSwitch6MpnLTableSwitch__v_;
+text: .text%__1cIValueGenVsetup_phis_for_switch6MpnEItem_pnKValueStack__v_;
+text: .text%__1cLLIR_EmitterOtableswitch_op6MpnLLIR_OprDesc_ipnKBlockBegin__v_;
+text: .text%__1cWstatic_call_RelocationLstatic_stub6M_pC_;
+text: .text%__1cSCompiledStaticCallMset_to_clean6M_v_;
+# Test JHello
+text: .text%__1cYjava_lang_reflect_MethodNset_signature6FpnHoopDesc_2_v_;
+text: .text%JVM_InitializeSocketLibrary;
+text: .text%__1cDhpiZinitialize_socket_library6F_i_;
+text: .text%JVM_Socket;
+text: .text%Unsafe_PageSize;
+text: .text%__1cNFingerprinterHdo_byte6M_v_: dump.o;
+text: .text%__1cXNativeSignatureIteratorHdo_byte6M_v_: interpreterRuntime.o;
+text: .text%Unsafe_SetMemory;
+text: .text%__1cECopyQpd_fill_to_words6FpnIHeapWord_II_v_: unsafe.o;
+text: .text%__1cNSharedRuntimeElrem6Fxx_x_;
+text: .text%Unsafe_DefineClass1;
+text: .text%__1cSUnsafe_DefineClass6FpnHJNIEnv__pnI_jstring_pnL_jbyteArray_iipnI_jobject_7_pnH_jclass__: unsafe.o;
+text: .text%JVM_DefineClass;
+text: .text%__1cPClassFileParserXverify_unqualified_name6MpcIi_i_;
+text: .text%__1cVLoaderConstraintTableYextend_loader_constraint6MpnVLoaderConstraintEntry_nGHandle_pnMklassOopDesc__v_;
+text: .text%__1cVLoaderConstraintTablebHensure_loader_constraint_capacity6MpnVLoaderConstraintEntry_i_v_;
+text: .text%__1cIciObjectIis_klass6M_i_: ciInstance.o;
+text: .text%__1cQInstanceConstantIencoding6kM_pnI_jobject__;
+text: .text%__1cLInstructionOas_ArrayLength6M_pnLArrayLength__: c1_Instruction.o;
+text: .text%__1cILIR_ListQunwind_exception6MnFRInfo_1pnMCodeEmitInfo__v_: c1_CodeGenerator.o;
+text: .text%__1cIRuntime1Tprimitive_arraycopy6FpnIHeapWord_2i_v_;
+text: .text%__1cRComputeEntryStackHdo_char6M_v_: generateOopMap.o;
+text: .text%jni_NewDirectByteBuffer;
+text: .text%__1cbDinitializeDirectBufferSupport6FpnHJNIEnv___i_: jni.o;
+text: .text%lookupDirectBufferClasses: jni.o;
+text: .text%__1cJlookupOne6FpnHJNIEnv__pkcpnGThread__pnH_jclass__: jni.o;
+text: .text%__1cHJNIEnv_JNewObject6MpnH_jclass_pnK_jmethodID_E_pnI_jobject__: jni.o;
+text: .text%jni_GetDoubleArrayRegion: jni.o;
+text: .text%__1cNSignatureInfoJdo_double6M_v_: bytecode.o;
+text: .text%__1cXJNI_ArgumentPusherVaArgJget_float6M_v_: jni.o;
+text: .text%__1cQComputeCallStackHdo_byte6M_v_: generateOopMap.o;
+text: .text%__1cFKlassQup_cast_abstract6M_p0_;
+text: .text%__1cRComputeEntryStackHdo_byte6M_v_: generateOopMap.o;
+text: .text%__1cNSharedRuntimeDd2i6Fd_i_;
+text: .text%__1cSInterpreterRuntimeWslow_signature_handler6FpnKJavaThread_pnNmethodOopDesc_pi5_pC_;
+text: .text%__1cXNativeSignatureIteratorJdo_object6Mii_v_: interpreterRT_x86.o;
+text: .text%__1cUSlowSignatureHandlerLpass_object6M_v_: interpreterRT_x86.o;
+text: .text%__1cXNativeSignatureIteratorIdo_array6Mii_v_: interpreterRT_x86.o;
+text: .text%__1cXNativeSignatureIteratorGdo_int6M_v_: interpreterRT_x86.o;
+text: .text%__1cUSlowSignatureHandlerIpass_int6M_v_: interpreterRT_x86.o;
+text: .text%__1cXNativeSignatureIteratorHdo_bool6M_v_: interpreterRT_x86.o;
+text: .text%jni_GetFloatArrayRegion: jni.o;
+text: .text%jni_GetCharArrayRegion: jni.o;
+text: .text%jni_SetFloatField: jni.o;
+text: .text%jni_NewFloatArray: jni.o;
+text: .text%jni_SetFloatArrayRegion: jni.o;
+# SwingSet
+text: .text%JVM_GetFieldIxModifiers;
+text: .text%JVM_GetCPFieldClassNameUTF;
+text: .text%JVM_GetCPFieldModifiers;
+text: .text%__1cPClassFileParserUverify_constantvalue6MiinSconstantPoolHandle_pnGThread__v_;
+text: .text%__1cXjava_lang_ref_ReferenceOset_discovered6FpnHoopDesc_2_v_;
+text: .text%__1cMStoreIndexedPother_values_do6MpFppnLInstruction__v_v_: c1_GraphBuilder.o;
+text: .text%JVM_MonitorNotify;
+text: .text%__1cSObjectSynchronizerGnotify6FnGHandle_pnGThread__v_;
+text: .text%__1cKValueStackElock6MpnHIRScope_pnLInstruction__i_;
+text: .text%__1cKValueStackGunlock6M_i_;
+text: .text%__1cLLIR_EmitterVmonitorenter_at_entry6MnFRInfo_pnMCodeEmitInfo__v_;
+text: .text%__1cLLIR_EmitterNmonitor_enter6MnFRInfo_111ipnMCodeEmitInfo_3_v_;
+text: .text%__1cQMonitorEnterStub2t6MnFRInfo_1pnMCodeEmitInfo__v_;
+text: .text%__1cILIR_ListbAload_stack_address_monitor6MinFRInfo__v_: c1_LIREmitter.o;
+text: .text%__1cILIR_ListLlock_object6MnFRInfo_111pnICodeStub_pnMCodeEmitInfo__v_;
+text: .text%__1cIValueGenNsyncTempRInfo6F_nFRInfo__;
+text: .text%__1cLLIR_EmitterQreturn_op_prolog6Mi_v_;
+text: .text%__1cLLIR_EmitterMmonitor_exit6MnFRInfo_11i_v_;
+text: .text%__1cILIR_ListNunlock_object6MnFRInfo_11pnICodeStub__v_;
+text: .text%__1cKLIR_OpLockFvisit6MpnQLIR_OpVisitState__v_;
+text: .text%__1cQMonitorEnterStubFvisit6MpnQLIR_OpVisitState__v_: c1_CodeStubs_x86.o;
+text: .text%__1cRMonitorAccessStubFvisit6MpnQLIR_OpVisitState__v_: c1_CodeStubs_x86.o;
+text: .text%__1cKLIR_OpLockJemit_code6MpnVLIR_AbstractAssembler__v_;
+text: .text%__1cNLIR_OptimizerJemit_lock6MpnKLIR_OpLock__v_;
+text: .text%__1cNLIR_AssemblerPmonitor_address6MinFRInfo__v_;
+text: .text%__1cIFrameMapbEaddress_for_monitor_lock_index6kMi_nHAddress__;
+text: .text%__1cIFrameMapbAfp_offset_for_monitor_lock6kMi_i_;
+text: .text%__1cNLIR_AssemblerJemit_lock6MpnKLIR_OpLock__v_;
+text: .text%__1cRC1_MacroAssemblerLlock_object6MpnMRegisterImpl_22rnFLabel__v_;
+text: .text%__1cQMonitorEnterStubEinfo6kM_pnMCodeEmitInfo__: c1_CodeStubs_x86.o;
+text: .text%__1cIFrameMapWmonitor_object_regname6kMi_nHOptoRegEName__;
+text: .text%__1cIFrameMapbCfp_offset_for_monitor_object6kMi_i_;
+text: .text%__1cMCodeEmitInfobHlocation_for_monitor_object_index6Mi_nILocation__;
+text: .text%__1cIFrameMapbHlocation_for_monitor_object_index6kMipnILocation__i_;
+text: .text%__1cMCodeEmitInfobFlocation_for_monitor_lock_index6Mi_nILocation__;
+text: .text%__1cIFrameMapbFlocation_for_monitor_lock_index6kMipnILocation__i_;
+text: .text%__1cMMonitorValue2t6MpnKScopeValue_nILocation__v_;
+text: .text%__1cMMonitorValueIwrite_on6MpnUDebugInfoWriteStream__v_;
+text: .text%__1cRC1_MacroAssemblerNunlock_object6MpnMRegisterImpl_22rnFLabel__v_;
+text: .text%__1cPMonitorExitStubMis_call_stub6kM_i_: c1_CodeStubs_x86.o;
+text: .text%__1cQMonitorEnterStubJemit_code6MpnNLIR_Assembler__v_;
+text: .text%__1cNLIR_AssemblerRload_receiver_reg6MpnMRegisterImpl__v_;
+text: .text%__1cNLIR_AssemblerLmonitorexit6MnFRInfo_1pnMRegisterImpl_i3_v_;
+text: .text%__1cPMonitorExitStubJemit_code6MpnNLIR_Assembler__v_;
+text: .text%jni_NewIntArray: jni.o;
+text: .text%__1cNCollectedHeapYlarge_typearray_allocate6FnLKlassHandle_iipnGThread__pnHoopDesc__: typeArrayKlass.o;
+text: .text%__1cFKlassUoop_oop_iterate_nv_m6MpnHoopDesc_pnQFilteringClosure_nJMemRegion__i_: objArrayKlassKlass.o;
+text: .text%__1cSobjArrayKlassKlassRoop_oop_iterate_m6MpnHoopDesc_pnKOopClosure_nJMemRegion__i_;
+text: .text%__1cQinstanceRefKlassSoop_oop_iterate_nv6MpnHoopDesc_pnQFilteringClosure__i_;
+text: .text%__1cRTenuredGenerationKshort_name6kM_pkc_: tenuredGeneration.o;
+text: .text%__1cKGenerationIcounters6M_pnRCollectorCounters__: tenuredGeneration.o;
+text: .text%__1cRTenuredGenerationHcollect6MiiIii_v_;
+text: .text%__1cRTenuredGenerationbJretire_alloc_buffers_before_full_gc6M_v_;
+text: .text%__1cbCOneContigSpaceCardGenerationHcollect6MiiIii_v_;
+text: .text%__1cMGenMarkSweepTinvoke_at_safepoint6FipnSReferenceProcessor_i_v_;
+text: .text%__1cJCodeCacheLgc_prologue6F_v_;
+text: .text%__1cHThreadsLgc_prologue6F_v_;
+text: .text%__1cKJavaThreadLgc_prologue6M_v_;
+text: .text%__1cKJavaThreadJframes_do6MpFpnFframe_pknLRegisterMap__v_v_;
+text: .text%__1cRframe_gc_prologue6FpnFframe_pknLRegisterMap__v_: thread.o;
+text: .text%__1cFframeLgc_prologue6M_v_;
+text: .text%__1cQGenCollectedHeapRsave_used_regions6Mii_v_;
+text: .text%__1cKGenerationQsave_used_region6M_v_: tenuredGeneration.o;
+text: .text%__1cbCOneContigSpaceCardGenerationLused_region6kM_nJMemRegion__;
+text: .text%__1cPContiguousSpaceLused_region6kM_nJMemRegion__: space.o;
+text: .text%__1cKGenerationQsave_used_region6M_v_: defNewGeneration.o;
+text: .text%__1cKGenerationLused_region6kM_nJMemRegion__: defNewGeneration.o;
+text: .text%__1cKGenerationQsave_used_region6M_v_: compactingPermGenGen.o;
+text: .text%__1cMGenMarkSweepPallocate_stacks6F_v_;
+text: .text%__1cQGenCollectedHeapOgather_scratch6MpnKGeneration_I_pnMScratchBlock__;
+text: .text%__1cQDefNewGenerationScontribute_scratch6MrpnMScratchBlock_pnKGeneration_I_v_;
+text: .text%__1cKGenerationScontribute_scratch6MrpnMScratchBlock_p0I_v_: tenuredGeneration.o;
+text: .text%__1cRsort_scratch_list6FrpnMScratchBlock__v_: genCollectedHeap.o;
+text: .text%__1cVremoveSmallestScratch6FppnMScratchBlock__1_: genCollectedHeap.o;
+text: .text%__1cMGenMarkSweepRmark_sweep_phase16Firii_v_;
+text: .text%__1cJEventMark2t6MpkcE_v_: genMarkSweep.o;
+text: .text%__1cJMarkSweepRFollowRootClosureGdo_oop6MppnHoopDesc__v_: markSweep.o;
+text: .text%__1cJMarkSweepLfollow_root6FppnHoopDesc__v_;
+text: .text%__1cParrayKlassKlassToop_follow_contents6MpnHoopDesc__v_;
+text: .text%__1cLklassVtableToop_follow_contents6M_v_;
+text: .text%__1cJMarkSweepO_mark_and_push6FppnHoopDesc__v_;
+text: .text%__1cKklassKlassToop_follow_contents6MpnHoopDesc__v_;
+text: .text%__1cJMarkSweepXrevisit_weak_klass_link6FpnFKlass__v_;
+text: .text%__1cJMarkSweepMfollow_stack6F_v_;
+text: .text%__1cNinstanceKlassToop_follow_contents6MpnHoopDesc__v_;
+text: .text%__1cSinstanceKlassKlassToop_follow_contents6MpnHoopDesc__v_;
+text: .text%__1cNinstanceKlassUfollow_static_fields6M_v_;
+text: .text%__1cLklassItableToop_follow_contents6M_v_;
+text: .text%__1cJMarkSweepNpreserve_mark6FpnHoopDesc_pnLmarkOopDesc__v_;
+text: .text%__1cLsymbolKlassToop_follow_contents6MpnHoopDesc__v_;
+text: .text%__1cOtypeArrayKlassToop_follow_contents6MpnHoopDesc__v_;
+text: .text%__1cMjniIdMapBaseHoops_do6MpnKOopClosure__v_;
+text: .text%__1cIjniIdMapHoops_do6MpnKOopClosure__v_;
+text: .text%__1cJMarkSweepSMarkAndPushClosureGdo_oop6MppnHoopDesc__v_: markSweep.o;
+text: .text%__1cNobjArrayKlassToop_follow_contents6MpnHoopDesc__v_;
+text: .text%__1cJMarkSweepPmark_and_follow6FppnHoopDesc__v_;
+text: .text%__1cSobjArrayKlassKlassToop_follow_contents6MpnHoopDesc__v_;
+text: .text%__1cRconstantPoolKlassToop_follow_contents6MpnHoopDesc__v_;
+text: .text%__1cWconstantPoolCacheKlassToop_follow_contents6MpnHoopDesc__v_;
+text: .text%__1cWConstantPoolCacheEntryPfollow_contents6M_v_;
+text: .text%__1cLmethodKlassToop_follow_contents6MpnHoopDesc__v_;
+text: .text%__1cQconstMethodKlassToop_follow_contents6MpnHoopDesc__v_;
+text: .text%__1cQinstanceRefKlassToop_follow_contents6MpnHoopDesc__v_;
+text: .text%__1cFJNIidHoops_do6MpnKOopClosure__v_;
+text: .text%__1cQSystemDictionaryValways_strong_oops_do6FpnKOopClosure__v_;
+text: .text%__1cQSystemDictionaryYalways_strong_classes_do6FpnKOopClosure__v_;
+text: .text%__1cKDictionaryYalways_strong_classes_do6MpnKOopClosure__v_;
+text: .text%__1cQSystemDictionaryPplaceholders_do6FpnKOopClosure__v_;
+text: .text%__1cVLoaderConstraintTableYalways_strong_classes_do6MpnKOopClosure__v_;
+text: .text%__1cJvmSymbolsHoops_do6FpnKOopClosure_i_v_;
+text: .text%__1cJMarkSweepOIsAliveClosureLdo_object_b6MpnHoopDesc__i_: markSweep.o;
+text: .text%__1cJMarkSweepQKeepAliveClosureGdo_oop6MppnHoopDesc__v_;
+text: .text%__1cJMarkSweepSFollowStackClosureHdo_void6M_v_: markSweep.o;
+text: .text%__1cQSystemDictionaryMdo_unloading6FpnRBoolObjectClosure_pnKOopClosure__i_;
+text: .text%__1cKDictionaryMdo_unloading6MpnRBoolObjectClosure_pnKOopClosure__i_;
+text: .text%__1cVLoaderConstraintTableYpurge_loader_constraints6MpnRBoolObjectClosure__v_;
+text: .text%__1cJCodeCacheMdo_unloading6FpnRBoolObjectClosure_pnKOopClosure_iri_v_;
+text: .text%__1cJCodeCacheFfirst6F_pnICodeBlob__;
+text: .text%__1cICodeHeapLfirst_block6kM_pnJHeapBlock__;
+text: .text%__1cICodeHeapJnext_free6kMpnJHeapBlock__pv_;
+text: .text%__1cJCodeCacheFalive6FpnICodeBlob__2_;
+text: .text%__1cKBufferBlobIis_alive6kM_i_: codeBlob.o;
+text: .text%__1cKBufferBlobbIfollow_roots_or_mark_for_unloading6MpnRBoolObjectClosure_pnKOopClosure_iri_v_: codeBlob.o;
+text: .text%__1cJCodeCacheEnext6FpnICodeBlob__2_;
+text: .text%__1cICodeHeapLblock_start6kMpv_pnJHeapBlock__;
+text: .text%__1cICodeHeapKnext_block6kMpnJHeapBlock__2_;
+text: .text%__1cNSingletonBlobIis_alive6kM_i_: codeBlob.o;
+text: .text%__1cNSingletonBlobbIfollow_roots_or_mark_for_unloading6MpnRBoolObjectClosure_pnKOopClosure_iri_v_: codeBlob.o;
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diff --git a/hotspot/make/solaris/makefiles/reorder_COMPILER1_i486 b/hotspot/make/solaris/makefiles/reorder_COMPILER1_i486
index bab5b288d70..caf8c0298ed 100644
--- a/hotspot/make/solaris/makefiles/reorder_COMPILER1_i486
+++ b/hotspot/make/solaris/makefiles/reorder_COMPILER1_i486
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text: .text%__1cQAgentLibraryList2t6M_v_: arguments.o;
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text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_CacheLocals.o;
text: .text%__1cFRInfo2t6M_v_: c1_CacheLocals.o;
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text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_Canonicalizer.o;
text: .text%__1cFRInfo2t6M_v_: c1_Canonicalizer.o;
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text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_Compilation.o;
text: .text%__1cFRInfo2t6M_v_: c1_Compilation.o;
text: .text%__1cMelapsedTimer2t6M_v_: c1_Compilation.o;
@@ -29,9 +29,9 @@ text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_Compiler.o;
text: .text%__1cFRInfo2t6M_v_: c1_Compiler.o;
text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_FrameMap.o;
text: .text%__1cFRInfo2t6M_v_: c1_FrameMap.o;
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-text: .text%__1cKc1_RegMask2t6M_v_: c1_FrameMap_i486.o;
+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_FrameMap_x86.o;
+text: .text%__1cFRInfo2t6M_v_: c1_FrameMap_x86.o;
+text: .text%__1cKc1_RegMask2t6M_v_: c1_FrameMap_x86.o;
text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_GraphBuilder.o;
text: .text%__1cFRInfo2t6M_v_: c1_GraphBuilder.o;
text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_IR.o;
@@ -43,41 +43,41 @@ text: .text%__1cFRInfo2t6M_v_: c1_InstructionPrinter.o;
text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_Items.o;
text: .text%__1cFRInfo2t6M_v_: c1_Items.o;
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text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_LIR.o;
text: .text%__1cFRInfo2t6M_v_: c1_LIR.o;
text: .text%__1cLLIR_OprFactHillegal6F_pnLLIR_OprDesc__: c1_LIR.o;
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+text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: c1_LIRAssembler_x86.o;
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text: .text%__1cTAssertIsPermClosure2t6M_v_: genCollectedHeap.o;
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text: .text%__1cFRInfo2t6M_v_: java.o;
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text: .text%__1cMarrayOopDescLheader_size6FnJBasicType__i_: parGCAllocBuffer.o;
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text: .text%__1cJTimeStamp2t6M_v_: runtimeService.o;
text: .text%__1cU__STATIC_CONSTRUCTOR6F_v_: safepoint.o;
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text: .text%__1cSThreadLocalStoragebCgenerate_code_for_get_thread6F_v_;
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+text: .text%__1cYVM_Version_StubGeneratorTgenerate_getPsrInfo6M_pC_: vm_version_x86.o;
text: .text%__1cMStubCodeMark2t6MpnRStubCodeGenerator_pkc4_v_;
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text: .text%__1cJAssemblerFpushl6MpnMRegisterImpl__v_;
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text: .text%__1cCosMsupports_sse6F_i_;
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text: .text%__1cWStubGenerator_generate6FpnKCodeBuffer_i_v_;
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text: .text%__1cOMacroAssemblerFenter6M_v_;
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text: .text%__1cJAssemblerFtestl6MpnMRegisterImpl_2_v_;
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text: .text%__1cJAssemblerGfstp_d6MnHAddress__v_;
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+text: .text%__1cNStubGeneratorUgenerate_atomic_xchg6M_pC_: stubGenerator_x86.o;
text: .text%__1cJAssemblerExchg6MpnMRegisterImpl_nHAddress__v_;
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+text: .text%__1cNStubGeneratorUgenerate_d2i_wrapper6MpC_1_: stubGenerator_x86.o;
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text: .text%__1cJAssemblerGfrstor6MnHAddress__v_;
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+text: .text%__1cNStubGeneratorUcreate_control_words6M_v_: stubGenerator_x86.o;
text: .text%__1cJTraceTime2T6M_v_;
text: .text%__1cNcarSpace_init6F_v_;
text: .text%__1cICarSpaceEinit6F_v_;
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+text: .text%__1cOMacroAssemblerWbang_stack_with_offset6Mi_v_: interp_masm_x86.o;
text: .text%__1cZInterpreterMacroAssemblerTnotify_method_entry6M_v_;
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text: .text%__1cJAssemblerEnegl6MpnMRegisterImpl__v_;
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text: .text%__1cUInterpreterGeneratorUgenerate_empty_entry6M_pC_;
text: .text%__1cUInterpreterGeneratorXgenerate_accessor_entry6M_pC_;
text: .text%__1cJAssemblerEshrl6MpnMRegisterImpl_i_v_;
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+text: .text%__1cLlog2_intptr6Fi_i_: interpreter_x86.o;
text: .text%__1cOMacroAssemblerQload_signed_byte6MpnMRegisterImpl_nHAddress__i_;
text: .text%__1cJAssemblerGmovsxb6MpnMRegisterImpl_nHAddress__v_;
text: .text%__1cOMacroAssemblerQload_signed_word6MpnMRegisterImpl_nHAddress__i_;
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+text: .text%__1cFj_not6FnNTemplateTableJCondition__nJAssemblerJCondition__: templateTable_x86.o;
text: .text%__1cNTemplateTableGbranch6Fii_v_;
text: .text%__1cZInterpreterMacroAssemblerUprofile_taken_branch6MpnMRegisterImpl_2_v_;
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+text: .text%__1cLLIR_OprDescIsize_for6FnJBasicType__n0AHOprSize__: c1_FrameMap_x86.o;
text: .text%__1cNc1_AllocTableLinit_tables6F_v_;
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+text: .text%__1cTsave_live_registers6FpnOMacroAssembler_i_pnGOopMap__: c1_Runtime1_x86.o;
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text: .text%__1cGOopMapQset_callee_saved6MnHOptoRegEName_ii2_v_;
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text: .text%__1cOMacroAssemblerLtlab_refill6MrnFLabel_22_v_;
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+text: .text%__1cLlog2_intptr6Fi_i_: assembler_x86.o;
text: .text%__1cOMacroAssemblerNeden_allocate6MpnMRegisterImpl_2i2rnFLabel__v_;
text: .text%__1cOMacroAssemblerLverify_tlab6M_v_;
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+text: .text%__1cLlog2_intptr6Fi_i_: c1_Runtime1_x86.o;
text: .text%__1cOMacroAssemblerNtlab_allocate6MpnMRegisterImpl_2i22rnFLabel__v_;
text: .text%__1cRC1_MacroAssemblerRinitialize_object6MpnMRegisterImpl_22i22_v_;
text: .text%__1cRC1_MacroAssemblerRinitialize_header6MpnMRegisterImpl_22_v_;
@@ -1581,7 +1581,7 @@ text: .text%__1cIiEntries2t6Miiii_v_;
text: .text%__1cRNativeGeneralJumpQjump_destination6kM_pC_;
text: .text%__1cJAssemblerOlocate_operand6FpCn0AMWhichOperand__1_;
text: .text%__1cIRuntime1Rgenerate_patching6FpnNStubAssembler_pC_pnJOopMapSet__;
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+text: .text%__1cWrestore_live_registers6FpnOMacroAssembler__v_: c1_Runtime1_x86.o;
text: .text%__1cNSafepointBlobGcreate6FpnKCodeBuffer_pnJOopMapSet_i_p0_;
text: .text%__1cNSafepointBlob2n6FII_pv_;
text: .text%__1cNSafepointBlob2t6MpnKCodeBuffer_ipnJOopMapSet_i_v_;
@@ -1778,8 +1778,8 @@ text: .text%__1cYsun_reflect_ConstantPoolPcompute_offsets6F_v_;
text: .text%__1cZsun_misc_AtomicLongCSImplPcompute_offsets6F_v_;
text: .text%__1cSstubRoutines_init26F_v_;
text: .text%__1cMStubRoutinesLinitialize26F_v_;
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-text: .text%__1cNStubGeneratorTgenerate_verify_oop6M_pC_: stubGenerator_i486.o;
+text: .text%__1cNStubGeneratorYgenerate_throw_exception6MpkcpCi_3_: stubGenerator_x86.o;
+text: .text%__1cNStubGeneratorTgenerate_verify_oop6M_pC_: stubGenerator_x86.o;
text: .text%__1cJAssemblerEincl6MnHAddress__v_;
text: .text%__1cHThreadsDadd6FpnKJavaThread_i_v_;
text: .text%__1cNThreadServiceKadd_thread6FpnKJavaThread_i_v_;
@@ -3074,11 +3074,11 @@ text: .text%__1cEItemRget_jint_constant6kM_i_;
text: .text%__1cLLIR_EmitterRarithmetic_op_int6MnJBytecodesECode_pnLLIR_OprDesc_44nFRInfo__v_;
text: .text%__1cLLIR_EmitterNarithmetic_op6MnJBytecodesECode_pnLLIR_OprDesc_44inFRInfo_pnMCodeEmitInfo__v_;
text: .text%__1cLLIR_EmitterYstrength_reduce_multiply6MpnLLIR_OprDesc_i22_i_;
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text: .text%__1cILIR_ListKshift_left6MpnLLIR_OprDesc_222_v_;
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text: .text%__1cIValueGenWcan_inline_as_constant6MpnEItem__i_;
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text: .text%__1cLGetRefCountGdo_cpu6Mi_v_: c1_RegAlloc.o;
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text: .text%__1cLLIR_EmitterMindexed_load6MnFRInfo_nJBasicType_pnLLIR_OprDesc_4pnMCodeEmitInfo__v_;
text: .text%__1cLLIR_EmitterNarray_address6MpnLLIR_OprDesc_2inJBasicType__pnLLIR_Address__;
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text: .text%__1cIRegAllocNoops_in_spill6kM_pnIintStack__;
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text: .text%__1cIValueGenbDsafepoint_poll_needs_register6F_i_;
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text: .text%__1cPRegisterManagerElock6MnFRInfo__v_;
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text: .text%__1cNc1_AllocTableFmerge6Mp0_v_;
text: .text%__1cGLIR_OpFvisit6MpnQLIR_OpVisitState__v_;
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text: .text%__1cHLIR_Op0Jemit_code6MpnVLIR_AbstractAssembler__v_;
text: .text%__1cNLIR_OptimizerIemit_op06MpnHLIR_Op0__v_;
text: .text%__1cHLIR_Op2Jemit_code6MpnVLIR_AbstractAssembler__v_;
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text: .text%__1cNLIR_OptimizerNoptimize_move6MpnHLIR_Op1_rpnLLIR_OprDesc_5_i_;
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text: .text%__1cNLIR_OptimizerMis_cache_reg6MpnLLIR_OprDesc__i_;
text: .text%__1cMLocalMappingMis_cache_reg6kMpnLLIR_OprDesc__i_;
text: .text%__1cMLocalMappingMis_cache_reg6kMnFRInfo__i_;
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text: .text%__1cIFrameMapYsignature_type_array_for6FpknIciMethod__pnNBasicTypeList__;
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text: .text%__1cIFrameMapRname_for_argument6Fi_i_;
text: .text%__1cIFrameMapSfp_offset_for_name6kMiii_i_;
text: .text%__1cIFrameMapPnum_local_names6kM_i_;
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text: .text%__1cIFrameMapSfp_offset_for_slot6kMi_i_;
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text: .text%__1cIFrameMapQaddress_for_name6kMiii_nHAddress__;
text: .text%__1cIFrameMapQmake_new_address6kMi_nHAddress__;
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text: .text%__1cNLIR_AssemblerLcode_offset6kM_i_;
text: .text%__1cNLIR_AssemblerbDadd_debug_info_for_null_check6MipnMCodeEmitInfo__v_;
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text: .text%__1cNLIR_AssemblerCpc6kM_pC_;
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text: .text%__1cNCodeStubArrayIindex_of6kMkpnICodeStub__i_: c1_LIRAssembler.o;
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text: .text%__1cNLIR_AssemblerOsafepoint_poll6MnFRInfo_pnMCodeEmitInfo__v_;
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text: .text%__1cPpoll_RelocationEtype6M_nJrelocInfoJrelocType__: codeBlob.o;
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text: .text%__1cRC1_MacroAssemblerRexception_handler6Mii_v_;
text: .text%__1cNLIR_AssemblerPemit_call_stubs6M_v_;
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text: .text%__1cLCompilationbBadd_exception_range_entries6MiipnOExceptionScope_ip2pi_v_;
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text: .text%__1cOLIR_OpJavaCallFvisit6MpnQLIR_OpVisitState__v_;
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text: .text%__1cIFrameMapWcaller_save_cpu_reg_at6Fi_pnLLIR_OprDesc__;
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text: .text%__1cIVoidTypeDtag6kM_nIValueTag__: c1_ValueType.o;
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text: .text%__1cNLIR_AssemblerJemit_call6MpnOLIR_OpJavaCall__v_;
text: .text%__1cNLIR_AssemblerKalign_call6MnILIR_Code__v_;
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+text: .text%__1cOStaticCallStubMis_call_stub6kM_i_: c1_CodeStubs_x86.o;
text: .text%__1cNLIR_AssemblerEcall6MpCnJrelocInfoJrelocType_pnMCodeEmitInfo__v_;
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text: .text%__1cPLIR_OpTypeCheckJemit_code6MpnVLIR_AbstractAssembler__v_;
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text: .text%__1cTSimpleExceptionStubJemit_code6MpnNLIR_Assembler__v_;
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text: .text%__1cJLoadFieldMas_LoadField6M_p0_: c1_Instruction.o;
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text: .text%__1cILIR_ListOallocate_array6MnFRInfo_11111nJBasicType_1pnICodeStub__v_;
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text: .text%__1cIValueGenMdo_ArrayCopy6MpnJIntrinsic__v_;
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text: .text%__1cRpositive_constant6FpnLInstruction__i_: c1_CodeGenerator.o;
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text: .text%__1cLLIR_EmitterNwrite_barrier6MpnLLIR_OprDesc_2_v_;
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+text: .text%__1cILIR_ListUunsigned_shift_right6MnFRInfo_i1_v_: c1_LIREmitter_x86.o;
text: .text%__1cILIR_ListUunsigned_shift_right6MpnLLIR_OprDesc_222_v_;
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text: .text%__1cPLIR_OpArrayCopyFvisit6MpnQLIR_OpVisitState__v_;
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text: .text%__1cNLIR_OptimizerQemit_alloc_array6MpnQLIR_OpAllocArray__v_;
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text: .text%__1cNLIR_AssemblerSarray_element_size6kMnJBasicType__nHAddressLScaleFactor__;
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text: .text%__1cRC1_MacroAssemblerMtry_allocate6MpnMRegisterImpl_2i22rnFLabel__v_;
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+text: .text%__1cQNewTypeArrayStubEinfo6kM_pnMCodeEmitInfo__: c1_CodeStubs_x86.o;
text: .text%__1cNLIR_AssemblerOemit_arraycopy6MpnPLIR_OpArrayCopy__v_;
text: .text%__1cMciArrayKlassMelement_type6M_pnGciType__;
text: .text%__1cNArrayCopyStub2t6MpnMCodeEmitInfo_pnOStaticCallStub__v_;
text: .text%__1cFRInfoMset_word_reg6MkpnMRegisterImpl__v_;
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text: .text%__1cNLIR_AssemblerOpush_parameter6MpnMRegisterImpl_i_v_;
text: .text%__1cQNewTypeArrayStubJemit_code6MpnNLIR_Assembler__v_;
text: .text%__1cNArrayCopyStubJemit_code6MpnNLIR_Assembler__v_;
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text: .text%__1cOLIR_OpAllocObjJemit_code6MpnVLIR_AbstractAssembler__v_;
text: .text%__1cNLIR_OptimizerOemit_alloc_obj6MpnOLIR_OpAllocObj__v_;
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text: .text%__1cNLIR_AssemblerOmembar_acquire6M_v_;
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text: .text%__1cNLIR_AssemblerOemit_osr_entry6MpnHIRScope_ipnFLabel_i_v_;
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+text: .text%__1cXArrayStoreExceptionStubEinfo6kM_pnMCodeEmitInfo__: c1_CodeStubs_x86.o;
text: .text%__1cNLIR_AssemblerEleal6MpnLLIR_OprDesc_2_v_;
text: .text%__1cNLIR_AssemblerGnegate6MpnLLIR_OprDesc_2_v_;
-text: .text%__1cNCodeStubArrayIindex_of6kMkpnICodeStub__i_: c1_LIRAssembler_i486.o;
+text: .text%__1cNCodeStubArrayIindex_of6kMkpnICodeStub__i_: c1_LIRAssembler_x86.o;
text: .text%__1cXArrayStoreExceptionStubJemit_code6MpnNLIR_Assembler__v_;
text: .text%__1cIRuntime1Tresolve_static_call6FpnKJavaThread_pnHoopDesc__pC_;
text: .text%__1cSCompiledStaticCallNcompute_entry6FnMmethodHandle_rnOStaticCallInfo__v_;
@@ -4788,7 +4788,7 @@ text: .text%__1cNLIR_AssemblerIfpu_push6MnFRInfo__v_;
text: .text%__1cIFrameMapLFpuStackSimEpush6Mi_v_;
text: .text%__1cNLIR_AssemblerKfpu_on_tos6MnFRInfo__v_;
text: .text%__1cIFrameMapLFpuStackSimPoffset_from_tos6kMi_i_;
-text: .text%__1cIintArrayIindex_of6kMki_i_: c1_FrameMap_i486.o;
+text: .text%__1cIintArrayIindex_of6kMki_i_: c1_FrameMap_x86.o;
text: .text%__1cNLIR_AssemblerHfpu_pop6MnFRInfo__v_;
text: .text%__1cIFrameMapLFpuStackSimDpop6Mi_i_;
text: .text%__1cNLIR_AssemblerKround32_op6MpnLLIR_OprDesc_2_v_;
@@ -4797,7 +4797,7 @@ text: .text%__1cNLIR_AssemblerJreset_FPU6M_v_;
text: .text%__1cNLIR_AssemblerIemit_op36MpnHLIR_Op3__v_;
text: .text%__1cNLIR_AssemblerParithmetic_idiv6MnILIR_Code_pnLLIR_OprDesc_333pnMCodeEmitInfo__v_;
text: .text%__1cNLIR_AssemblerXadd_debug_info_for_div06MipnMCodeEmitInfo__v_;
-text: .text%__1cNDivByZeroStubEinfo6kM_pnMCodeEmitInfo__: c1_CodeStubs_i486.o;
+text: .text%__1cNDivByZeroStubEinfo6kM_pnMCodeEmitInfo__: c1_CodeStubs_x86.o;
text: .text%__1cNDivByZeroStubJemit_code6MpnNLIR_Assembler__v_;
text: .text%__1cIciObjectSis_obj_array_klass6M_i_: ciTypeArrayKlass.o;
text: .text%__1cLInstructionOas_ArrayLength6M_pnLArrayLength__: c1_GraphBuilder.o;
@@ -4874,12 +4874,12 @@ text: .text%__1cFKlassQup_cast_abstract6M_p0_;
text: .text%__1cRComputeEntryStackHdo_byte6M_v_: generateOopMap.o;
text: .text%__1cNSharedRuntimeDd2i6Fd_i_;
text: .text%__1cSInterpreterRuntimeWslow_signature_handler6FpnKJavaThread_pnNmethodOopDesc_pi5_pC_;
-text: .text%__1cXNativeSignatureIteratorJdo_object6Mii_v_: interpreterRT_i486.o;
-text: .text%__1cUSlowSignatureHandlerLpass_object6M_v_: interpreterRT_i486.o;
-text: .text%__1cXNativeSignatureIteratorIdo_array6Mii_v_: interpreterRT_i486.o;
-text: .text%__1cXNativeSignatureIteratorGdo_int6M_v_: interpreterRT_i486.o;
-text: .text%__1cUSlowSignatureHandlerIpass_int6M_v_: interpreterRT_i486.o;
-text: .text%__1cXNativeSignatureIteratorHdo_bool6M_v_: interpreterRT_i486.o;
+text: .text%__1cXNativeSignatureIteratorJdo_object6Mii_v_: interpreterRT_x86.o;
+text: .text%__1cUSlowSignatureHandlerLpass_object6M_v_: interpreterRT_x86.o;
+text: .text%__1cXNativeSignatureIteratorIdo_array6Mii_v_: interpreterRT_x86.o;
+text: .text%__1cXNativeSignatureIteratorGdo_int6M_v_: interpreterRT_x86.o;
+text: .text%__1cUSlowSignatureHandlerIpass_int6M_v_: interpreterRT_x86.o;
+text: .text%__1cXNativeSignatureIteratorHdo_bool6M_v_: interpreterRT_x86.o;
text: .text%jni_GetFloatArrayRegion: jni.o;
text: .text%jni_GetCharArrayRegion: jni.o;
text: .text%jni_SetFloatField: jni.o;
@@ -4906,8 +4906,8 @@ text: .text%__1cLLIR_EmitterQreturn_op_prolog6Mi_v_;
text: .text%__1cLLIR_EmitterMmonitor_exit6MnFRInfo_11i_v_;
text: .text%__1cILIR_ListNunlock_object6MnFRInfo_11pnICodeStub__v_;
text: .text%__1cKLIR_OpLockFvisit6MpnQLIR_OpVisitState__v_;
-text: .text%__1cQMonitorEnterStubFvisit6MpnQLIR_OpVisitState__v_: c1_CodeStubs_i486.o;
-text: .text%__1cRMonitorAccessStubFvisit6MpnQLIR_OpVisitState__v_: c1_CodeStubs_i486.o;
+text: .text%__1cQMonitorEnterStubFvisit6MpnQLIR_OpVisitState__v_: c1_CodeStubs_x86.o;
+text: .text%__1cRMonitorAccessStubFvisit6MpnQLIR_OpVisitState__v_: c1_CodeStubs_x86.o;
text: .text%__1cKLIR_OpLockJemit_code6MpnVLIR_AbstractAssembler__v_;
text: .text%__1cNLIR_OptimizerJemit_lock6MpnKLIR_OpLock__v_;
text: .text%__1cNLIR_AssemblerPmonitor_address6MinFRInfo__v_;
@@ -4915,7 +4915,7 @@ text: .text%__1cIFrameMapbEaddress_for_monitor_lock_index6kMi_nHAddress__;
text: .text%__1cIFrameMapbAfp_offset_for_monitor_lock6kMi_i_;
text: .text%__1cNLIR_AssemblerJemit_lock6MpnKLIR_OpLock__v_;
text: .text%__1cRC1_MacroAssemblerLlock_object6MpnMRegisterImpl_22rnFLabel__v_;
-text: .text%__1cQMonitorEnterStubEinfo6kM_pnMCodeEmitInfo__: c1_CodeStubs_i486.o;
+text: .text%__1cQMonitorEnterStubEinfo6kM_pnMCodeEmitInfo__: c1_CodeStubs_x86.o;
text: .text%__1cIFrameMapWmonitor_object_regname6kMi_nHOptoRegEName__;
text: .text%__1cIFrameMapbCfp_offset_for_monitor_object6kMi_i_;
text: .text%__1cMCodeEmitInfobHlocation_for_monitor_object_index6Mi_nILocation__;
@@ -4925,7 +4925,7 @@ text: .text%__1cIFrameMapbFlocation_for_monitor_lock_index6kMipnILocation__i_;
text: .text%__1cMMonitorValue2t6MpnKScopeValue_nILocation__v_;
text: .text%__1cMMonitorValueIwrite_on6MpnUDebugInfoWriteStream__v_;
text: .text%__1cRC1_MacroAssemblerNunlock_object6MpnMRegisterImpl_22rnFLabel__v_;
-text: .text%__1cPMonitorExitStubMis_call_stub6kM_i_: c1_CodeStubs_i486.o;
+text: .text%__1cPMonitorExitStubMis_call_stub6kM_i_: c1_CodeStubs_x86.o;
text: .text%__1cQMonitorEnterStubJemit_code6MpnNLIR_Assembler__v_;
text: .text%__1cNLIR_AssemblerRload_receiver_reg6MpnMRegisterImpl__v_;
text: .text%__1cNLIR_AssemblerLmonitorexit6MnFRInfo_1pnMRegisterImpl_i3_v_;
@@ -5168,7 +5168,7 @@ text: .text%__1cFRInfoOas_register_lo6kM_pnMRegisterImpl__;
text: .text%__1cCosHrealloc6FpvI_1_;
text: .text%Unsafe_GetNativeFloat;
text: .text%__1cIValueGenQdo_currentThread6MpnJIntrinsic__v_;
-text: .text%__1cILIR_ListKget_thread6MnFRInfo__v_: c1_CodeGenerator_i486.o;
+text: .text%__1cILIR_ListKget_thread6MnFRInfo__v_: c1_CodeGenerator_x86.o;
text: .text%__1cNLIR_AssemblerKget_thread6MpnLLIR_OprDesc__v_;
text: .text%__1cIValueGenSload_item_patching6MpnHIRScope_ipnEItem_pnKValueStack_pnOExceptionScope__v_;
text: .text%__1cEItemUget_jobject_constant6kM_pnIciObject__;
@@ -5246,7 +5246,7 @@ text: .text%__1cGThreadLnmethods_do6M_v_;
text: .text%__1cFframeLnmethods_do6M_v_;
text: .text%__1cFframeVnmethods_code_blob_do6M_v_;
text: .text%__1cILIR_ListEidiv6MnFRInfo_i11pnMCodeEmitInfo__v_;
-text: .text%__1cLlog2_intptr6Fi_i_: c1_LIRAssembler_i486.o;
+text: .text%__1cLlog2_intptr6Fi_i_: c1_LIRAssembler_x86.o;
text: .text%__1cONMethodSweeperPprocess_nmethod6FpnHnmethod__v_;
text: .text%__1cHnmethodPis_locked_by_vm6kM_i_: nmethod.o;
text: .text%__1cHnmethodLis_unloaded6kM_i_: nmethod.o;
@@ -5423,13 +5423,13 @@ text: .text%__1cIValueGenPdo_UnsafeGetRaw6MpnMUnsafeGetRaw__v_;
text: .text%__1cLLIR_EmitterOget_raw_unsafe6MnFRInfo_pnLLIR_OprDesc_3inJBasicType__v_;
text: .text%__1cILIR_ListMload_mem_reg6MpnLLIR_Address_nFRInfo_nJBasicType_pnMCodeEmitInfo_nHLIR_Op1NLIR_PatchCode__v_;
text: .text%__1cIValueGenPdo_LookupSwitch6MpnMLookupSwitch__v_;
-text: .text%__1cUcreate_lookup_ranges6FpnMLookupSwitch__pnQLookupRangeArray__: c1_CodeGenerator_i486.o;
+text: .text%__1cUcreate_lookup_ranges6FpnMLookupSwitch__pnQLookupRangeArray__: c1_CodeGenerator_x86.o;
text: .text%__1cLLIR_EmitterVlookupswitch_range_op6MpnLLIR_OprDesc_iipnKBlockBegin__v_;
text: .text%__1cNSharedRuntimeEldiv6Fxx_x_;
text: .text%Unsafe_GetObjectVolatile;
text: .text%signalHandler;
text: .text%JVM_handle_solaris_signal;
-text: .text%__1cKJavaThreadUin_stack_yellow_zone6MpC_i_: os_solaris_i486.o;
+text: .text%__1cKJavaThreadUin_stack_yellow_zone6MpC_i_: os_solaris_x86.o;
text: .text%__1cICodeBlobRis_at_poll_return6MpC_i_;
text: .text%__1cUSafepointSynchronizebDhandle_polling_page_exception6FpnKJavaThread__pC_;
text: .text%__1cbCCompiledCodeSafepointHandlerbDhandle_polling_page_exception6M_pC_;
diff --git a/hotspot/make/solaris/makefiles/sa.make b/hotspot/make/solaris/makefiles/sa.make
index 6d700b23437..f8c1bf416c0 100644
--- a/hotspot/make/solaris/makefiles/sa.make
+++ b/hotspot/make/solaris/makefiles/sa.make
@@ -37,8 +37,9 @@ GENERATED = ../generated
SA_CLASSPATH = $(BOOT_JAVA_HOME)/lib/tools.jar
# gnumake 3.78.1 does not accept the *s that
-# are in AGENT_ALLFILES, so use the shell to expand them
-AGENT_ALLFILES := $(shell /usr/bin/test -d $(AGENT_DIR) && /bin/ls $(AGENT_ALLFILES))
+# are in AGENT_FILES1 and AGENT_FILES2, so use the shell to expand them
+AGENT_FILES1 := $(shell /usr/bin/test -d $(AGENT_DIR) && /bin/ls $(AGENT_FILES1))
+AGENT_FILES2 := $(shell /usr/bin/test -d $(AGENT_DIR) && /bin/ls $(AGENT_FILES2))
SA_CLASSDIR = $(GENERATED)/saclasses
@@ -52,7 +53,7 @@ all:
$(MAKE) -f sa.make $(GENERATED)/sa-jdi.jar; \
fi
-$(GENERATED)/sa-jdi.jar: $(AGENT_ALLFILES)
+$(GENERATED)/sa-jdi.jar: $(AGENT_FILES1) $(AGENT_FILES2)
$(QUIETLY) echo "Making $@";
$(QUIETLY) if [ "$(BOOT_JAVA_HOME)" = "" ]; then \
echo "ALT_BOOTDIR, BOOTDIR or JAVA_HOME needs to be defined to build SA"; \
@@ -66,9 +67,17 @@ $(GENERATED)/sa-jdi.jar: $(AGENT_ALLFILES)
$(QUIETLY) if [ ! -d $(SA_CLASSDIR) ] ; then \
mkdir -p $(SA_CLASSDIR); \
fi
- $(QUIETLY) $(COMPILE.JAVAC) -source 1.4 -classpath $(SA_CLASSPATH) -g -d $(SA_CLASSDIR) $(AGENT_ALLFILES)
+ $(QUIETLY) $(COMPILE.JAVAC) -source 1.4 -classpath $(SA_CLASSPATH) -sourcepath $(AGENT_SRC_DIR) -g -d $(SA_CLASSDIR) $(AGENT_FILES1)
+ $(QUIETLY) $(COMPILE.JAVAC) -source 1.4 -classpath $(SA_CLASSPATH) -sourcepath $(AGENT_SRC_DIR) -g -d $(SA_CLASSDIR) $(AGENT_FILES2)
+
$(QUIETLY) $(COMPILE.RMIC) -classpath $(SA_CLASSDIR) -d $(SA_CLASSDIR) sun.jvm.hotspot.debugger.remote.RemoteDebuggerServer
$(QUIETLY) echo "$(SA_BUILD_VERSION_PROP)" > $(SA_PROPERTIES)
+ $(QUIETLY) rm -f $(SA_CLASSDIR)/sun/jvm/hotspot/utilities/soql/sa.js
+ $(QUIETLY) cp $(AGENT_SRC_DIR)/sun/jvm/hotspot/utilities/soql/sa.js $(SA_CLASSDIR)/sun/jvm/hotspot/utilities/soql
+ $(QUIETLY) mkdir -p $(SA_CLASSDIR)/sun/jvm/hotspot/ui/resources
+ $(QUIETLY) rm -f $(SA_CLASSDIR)/sun/jvm/hotspot/ui/resources/*
+ $(QUIETLY) cp $(AGENT_SRC_DIR)/sun/jvm/hotspot/ui/resources/*.png $(SA_CLASSDIR)/sun/jvm/hotspot/ui/resources/
+ $(QUIETLY) cp -r $(AGENT_SRC_DIR)/images/* $(SA_CLASSDIR)/
$(QUIETLY) $(RUN.JAR) cf $@ -C $(SA_CLASSDIR)/ .
$(QUIETLY) $(RUN.JAR) uf $@ -C $(AGENT_SRC_DIR) META-INF/services/com.sun.jdi.connect.Connector
$(QUIETLY) $(RUN.JAVAH) -classpath $(SA_CLASSDIR) -d $(GENERATED) -jni sun.jvm.hotspot.debugger.proc.ProcDebuggerLocal
diff --git a/hotspot/make/windows/makefiles/sa.make b/hotspot/make/windows/makefiles/sa.make
index 481b5149d03..57fd493f823 100644
--- a/hotspot/make/windows/makefiles/sa.make
+++ b/hotspot/make/windows/makefiles/sa.make
@@ -49,15 +49,22 @@ SA_PROPERTIES = $(SA_CLASSDIR)\sa.properties
default:: $(GENERATED)\sa-jdi.jar
-$(GENERATED)\sa-jdi.jar: $(AGENT_ALLFILES:/=\)
+$(GENERATED)\sa-jdi.jar: $(AGENT_FILES1:/=\) $(AGENT_FILES2:/=\)
@if not exist $(SA_CLASSDIR) mkdir $(SA_CLASSDIR)
@echo ...Building sa-jdi.jar
@echo ...$(COMPILE_JAVAC) -source 1.4 -classpath $(SA_CLASSPATH) -g -d $(SA_CLASSDIR) ....
- @$(COMPILE_JAVAC) -source 1.4 -classpath $(SA_CLASSPATH) -g -d $(SA_CLASSDIR) $(AGENT_ALLFILES:/=\)
+ @$(COMPILE_JAVAC) -source 1.4 -classpath $(SA_CLASSPATH) -sourcepath $(AGENT_SRC_DIR) -g -d $(SA_CLASSDIR) $(AGENT_FILES1:/=\)
+ @$(COMPILE_JAVAC) -source 1.4 -classpath $(SA_CLASSPATH) -sourcepath $(AGENT_SRC_DIR) -g -d $(SA_CLASSDIR) $(AGENT_FILES2:/=\)
$(COMPILE_RMIC) -classpath $(SA_CLASSDIR) -d $(SA_CLASSDIR) sun.jvm.hotspot.debugger.remote.RemoteDebuggerServer
$(QUIETLY) echo $(SA_BUILD_VERSION_PROP) > $(SA_PROPERTIES)
$(RUN_JAR) cf $@ -C saclasses .
$(RUN_JAR) uf $@ -C $(AGENT_SRC_DIR:/=\) META-INF\services\com.sun.jdi.connect.Connector
+ $(QUIETLY) rm -f $(SA_CLASSDIR)/sun/jvm/hotspot/utilities/soql/sa.js
+ $(QUIETLY) cp $(AGENT_SRC_DIR)/sun/jvm/hotspot/utilities/soql/sa.js $(SA_CLASSDIR)/sun/jvm/hotspot/utilities/soql
+ $(QUIETLY) mkdir -p $(SA_CLASSDIR)/sun/jvm/hotspot/ui/resources
+ $(QUIETLY) rm -f $(SA_CLASSDIR)/sun/jvm/hotspot/ui/resources/*
+ $(QUIETLY) cp $(AGENT_SRC_DIR)/sun/jvm/hotspot/ui/resources/*.png $(SA_CLASSDIR)/sun/jvm/hotspot/ui/resources/
+ $(QUIETLY) cp -r $(AGENT_SRC_DIR)/images/* $(SA_CLASSDIR)/
$(RUN_JAVAH) -classpath $(SA_CLASSDIR) -jni sun.jvm.hotspot.debugger.windbg.WindbgDebuggerLocal
$(RUN_JAVAH) -classpath $(SA_CLASSDIR) -jni sun.jvm.hotspot.debugger.x86.X86ThreadContext
$(RUN_JAVAH) -classpath $(SA_CLASSDIR) -jni sun.jvm.hotspot.debugger.ia64.IA64ThreadContext
diff --git a/hotspot/src/cpu/sparc/vm/c1_LIRGenerator_sparc.cpp b/hotspot/src/cpu/sparc/vm/c1_LIRGenerator_sparc.cpp
index d5696d442f4..6d941c36866 100644
--- a/hotspot/src/cpu/sparc/vm/c1_LIRGenerator_sparc.cpp
+++ b/hotspot/src/cpu/sparc/vm/c1_LIRGenerator_sparc.cpp
@@ -956,7 +956,8 @@ void LIRGenerator::do_NewMultiArray(NewMultiArray* x) {
size->load_item();
store_stack_parameter (size->result(),
in_ByteSize(STACK_BIAS +
- (i + frame::memory_parameter_word_sp_offset) * wordSize));
+ frame::memory_parameter_word_sp_offset * wordSize +
+ i * sizeof(jint)));
}
// This instruction can be deoptimized in the slow path : use
diff --git a/hotspot/src/cpu/sparc/vm/relocInfo_sparc.cpp b/hotspot/src/cpu/sparc/vm/relocInfo_sparc.cpp
index 795e1831e52..ab365558201 100644
--- a/hotspot/src/cpu/sparc/vm/relocInfo_sparc.cpp
+++ b/hotspot/src/cpu/sparc/vm/relocInfo_sparc.cpp
@@ -204,3 +204,9 @@ void Relocation::pd_swap_out_breakpoint(address x, short* instrs, int instrlen)
NativeInstruction* ni = nativeInstruction_at(x);
ni->set_long_at(0, u.l);
}
+
+void poll_Relocation::fix_relocation_after_move(const CodeBuffer* src, CodeBuffer* dest) {
+}
+
+void poll_return_Relocation::fix_relocation_after_move(const CodeBuffer* src, CodeBuffer* dest) {
+}
diff --git a/hotspot/src/cpu/sparc/vm/sharedRuntime_sparc.cpp b/hotspot/src/cpu/sparc/vm/sharedRuntime_sparc.cpp
index 3812e2eaed9..6fed65b3ddc 100644
--- a/hotspot/src/cpu/sparc/vm/sharedRuntime_sparc.cpp
+++ b/hotspot/src/cpu/sparc/vm/sharedRuntime_sparc.cpp
@@ -465,9 +465,7 @@ int SharedRuntime::java_calling_convention(const BasicType *sig_bt,
case T_LONG:
assert(sig_bt[i+1] == T_VOID, "expecting VOID in other half");
-#ifdef COMPILER2
#ifdef _LP64
- // Can't be tiered (yet)
if (int_reg < int_reg_max) {
Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++);
regs[i].set2(r->as_VMReg());
@@ -476,11 +474,12 @@ int SharedRuntime::java_calling_convention(const BasicType *sig_bt,
stk_reg_pairs += 2;
}
#else
+#ifdef COMPILER2
// For 32-bit build, can't pass longs in O-regs because they become
// I-regs and get trashed. Use G-regs instead. G1 and G4 are almost
// spare and available. This convention isn't used by the Sparc ABI or
// anywhere else. If we're tiered then we don't use G-regs because c1
- // can't deal with them as a "pair".
+ // can't deal with them as a "pair". (Tiered makes this code think g's are filled)
// G0: zero
// G1: 1st Long arg
// G2: global allocated to TLS
@@ -500,7 +499,6 @@ int SharedRuntime::java_calling_convention(const BasicType *sig_bt,
regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
stk_reg_pairs += 2;
}
-#endif // _LP64
#else // COMPILER2
if (int_reg_pairs + 1 < int_reg_max) {
if (is_outgoing) {
@@ -514,6 +512,7 @@ int SharedRuntime::java_calling_convention(const BasicType *sig_bt,
stk_reg_pairs += 2;
}
#endif // COMPILER2
+#endif // _LP64
break;
case T_FLOAT:
@@ -699,17 +698,16 @@ Register AdapterGenerator::next_arg_slot(const int st_off){
// Stores long into offset pointed to by base
void AdapterGenerator::store_c2i_long(Register r, Register base,
const int st_off, bool is_stack) {
-#ifdef COMPILER2
#ifdef _LP64
// In V9, longs are given 2 64-bit slots in the interpreter, but the
// data is passed in only 1 slot.
__ stx(r, base, next_arg_slot(st_off));
#else
+#ifdef COMPILER2
// Misaligned store of 64-bit data
__ stw(r, base, arg_slot(st_off)); // lo bits
__ srlx(r, 32, r);
__ stw(r, base, next_arg_slot(st_off)); // hi bits
-#endif // _LP64
#else
if (is_stack) {
// Misaligned store of 64-bit data
@@ -721,6 +719,7 @@ void AdapterGenerator::store_c2i_long(Register r, Register base,
__ stw(r , base, next_arg_slot(st_off)); // hi bits
}
#endif // COMPILER2
+#endif // _LP64
tag_c2i_arg(frame::TagCategory2, base, st_off, r);
}
@@ -1637,7 +1636,7 @@ static void long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
}
} else if (dst.is_single_phys_reg()) {
if (src.is_adjacent_aligned_on_stack(2)) {
- __ ld_long(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
+ __ ldx(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
} else {
// dst is a single reg.
// Remember lo is low address not msb for stack slots
@@ -1811,7 +1810,6 @@ nmethod *SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
VMRegPair *in_regs,
BasicType ret_type) {
-
// Native nmethod wrappers never take possesion of the oop arguments.
// So the caller will gc the arguments. The only thing we need an
// oopMap for is if the call is static
diff --git a/hotspot/src/cpu/x86/vm/assembler_x86_64.cpp b/hotspot/src/cpu/x86/vm/assembler_x86.cpp
similarity index 58%
rename from hotspot/src/cpu/x86/vm/assembler_x86_64.cpp
rename to hotspot/src/cpu/x86/vm/assembler_x86.cpp
index 431c233df73..d8bc4948c92 100644
--- a/hotspot/src/cpu/x86/vm/assembler_x86_64.cpp
+++ b/hotspot/src/cpu/x86/vm/assembler_x86.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright 2003-2008 Sun Microsystems, Inc. All Rights Reserved.
+ * Copyright 1997-2008 Sun Microsystems, Inc. All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -23,7 +23,7 @@
*/
#include "incls/_precompiled.incl"
-#include "incls/_assembler_x86_64.cpp.incl"
+#include "incls/_assembler_x86.cpp.incl"
// Implementation of AddressLiteral
@@ -52,6 +52,10 @@ AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
case relocInfo::runtime_call_type:
_rspec = runtime_call_Relocation::spec();
break;
+ case relocInfo::poll_type:
+ case relocInfo::poll_return_type:
+ _rspec = Relocation::spec_simple(rtype);
+ break;
case relocInfo::none:
break;
default:
@@ -62,20 +66,13 @@ AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
// Implementation of Address
-Address Address::make_array(ArrayAddress adr) {
#ifdef _LP64
+
+Address Address::make_array(ArrayAddress adr) {
// Not implementable on 64bit machines
// Should have been handled higher up the call chain.
ShouldNotReachHere();
return Address();
-#else
- AddressLiteral base = adr.base();
- Address index = adr.index();
- assert(index._disp == 0, "must not have disp"); // maybe it can?
- Address array(index._base, index._index, index._scale, (intptr_t) base.target());
- array._rspec = base._rspec;
- return array;
-#endif // _LP64
}
// exceedingly dangerous constructor
@@ -95,12 +92,39 @@ Address::Address(int disp, address loc, relocInfo::relocType rtype) {
// HMM
_rspec = runtime_call_Relocation::spec();
break;
+ case relocInfo::poll_type:
+ case relocInfo::poll_return_type:
+ _rspec = Relocation::spec_simple(rtype);
+ break;
case relocInfo::none:
break;
default:
ShouldNotReachHere();
}
}
+#else // LP64
+
+Address Address::make_array(ArrayAddress adr) {
+ AddressLiteral base = adr.base();
+ Address index = adr.index();
+ assert(index._disp == 0, "must not have disp"); // maybe it can?
+ Address array(index._base, index._index, index._scale, (intptr_t) base.target());
+ array._rspec = base._rspec;
+ return array;
+}
+
+// exceedingly dangerous constructor
+Address::Address(address loc, RelocationHolder spec) {
+ _base = noreg;
+ _index = noreg;
+ _scale = no_scale;
+ _disp = (intptr_t) loc;
+ _rspec = spec;
+}
+
+#endif // _LP64
+
+
// Convert the raw encoding form into the form expected by the constructor for
// Address. An index of 4 (rsp) corresponds to having no index, so convert
@@ -116,89 +140,21 @@ Address Address::make_raw(int base, int index, int scale, int disp) {
}
}
-
// Implementation of Assembler
+
int AbstractAssembler::code_fill_byte() {
return (u_char)'\xF4'; // hlt
}
-// This should only be used by 64bit instructions that can use rip-relative
-// it cannot be used by instructions that want an immediate value.
-
-bool Assembler::reachable(AddressLiteral adr) {
- int64_t disp;
-
- // None will force a 64bit literal to the code stream. Likely a placeholder
- // for something that will be patched later and we need to certain it will
- // always be reachable.
- if (adr.reloc() == relocInfo::none) {
- return false;
- }
- if (adr.reloc() == relocInfo::internal_word_type) {
- // This should be rip relative and easily reachable.
- return true;
- }
- if (adr.reloc() != relocInfo::external_word_type &&
- adr.reloc() != relocInfo::runtime_call_type ) {
- return false;
- }
-
- // Stress the correction code
- if (ForceUnreachable) {
- // Must be runtimecall reloc, see if it is in the codecache
- // Flipping stuff in the codecache to be unreachable causes issues
- // with things like inline caches where the additional instructions
- // are not handled.
- if (CodeCache::find_blob(adr._target) == NULL) {
- return false;
- }
- }
- // For external_word_type/runtime_call_type if it is reachable from where we
- // are now (possibly a temp buffer) and where we might end up
- // anywhere in the codeCache then we are always reachable.
- // This would have to change if we ever save/restore shared code
- // to be more pessimistic.
-
- disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
- if (!is_simm32(disp)) return false;
- disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
- if (!is_simm32(disp)) return false;
-
- disp = (int64_t)adr._target - ((int64_t)_code_pos + sizeof(int));
-
- // Because rip relative is a disp + address_of_next_instruction and we
- // don't know the value of address_of_next_instruction we apply a fudge factor
- // to make sure we will be ok no matter the size of the instruction we get placed into.
- // We don't have to fudge the checks above here because they are already worst case.
-
- // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
- // + 4 because better safe than sorry.
- const int fudge = 12 + 4;
- if (disp < 0) {
- disp -= fudge;
- } else {
- disp += fudge;
- }
- return is_simm32(disp);
+// make this go away someday
+void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
+ if (rtype == relocInfo::none)
+ emit_long(data);
+ else emit_data(data, Relocation::spec_simple(rtype), format);
}
-
-// make this go away eventually
-void Assembler::emit_data(jint data,
- relocInfo::relocType rtype,
- int format) {
- if (rtype == relocInfo::none) {
- emit_long(data);
- } else {
- emit_data(data, Relocation::spec_simple(rtype), format);
- }
-}
-
-void Assembler::emit_data(jint data,
- RelocationHolder const& rspec,
- int format) {
- assert(imm64_operand == 0, "default format must be imm64 in this file");
- assert(imm64_operand != format, "must not be imm64");
+void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
+ assert(imm_operand == 0, "default format must be immediate in this file");
assert(inst_mark() != NULL, "must be inside InstructionMark");
if (rspec.type() != relocInfo::none) {
#ifdef ASSERT
@@ -216,67 +172,50 @@ void Assembler::emit_data(jint data,
emit_long(data);
}
-void Assembler::emit_data64(jlong data,
- relocInfo::relocType rtype,
- int format) {
- if (rtype == relocInfo::none) {
- emit_long64(data);
- } else {
- emit_data64(data, Relocation::spec_simple(rtype), format);
+static int encode(Register r) {
+ int enc = r->encoding();
+ if (enc >= 8) {
+ enc -= 8;
}
+ return enc;
}
-void Assembler::emit_data64(jlong data,
- RelocationHolder const& rspec,
- int format) {
- assert(imm64_operand == 0, "default format must be imm64 in this file");
- assert(imm64_operand == format, "must be imm64");
- assert(inst_mark() != NULL, "must be inside InstructionMark");
- // Do not use AbstractAssembler::relocate, which is not intended for
- // embedded words. Instead, relocate to the enclosing instruction.
- code_section()->relocate(inst_mark(), rspec, format);
-#ifdef ASSERT
- check_relocation(rspec, format);
-#endif
- emit_long64(data);
+static int encode(XMMRegister r) {
+ int enc = r->encoding();
+ if (enc >= 8) {
+ enc -= 8;
+ }
+ return enc;
}
void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
+ assert(dst->has_byte_register(), "must have byte register");
assert(isByte(op1) && isByte(op2), "wrong opcode");
assert(isByte(imm8), "not a byte");
assert((op1 & 0x01) == 0, "should be 8bit operation");
- int dstenc = dst->encoding();
- if (dstenc >= 8) {
- dstenc -= 8;
- }
emit_byte(op1);
- emit_byte(op2 | dstenc);
+ emit_byte(op2 | encode(dst));
emit_byte(imm8);
}
-void Assembler::emit_arith(int op1, int op2, Register dst, int imm32) {
+
+void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
assert(isByte(op1) && isByte(op2), "wrong opcode");
assert((op1 & 0x01) == 1, "should be 32bit operation");
assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
- int dstenc = dst->encoding();
- if (dstenc >= 8) {
- dstenc -= 8;
- }
if (is8bit(imm32)) {
emit_byte(op1 | 0x02); // set sign bit
- emit_byte(op2 | dstenc);
+ emit_byte(op2 | encode(dst));
emit_byte(imm32 & 0xFF);
} else {
emit_byte(op1);
- emit_byte(op2 | dstenc);
+ emit_byte(op2 | encode(dst));
emit_long(imm32);
}
}
// immediate-to-memory forms
-void Assembler::emit_arith_operand(int op1,
- Register rm, Address adr,
- int imm32) {
+void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
assert((op1 & 0x01) == 1, "should be 32bit operation");
assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
if (is8bit(imm32)) {
@@ -290,127 +229,117 @@ void Assembler::emit_arith_operand(int op1,
}
}
+void Assembler::emit_arith(int op1, int op2, Register dst, jobject obj) {
+ LP64_ONLY(ShouldNotReachHere());
+ assert(isByte(op1) && isByte(op2), "wrong opcode");
+ assert((op1 & 0x01) == 1, "should be 32bit operation");
+ assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
+ InstructionMark im(this);
+ emit_byte(op1);
+ emit_byte(op2 | encode(dst));
+ emit_data((intptr_t)obj, relocInfo::oop_type, 0);
+}
+
void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
assert(isByte(op1) && isByte(op2), "wrong opcode");
- int dstenc = dst->encoding();
- int srcenc = src->encoding();
- if (dstenc >= 8) {
- dstenc -= 8;
- }
- if (srcenc >= 8) {
- srcenc -= 8;
- }
emit_byte(op1);
- emit_byte(op2 | dstenc << 3 | srcenc);
+ emit_byte(op2 | encode(dst) << 3 | encode(src));
}
+
void Assembler::emit_operand(Register reg, Register base, Register index,
Address::ScaleFactor scale, int disp,
RelocationHolder const& rspec,
int rip_relative_correction) {
relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
- int regenc = reg->encoding();
- if (regenc >= 8) {
- regenc -= 8;
- }
+
+ // Encode the registers as needed in the fields they are used in
+
+ int regenc = encode(reg) << 3;
+ int indexenc = index->is_valid() ? encode(index) << 3 : 0;
+ int baseenc = base->is_valid() ? encode(base) : 0;
+
if (base->is_valid()) {
if (index->is_valid()) {
assert(scale != Address::no_scale, "inconsistent address");
- int indexenc = index->encoding();
- if (indexenc >= 8) {
- indexenc -= 8;
- }
- int baseenc = base->encoding();
- if (baseenc >= 8) {
- baseenc -= 8;
- }
// [base + index*scale + disp]
if (disp == 0 && rtype == relocInfo::none &&
- base != rbp && base != r13) {
+ base != rbp LP64_ONLY(&& base != r13)) {
// [base + index*scale]
// [00 reg 100][ss index base]
assert(index != rsp, "illegal addressing mode");
- emit_byte(0x04 | regenc << 3);
- emit_byte(scale << 6 | indexenc << 3 | baseenc);
+ emit_byte(0x04 | regenc);
+ emit_byte(scale << 6 | indexenc | baseenc);
} else if (is8bit(disp) && rtype == relocInfo::none) {
// [base + index*scale + imm8]
// [01 reg 100][ss index base] imm8
assert(index != rsp, "illegal addressing mode");
- emit_byte(0x44 | regenc << 3);
- emit_byte(scale << 6 | indexenc << 3 | baseenc);
+ emit_byte(0x44 | regenc);
+ emit_byte(scale << 6 | indexenc | baseenc);
emit_byte(disp & 0xFF);
} else {
// [base + index*scale + disp32]
// [10 reg 100][ss index base] disp32
assert(index != rsp, "illegal addressing mode");
- emit_byte(0x84 | regenc << 3);
- emit_byte(scale << 6 | indexenc << 3 | baseenc);
+ emit_byte(0x84 | regenc);
+ emit_byte(scale << 6 | indexenc | baseenc);
emit_data(disp, rspec, disp32_operand);
}
- } else if (base == rsp || base == r12) {
+ } else if (base == rsp LP64_ONLY(|| base == r12)) {
// [rsp + disp]
if (disp == 0 && rtype == relocInfo::none) {
// [rsp]
// [00 reg 100][00 100 100]
- emit_byte(0x04 | regenc << 3);
+ emit_byte(0x04 | regenc);
emit_byte(0x24);
} else if (is8bit(disp) && rtype == relocInfo::none) {
// [rsp + imm8]
// [01 reg 100][00 100 100] disp8
- emit_byte(0x44 | regenc << 3);
+ emit_byte(0x44 | regenc);
emit_byte(0x24);
emit_byte(disp & 0xFF);
} else {
// [rsp + imm32]
// [10 reg 100][00 100 100] disp32
- emit_byte(0x84 | regenc << 3);
+ emit_byte(0x84 | regenc);
emit_byte(0x24);
emit_data(disp, rspec, disp32_operand);
}
} else {
// [base + disp]
- assert(base != rsp && base != r12, "illegal addressing mode");
- int baseenc = base->encoding();
- if (baseenc >= 8) {
- baseenc -= 8;
- }
+ assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
if (disp == 0 && rtype == relocInfo::none &&
- base != rbp && base != r13) {
+ base != rbp LP64_ONLY(&& base != r13)) {
// [base]
// [00 reg base]
- emit_byte(0x00 | regenc << 3 | baseenc);
+ emit_byte(0x00 | regenc | baseenc);
} else if (is8bit(disp) && rtype == relocInfo::none) {
// [base + disp8]
// [01 reg base] disp8
- emit_byte(0x40 | regenc << 3 | baseenc);
+ emit_byte(0x40 | regenc | baseenc);
emit_byte(disp & 0xFF);
} else {
// [base + disp32]
// [10 reg base] disp32
- emit_byte(0x80 | regenc << 3 | baseenc);
+ emit_byte(0x80 | regenc | baseenc);
emit_data(disp, rspec, disp32_operand);
}
}
} else {
if (index->is_valid()) {
assert(scale != Address::no_scale, "inconsistent address");
- int indexenc = index->encoding();
- if (indexenc >= 8) {
- indexenc -= 8;
- }
// [index*scale + disp]
// [00 reg 100][ss index 101] disp32
assert(index != rsp, "illegal addressing mode");
- emit_byte(0x04 | regenc << 3);
- emit_byte(scale << 6 | indexenc << 3 | 0x05);
+ emit_byte(0x04 | regenc);
+ emit_byte(scale << 6 | indexenc | 0x05);
emit_data(disp, rspec, disp32_operand);
-#ifdef _LP64
} else if (rtype != relocInfo::none ) {
- // [disp] RIP-RELATIVE
+ // [disp] (64bit) RIP-RELATIVE (32bit) abs
// [00 000 101] disp32
- emit_byte(0x05 | regenc << 3);
+ emit_byte(0x05 | regenc);
// Note that the RIP-rel. correction applies to the generated
// disp field, but _not_ to the target address in the rspec.
@@ -419,16 +348,18 @@ void Assembler::emit_operand(Register reg, Register base, Register index,
// intptr_t disp = target - next_ip;
assert(inst_mark() != NULL, "must be inside InstructionMark");
address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
- int64_t adjusted = (int64_t) disp - (next_ip - inst_mark());
+ int64_t adjusted = disp;
+ // Do rip-rel adjustment for 64bit
+ LP64_ONLY(adjusted -= (next_ip - inst_mark()));
assert(is_simm32(adjusted),
"must be 32bit offset (RIP relative address)");
- emit_data((int) adjusted, rspec, disp32_operand);
+ emit_data((int32_t) adjusted, rspec, disp32_operand);
-#endif // _LP64
} else {
+ // 32bit never did this, did everything as the rip-rel/disp code above
// [disp] ABSOLUTE
// [00 reg 100][00 100 101] disp32
- emit_byte(0x04 | regenc << 3);
+ emit_byte(0x04 | regenc);
emit_byte(0x25);
emit_data(disp, rspec, disp32_operand);
}
@@ -437,132 +368,8 @@ void Assembler::emit_operand(Register reg, Register base, Register index,
void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
Address::ScaleFactor scale, int disp,
- RelocationHolder const& rspec,
- int rip_relative_correction) {
- relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
- int regenc = reg->encoding();
- if (regenc >= 8) {
- regenc -= 8;
- }
- if (base->is_valid()) {
- if (index->is_valid()) {
- assert(scale != Address::no_scale, "inconsistent address");
- int indexenc = index->encoding();
- if (indexenc >= 8) {
- indexenc -= 8;
- }
- int baseenc = base->encoding();
- if (baseenc >= 8) {
- baseenc -= 8;
- }
- // [base + index*scale + disp]
- if (disp == 0 && rtype == relocInfo::none &&
- base != rbp && base != r13) {
- // [base + index*scale]
- // [00 reg 100][ss index base]
- assert(index != rsp, "illegal addressing mode");
- emit_byte(0x04 | regenc << 3);
- emit_byte(scale << 6 | indexenc << 3 | baseenc);
- } else if (is8bit(disp) && rtype == relocInfo::none) {
- // [base + index*scale + disp8]
- // [01 reg 100][ss index base] disp8
- assert(index != rsp, "illegal addressing mode");
- emit_byte(0x44 | regenc << 3);
- emit_byte(scale << 6 | indexenc << 3 | baseenc);
- emit_byte(disp & 0xFF);
- } else {
- // [base + index*scale + disp32]
- // [10 reg 100][ss index base] disp32
- assert(index != rsp, "illegal addressing mode");
- emit_byte(0x84 | regenc << 3);
- emit_byte(scale << 6 | indexenc << 3 | baseenc);
- emit_data(disp, rspec, disp32_operand);
- }
- } else if (base == rsp || base == r12) {
- // [rsp + disp]
- if (disp == 0 && rtype == relocInfo::none) {
- // [rsp]
- // [00 reg 100][00 100 100]
- emit_byte(0x04 | regenc << 3);
- emit_byte(0x24);
- } else if (is8bit(disp) && rtype == relocInfo::none) {
- // [rsp + imm8]
- // [01 reg 100][00 100 100] disp8
- emit_byte(0x44 | regenc << 3);
- emit_byte(0x24);
- emit_byte(disp & 0xFF);
- } else {
- // [rsp + imm32]
- // [10 reg 100][00 100 100] disp32
- emit_byte(0x84 | regenc << 3);
- emit_byte(0x24);
- emit_data(disp, rspec, disp32_operand);
- }
- } else {
- // [base + disp]
- assert(base != rsp && base != r12, "illegal addressing mode");
- int baseenc = base->encoding();
- if (baseenc >= 8) {
- baseenc -= 8;
- }
- if (disp == 0 && rtype == relocInfo::none &&
- base != rbp && base != r13) {
- // [base]
- // [00 reg base]
- emit_byte(0x00 | regenc << 3 | baseenc);
- } else if (is8bit(disp) && rtype == relocInfo::none) {
- // [base + imm8]
- // [01 reg base] disp8
- emit_byte(0x40 | regenc << 3 | baseenc);
- emit_byte(disp & 0xFF);
- } else {
- // [base + imm32]
- // [10 reg base] disp32
- emit_byte(0x80 | regenc << 3 | baseenc);
- emit_data(disp, rspec, disp32_operand);
- }
- }
- } else {
- if (index->is_valid()) {
- assert(scale != Address::no_scale, "inconsistent address");
- int indexenc = index->encoding();
- if (indexenc >= 8) {
- indexenc -= 8;
- }
- // [index*scale + disp]
- // [00 reg 100][ss index 101] disp32
- assert(index != rsp, "illegal addressing mode");
- emit_byte(0x04 | regenc << 3);
- emit_byte(scale << 6 | indexenc << 3 | 0x05);
- emit_data(disp, rspec, disp32_operand);
-#ifdef _LP64
- } else if ( rtype != relocInfo::none ) {
- // [disp] RIP-RELATIVE
- // [00 reg 101] disp32
- emit_byte(0x05 | regenc << 3);
- // Note that the RIP-rel. correction applies to the generated
- // disp field, but _not_ to the target address in the rspec.
-
- // disp was created by converting the target address minus the pc
- // at the start of the instruction. That needs more correction here.
- // intptr_t disp = target - next_ip;
-
- assert(inst_mark() != NULL, "must be inside InstructionMark");
- address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
-
- int64_t adjusted = (int64_t) disp - (next_ip - inst_mark());
- assert(is_simm32(adjusted),
- "must be 32bit offset (RIP relative address)");
- emit_data((int) adjusted, rspec, disp32_operand);
-#endif // _LP64
- } else {
- // [disp] ABSOLUTE
- // [00 reg 100][00 100 101] disp32
- emit_byte(0x04 | regenc << 3);
- emit_byte(0x25);
- emit_data(disp, rspec, disp32_operand);
- }
- }
+ RelocationHolder const& rspec) {
+ emit_operand((Register)reg, base, index, scale, disp, rspec);
}
// Secret local extension to Assembler::WhichOperand:
@@ -603,8 +410,9 @@ address Assembler::locate_operand(address inst, WhichOperand which) {
case ES_segment:
case FS_segment:
case GS_segment:
- assert(0, "shouldn't have that prefix");
- assert(ip == inst + 1 || ip == inst + 2, "only two prefixes allowed");
+ // Seems dubious
+ LP64_ONLY(assert(false, "shouldn't have that prefix"));
+ assert(ip == inst+1, "only one prefix allowed");
goto again_after_prefix;
case 0x67:
@@ -616,7 +424,7 @@ address Assembler::locate_operand(address inst, WhichOperand which) {
case REX_RB:
case REX_RX:
case REX_RXB:
-// assert(ip == inst + 1, "only one prefix allowed");
+ NOT_LP64(assert(false, "64bit prefixes"));
goto again_after_prefix;
case REX_W:
@@ -627,8 +435,8 @@ address Assembler::locate_operand(address inst, WhichOperand which) {
case REX_WRB:
case REX_WRX:
case REX_WRXB:
+ NOT_LP64(assert(false, "64bit prefixes"));
is_64bit = true;
-// assert(ip == inst + 1, "only one prefix allowed");
goto again_after_prefix;
case 0xFF: // pushq a; decl a; incl a; call a; jmp a
@@ -637,15 +445,15 @@ address Assembler::locate_operand(address inst, WhichOperand which) {
case 0x8A: // movb r, a
case 0x8B: // movl r, a
case 0x8F: // popl a
- debug_only(has_disp32 = true;)
+ debug_only(has_disp32 = true);
break;
case 0x68: // pushq #32
if (which == end_pc_operand) {
return ip + 4;
}
- assert(0, "pushq has no disp32 or imm64");
- ShouldNotReachHere();
+ assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
+ return ip; // not produced by emit_operand
case 0x66: // movw ... (size prefix)
again_after_size_prefix2:
@@ -666,11 +474,14 @@ address Assembler::locate_operand(address inst, WhichOperand which) {
case REX_WRB:
case REX_WRX:
case REX_WRXB:
+ NOT_LP64(assert(false, "64bit prefix found"));
goto again_after_size_prefix2;
case 0x8B: // movw r, a
case 0x89: // movw a, r
+ debug_only(has_disp32 = true);
break;
case 0xC7: // movw a, #16
+ debug_only(has_disp32 = true);
tail_size = 2; // the imm16
break;
case 0x0F: // several SSE/SSE2 variants
@@ -683,8 +494,13 @@ address Assembler::locate_operand(address inst, WhichOperand which) {
case REP8(0xB8): // movl/q r, #32/#64(oop?)
if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
- assert((which == call32_operand || which == imm64_operand) && is_64bit ||
+ // these asserts are somewhat nonsensical
+#ifndef _LP64
+ assert(which == imm_operand || which == disp32_operand, "");
+#else
+ assert((which == call32_operand || which == imm_operand) && is_64bit ||
which == narrow_oop_operand && !is_64bit, "");
+#endif // _LP64
return ip;
case 0x69: // imul r, a, #32
@@ -700,18 +516,23 @@ address Assembler::locate_operand(address inst, WhichOperand which) {
case 0x2E: // ucomiss
case 0x2F: // comiss
case 0x54: // andps
+ case 0x55: // andnps
+ case 0x56: // orps
case 0x57: // xorps
case 0x6E: // movd
case 0x7E: // movd
case 0xAE: // ldmxcsr a
- debug_only(has_disp32 = true); // has both kinds of operands!
+ // 64bit side says it these have both operands but that doesn't
+ // appear to be true
+ debug_only(has_disp32 = true);
break;
+
case 0xAD: // shrd r, a, %cl
case 0xAF: // imul r, a
- case 0xBE: // movsbl r, a
- case 0xBF: // movswl r, a
- case 0xB6: // movzbl r, a
- case 0xB7: // movzwl r, a
+ case 0xBE: // movsbl r, a (movsxb)
+ case 0xBF: // movswl r, a (movsxw)
+ case 0xB6: // movzbl r, a (movzxb)
+ case 0xB7: // movzwl r, a (movzxw)
case REP16(0x40): // cmovl cc, r, a
case 0xB0: // cmpxchgb
case 0xB1: // cmpxchg
@@ -721,13 +542,15 @@ address Assembler::locate_operand(address inst, WhichOperand which) {
debug_only(has_disp32 = true);
// fall out of the switch to decode the address
break;
+
case 0xAC: // shrd r, a, #8
debug_only(has_disp32 = true);
tail_size = 1; // the imm8
break;
+
case REP16(0x80): // jcc rdisp32
if (which == end_pc_operand) return ip + 4;
- assert(which == call32_operand, "jcc has no disp32 or imm64");
+ assert(which == call32_operand, "jcc has no disp32 or imm");
return ip;
default:
ShouldNotReachHere();
@@ -736,6 +559,7 @@ address Assembler::locate_operand(address inst, WhichOperand which) {
case 0x81: // addl a, #32; addl r, #32
// also: orl, adcl, sbbl, andl, subl, xorl, cmpl
+ // on 32bit in the case of cmpl, the imm might be an oop
tail_size = 4;
debug_only(has_disp32 = true); // has both kinds of operands!
break;
@@ -764,11 +588,9 @@ address Assembler::locate_operand(address inst, WhichOperand which) {
case REP4(0x18): // sbb...
case REP4(0x28): // sub...
case 0xF7: // mull a
- case 0x87: // xchg r, a
- debug_only(has_disp32 = true);
- break;
- case REP4(0x38): // cmp...
case 0x8D: // lea r, a
+ case 0x87: // xchg r, a
+ case REP4(0x38): // cmp...
case 0x85: // test r, a
debug_only(has_disp32 = true); // has both kinds of operands!
break;
@@ -784,7 +606,7 @@ address Assembler::locate_operand(address inst, WhichOperand which) {
case 0xE8: // call rdisp32
case 0xE9: // jmp rdisp32
if (which == end_pc_operand) return ip + 4;
- assert(which == call32_operand, "call has no disp32 or imm32");
+ assert(which == call32_operand, "call has no disp32 or imm");
return ip;
case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
@@ -818,6 +640,7 @@ address Assembler::locate_operand(address inst, WhichOperand which) {
case REX_WRB:
case REX_WRX:
case REX_WRXB:
+ NOT_LP64(assert(false, "found 64bit prefix"));
ip++;
default:
ip++;
@@ -833,7 +656,12 @@ address Assembler::locate_operand(address inst, WhichOperand which) {
}
assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
- assert(which != imm64_operand, "instruction is not a movq reg, imm64");
+#ifdef _LP64
+ assert(which != imm_operand, "instruction is not a movq reg, imm64");
+#else
+ // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
+ assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
+#endif // LP64
assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
// parse the output of emit_operand
@@ -888,7 +716,11 @@ address Assembler::locate_operand(address inst, WhichOperand which) {
return ip + tail_size;
}
- assert(0, "fix locate_operand");
+#ifdef _LP64
+ assert(false, "fix locate_operand");
+#else
+ assert(which == imm_operand, "instruction has only an imm field");
+#endif // LP64
return ip;
}
@@ -897,219 +729,36 @@ address Assembler::locate_next_instruction(address inst) {
return locate_operand(inst, end_pc_operand);
}
+
#ifdef ASSERT
void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
address inst = inst_mark();
- assert(inst != NULL && inst < pc(),
- "must point to beginning of instruction");
+ assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
address opnd;
Relocation* r = rspec.reloc();
if (r->type() == relocInfo::none) {
return;
} else if (r->is_call() || format == call32_operand) {
+ // assert(format == imm32_operand, "cannot specify a nonzero format");
opnd = locate_operand(inst, call32_operand);
} else if (r->is_data()) {
- assert(format == imm64_operand || format == disp32_operand ||
- format == narrow_oop_operand, "format ok");
- opnd = locate_operand(inst, (WhichOperand) format);
+ assert(format == imm_operand || format == disp32_operand
+ LP64_ONLY(|| format == narrow_oop_operand), "format ok");
+ opnd = locate_operand(inst, (WhichOperand)format);
} else {
- assert(format == 0, "cannot specify a format");
+ assert(format == imm_operand, "cannot specify a format");
return;
}
assert(opnd == pc(), "must put operand where relocs can find it");
}
-#endif
+#endif // ASSERT
-int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
- if (reg_enc >= 8) {
- prefix(REX_B);
- reg_enc -= 8;
- } else if (byteinst && reg_enc >= 4) {
- prefix(REX);
- }
- return reg_enc;
-}
-
-int Assembler::prefixq_and_encode(int reg_enc) {
- if (reg_enc < 8) {
- prefix(REX_W);
- } else {
- prefix(REX_WB);
- reg_enc -= 8;
- }
- return reg_enc;
-}
-
-int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) {
- if (dst_enc < 8) {
- if (src_enc >= 8) {
- prefix(REX_B);
- src_enc -= 8;
- } else if (byteinst && src_enc >= 4) {
- prefix(REX);
- }
- } else {
- if (src_enc < 8) {
- prefix(REX_R);
- } else {
- prefix(REX_RB);
- src_enc -= 8;
- }
- dst_enc -= 8;
- }
- return dst_enc << 3 | src_enc;
-}
-
-int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
- if (dst_enc < 8) {
- if (src_enc < 8) {
- prefix(REX_W);
- } else {
- prefix(REX_WB);
- src_enc -= 8;
- }
- } else {
- if (src_enc < 8) {
- prefix(REX_WR);
- } else {
- prefix(REX_WRB);
- src_enc -= 8;
- }
- dst_enc -= 8;
- }
- return dst_enc << 3 | src_enc;
-}
-
-void Assembler::prefix(Register reg) {
- if (reg->encoding() >= 8) {
- prefix(REX_B);
- }
-}
-
-void Assembler::prefix(Address adr) {
- if (adr.base_needs_rex()) {
- if (adr.index_needs_rex()) {
- prefix(REX_XB);
- } else {
- prefix(REX_B);
- }
- } else {
- if (adr.index_needs_rex()) {
- prefix(REX_X);
- }
- }
-}
-
-void Assembler::prefixq(Address adr) {
- if (adr.base_needs_rex()) {
- if (adr.index_needs_rex()) {
- prefix(REX_WXB);
- } else {
- prefix(REX_WB);
- }
- } else {
- if (adr.index_needs_rex()) {
- prefix(REX_WX);
- } else {
- prefix(REX_W);
- }
- }
-}
-
-
-void Assembler::prefix(Address adr, Register reg, bool byteinst) {
- if (reg->encoding() < 8) {
- if (adr.base_needs_rex()) {
- if (adr.index_needs_rex()) {
- prefix(REX_XB);
- } else {
- prefix(REX_B);
- }
- } else {
- if (adr.index_needs_rex()) {
- prefix(REX_X);
- } else if (reg->encoding() >= 4 ) {
- prefix(REX);
- }
- }
- } else {
- if (adr.base_needs_rex()) {
- if (adr.index_needs_rex()) {
- prefix(REX_RXB);
- } else {
- prefix(REX_RB);
- }
- } else {
- if (adr.index_needs_rex()) {
- prefix(REX_RX);
- } else {
- prefix(REX_R);
- }
- }
- }
-}
-
-void Assembler::prefixq(Address adr, Register src) {
- if (src->encoding() < 8) {
- if (adr.base_needs_rex()) {
- if (adr.index_needs_rex()) {
- prefix(REX_WXB);
- } else {
- prefix(REX_WB);
- }
- } else {
- if (adr.index_needs_rex()) {
- prefix(REX_WX);
- } else {
- prefix(REX_W);
- }
- }
- } else {
- if (adr.base_needs_rex()) {
- if (adr.index_needs_rex()) {
- prefix(REX_WRXB);
- } else {
- prefix(REX_WRB);
- }
- } else {
- if (adr.index_needs_rex()) {
- prefix(REX_WRX);
- } else {
- prefix(REX_WR);
- }
- }
- }
-}
-
-void Assembler::prefix(Address adr, XMMRegister reg) {
- if (reg->encoding() < 8) {
- if (adr.base_needs_rex()) {
- if (adr.index_needs_rex()) {
- prefix(REX_XB);
- } else {
- prefix(REX_B);
- }
- } else {
- if (adr.index_needs_rex()) {
- prefix(REX_X);
- }
- }
- } else {
- if (adr.base_needs_rex()) {
- if (adr.index_needs_rex()) {
- prefix(REX_RXB);
- } else {
- prefix(REX_RB);
- }
- } else {
- if (adr.index_needs_rex()) {
- prefix(REX_RX);
- } else {
- prefix(REX_R);
- }
- }
- }
+void Assembler::emit_operand32(Register reg, Address adr) {
+ assert(reg->encoding() < 8, "no extended registers");
+ assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
+ emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
+ adr._rspec);
}
void Assembler::emit_operand(Register reg, Address adr,
@@ -1119,13 +768,24 @@ void Assembler::emit_operand(Register reg, Address adr,
rip_relative_correction);
}
-void Assembler::emit_operand(XMMRegister reg, Address adr,
- int rip_relative_correction) {
+void Assembler::emit_operand(XMMRegister reg, Address adr) {
emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
- adr._rspec,
- rip_relative_correction);
+ adr._rspec);
}
+// MMX operations
+void Assembler::emit_operand(MMXRegister reg, Address adr) {
+ assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
+ emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
+}
+
+// work around gcc (3.2.1-7a) bug
+void Assembler::emit_operand(Address adr, MMXRegister reg) {
+ assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
+ emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
+}
+
+
void Assembler::emit_farith(int b1, int b2, int i) {
assert(isByte(b1) && isByte(b2), "wrong opcode");
assert(0 <= i && i < 8, "illegal stack offset");
@@ -1133,612 +793,10 @@ void Assembler::emit_farith(int b1, int b2, int i) {
emit_byte(b2 + i);
}
-// pushad is invalid, use this instead.
-// NOTE: Kills flags!!
-void Assembler::pushaq() {
- // we have to store original rsp. ABI says that 128 bytes
- // below rsp are local scratch.
- movq(Address(rsp, -5 * wordSize), rsp);
- subq(rsp, 16 * wordSize);
+// Now the Assembler instruction (identical for 32/64 bits)
- movq(Address(rsp, 15 * wordSize), rax);
- movq(Address(rsp, 14 * wordSize), rcx);
- movq(Address(rsp, 13 * wordSize), rdx);
- movq(Address(rsp, 12 * wordSize), rbx);
- // skip rsp
- movq(Address(rsp, 10 * wordSize), rbp);
- movq(Address(rsp, 9 * wordSize), rsi);
- movq(Address(rsp, 8 * wordSize), rdi);
- movq(Address(rsp, 7 * wordSize), r8);
- movq(Address(rsp, 6 * wordSize), r9);
- movq(Address(rsp, 5 * wordSize), r10);
- movq(Address(rsp, 4 * wordSize), r11);
- movq(Address(rsp, 3 * wordSize), r12);
- movq(Address(rsp, 2 * wordSize), r13);
- movq(Address(rsp, wordSize), r14);
- movq(Address(rsp, 0), r15);
-}
-
-// popad is invalid, use this instead
-// NOTE: Kills flags!!
-void Assembler::popaq() {
- movq(r15, Address(rsp, 0));
- movq(r14, Address(rsp, wordSize));
- movq(r13, Address(rsp, 2 * wordSize));
- movq(r12, Address(rsp, 3 * wordSize));
- movq(r11, Address(rsp, 4 * wordSize));
- movq(r10, Address(rsp, 5 * wordSize));
- movq(r9, Address(rsp, 6 * wordSize));
- movq(r8, Address(rsp, 7 * wordSize));
- movq(rdi, Address(rsp, 8 * wordSize));
- movq(rsi, Address(rsp, 9 * wordSize));
- movq(rbp, Address(rsp, 10 * wordSize));
- // skip rsp
- movq(rbx, Address(rsp, 12 * wordSize));
- movq(rdx, Address(rsp, 13 * wordSize));
- movq(rcx, Address(rsp, 14 * wordSize));
- movq(rax, Address(rsp, 15 * wordSize));
-
- addq(rsp, 16 * wordSize);
-}
-
-void Assembler::pushfq() {
- emit_byte(0x9C);
-}
-
-void Assembler::popfq() {
- emit_byte(0x9D);
-}
-
-void Assembler::pushq(int imm32) {
- emit_byte(0x68);
- emit_long(imm32);
-}
-
-void Assembler::pushq(Register src) {
- int encode = prefix_and_encode(src->encoding());
-
- emit_byte(0x50 | encode);
-}
-
-void Assembler::pushq(Address src) {
- InstructionMark im(this);
- prefix(src);
- emit_byte(0xFF);
- emit_operand(rsi, src);
-}
-
-void Assembler::popq(Register dst) {
- int encode = prefix_and_encode(dst->encoding());
- emit_byte(0x58 | encode);
-}
-
-void Assembler::popq(Address dst) {
- InstructionMark im(this);
- prefix(dst);
- emit_byte(0x8F);
- emit_operand(rax, dst);
-}
-
-void Assembler::prefix(Prefix p) {
- a_byte(p);
-}
-
-void Assembler::movb(Register dst, Address src) {
- InstructionMark im(this);
- prefix(src, dst, true);
- emit_byte(0x8A);
- emit_operand(dst, src);
-}
-
-void Assembler::movb(Address dst, int imm8) {
- InstructionMark im(this);
- prefix(dst);
- emit_byte(0xC6);
- emit_operand(rax, dst, 1);
- emit_byte(imm8);
-}
-
-void Assembler::movb(Address dst, Register src) {
- InstructionMark im(this);
- prefix(dst, src, true);
- emit_byte(0x88);
- emit_operand(src, dst);
-}
-
-void Assembler::movw(Address dst, int imm16) {
- InstructionMark im(this);
- emit_byte(0x66); // switch to 16-bit mode
- prefix(dst);
- emit_byte(0xC7);
- emit_operand(rax, dst, 2);
- emit_word(imm16);
-}
-
-void Assembler::movw(Register dst, Address src) {
- InstructionMark im(this);
- emit_byte(0x66);
- prefix(src, dst);
- emit_byte(0x8B);
- emit_operand(dst, src);
-}
-
-void Assembler::movw(Address dst, Register src) {
- InstructionMark im(this);
- emit_byte(0x66);
- prefix(dst, src);
- emit_byte(0x89);
- emit_operand(src, dst);
-}
-
-// Uses zero extension.
-void Assembler::movl(Register dst, int imm32) {
- int encode = prefix_and_encode(dst->encoding());
- emit_byte(0xB8 | encode);
- emit_long(imm32);
-}
-
-void Assembler::movl(Register dst, Register src) {
- int encode = prefix_and_encode(dst->encoding(), src->encoding());
- emit_byte(0x8B);
- emit_byte(0xC0 | encode);
-}
-
-void Assembler::movl(Register dst, Address src) {
- InstructionMark im(this);
- prefix(src, dst);
- emit_byte(0x8B);
- emit_operand(dst, src);
-}
-
-void Assembler::movl(Address dst, int imm32) {
- InstructionMark im(this);
- prefix(dst);
- emit_byte(0xC7);
- emit_operand(rax, dst, 4);
- emit_long(imm32);
-}
-
-void Assembler::movl(Address dst, Register src) {
- InstructionMark im(this);
- prefix(dst, src);
- emit_byte(0x89);
- emit_operand(src, dst);
-}
-
-void Assembler::mov64(Register dst, intptr_t imm64) {
- InstructionMark im(this);
- int encode = prefixq_and_encode(dst->encoding());
- emit_byte(0xB8 | encode);
- emit_long64(imm64);
-}
-
-void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
- InstructionMark im(this);
- int encode = prefixq_and_encode(dst->encoding());
- emit_byte(0xB8 | encode);
- emit_data64(imm64, rspec);
-}
-
-void Assembler::movq(Register dst, Register src) {
- int encode = prefixq_and_encode(dst->encoding(), src->encoding());
- emit_byte(0x8B);
- emit_byte(0xC0 | encode);
-}
-
-void Assembler::movq(Register dst, Address src) {
- InstructionMark im(this);
- prefixq(src, dst);
- emit_byte(0x8B);
- emit_operand(dst, src);
-}
-
-void Assembler::mov64(Address dst, intptr_t imm32) {
- assert(is_simm32(imm32), "lost bits");
- InstructionMark im(this);
- prefixq(dst);
- emit_byte(0xC7);
- emit_operand(rax, dst, 4);
- emit_long(imm32);
-}
-
-void Assembler::movq(Address dst, Register src) {
- InstructionMark im(this);
- prefixq(dst, src);
- emit_byte(0x89);
- emit_operand(src, dst);
-}
-
-void Assembler::movsbl(Register dst, Address src) {
- InstructionMark im(this);
- prefix(src, dst);
- emit_byte(0x0F);
- emit_byte(0xBE);
- emit_operand(dst, src);
-}
-
-void Assembler::movsbl(Register dst, Register src) {
- int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
- emit_byte(0x0F);
- emit_byte(0xBE);
- emit_byte(0xC0 | encode);
-}
-
-void Assembler::movswl(Register dst, Address src) {
- InstructionMark im(this);
- prefix(src, dst);
- emit_byte(0x0F);
- emit_byte(0xBF);
- emit_operand(dst, src);
-}
-
-void Assembler::movswl(Register dst, Register src) {
- int encode = prefix_and_encode(dst->encoding(), src->encoding());
- emit_byte(0x0F);
- emit_byte(0xBF);
- emit_byte(0xC0 | encode);
-}
-
-void Assembler::movslq(Register dst, Address src) {
- InstructionMark im(this);
- prefixq(src, dst);
- emit_byte(0x63);
- emit_operand(dst, src);
-}
-
-void Assembler::movslq(Register dst, Register src) {
- int encode = prefixq_and_encode(dst->encoding(), src->encoding());
- emit_byte(0x63);
- emit_byte(0xC0 | encode);
-}
-
-void Assembler::movzbl(Register dst, Address src) {
- InstructionMark im(this);
- prefix(src, dst);
- emit_byte(0x0F);
- emit_byte(0xB6);
- emit_operand(dst, src);
-}
-
-void Assembler::movzbl(Register dst, Register src) {
- int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
- emit_byte(0x0F);
- emit_byte(0xB6);
- emit_byte(0xC0 | encode);
-}
-
-void Assembler::movzwl(Register dst, Address src) {
- InstructionMark im(this);
- prefix(src, dst);
- emit_byte(0x0F);
- emit_byte(0xB7);
- emit_operand(dst, src);
-}
-
-void Assembler::movzwl(Register dst, Register src) {
- int encode = prefix_and_encode(dst->encoding(), src->encoding());
- emit_byte(0x0F);
- emit_byte(0xB7);
- emit_byte(0xC0 | encode);
-}
-
-void Assembler::movss(XMMRegister dst, XMMRegister src) {
- emit_byte(0xF3);
- int encode = prefix_and_encode(dst->encoding(), src->encoding());
- emit_byte(0x0F);
- emit_byte(0x10);
- emit_byte(0xC0 | encode);
-}
-
-void Assembler::movss(XMMRegister dst, Address src) {
- InstructionMark im(this);
- emit_byte(0xF3);
- prefix(src, dst);
- emit_byte(0x0F);
- emit_byte(0x10);
- emit_operand(dst, src);
-}
-
-void Assembler::movss(Address dst, XMMRegister src) {
- InstructionMark im(this);
- emit_byte(0xF3);
- prefix(dst, src);
- emit_byte(0x0F);
- emit_byte(0x11);
- emit_operand(src, dst);
-}
-
-void Assembler::movsd(XMMRegister dst, XMMRegister src) {
- emit_byte(0xF2);
- int encode = prefix_and_encode(dst->encoding(), src->encoding());
- emit_byte(0x0F);
- emit_byte(0x10);
- emit_byte(0xC0 | encode);
-}
-
-void Assembler::movsd(XMMRegister dst, Address src) {
- InstructionMark im(this);
- emit_byte(0xF2);
- prefix(src, dst);
- emit_byte(0x0F);
- emit_byte(0x10);
- emit_operand(dst, src);
-}
-
-void Assembler::movsd(Address dst, XMMRegister src) {
- InstructionMark im(this);
- emit_byte(0xF2);
- prefix(dst, src);
- emit_byte(0x0F);
- emit_byte(0x11);
- emit_operand(src, dst);
-}
-
-// New cpus require to use movsd and movss to avoid partial register stall
-// when loading from memory. But for old Opteron use movlpd instead of movsd.
-// The selection is done in MacroAssembler::movdbl() and movflt().
-void Assembler::movlpd(XMMRegister dst, Address src) {
- InstructionMark im(this);
- emit_byte(0x66);
- prefix(src, dst);
- emit_byte(0x0F);
- emit_byte(0x12);
- emit_operand(dst, src);
-}
-
-void Assembler::movapd(XMMRegister dst, XMMRegister src) {
- int dstenc = dst->encoding();
- int srcenc = src->encoding();
- emit_byte(0x66);
- if (dstenc < 8) {
- if (srcenc >= 8) {
- prefix(REX_B);
- srcenc -= 8;
- }
- } else {
- if (srcenc < 8) {
- prefix(REX_R);
- } else {
- prefix(REX_RB);
- srcenc -= 8;
- }
- dstenc -= 8;
- }
- emit_byte(0x0F);
- emit_byte(0x28);
- emit_byte(0xC0 | dstenc << 3 | srcenc);
-}
-
-void Assembler::movaps(XMMRegister dst, XMMRegister src) {
- int dstenc = dst->encoding();
- int srcenc = src->encoding();
- if (dstenc < 8) {
- if (srcenc >= 8) {
- prefix(REX_B);
- srcenc -= 8;
- }
- } else {
- if (srcenc < 8) {
- prefix(REX_R);
- } else {
- prefix(REX_RB);
- srcenc -= 8;
- }
- dstenc -= 8;
- }
- emit_byte(0x0F);
- emit_byte(0x28);
- emit_byte(0xC0 | dstenc << 3 | srcenc);
-}
-
-void Assembler::movdl(XMMRegister dst, Register src) {
- emit_byte(0x66);
- int encode = prefix_and_encode(dst->encoding(), src->encoding());
- emit_byte(0x0F);
- emit_byte(0x6E);
- emit_byte(0xC0 | encode);
-}
-
-void Assembler::movdl(Register dst, XMMRegister src) {
- emit_byte(0x66);
- // swap src/dst to get correct prefix
- int encode = prefix_and_encode(src->encoding(), dst->encoding());
- emit_byte(0x0F);
- emit_byte(0x7E);
- emit_byte(0xC0 | encode);
-}
-
-void Assembler::movdq(XMMRegister dst, Register src) {
- emit_byte(0x66);
- int encode = prefixq_and_encode(dst->encoding(), src->encoding());
- emit_byte(0x0F);
- emit_byte(0x6E);
- emit_byte(0xC0 | encode);
-}
-
-void Assembler::movdq(Register dst, XMMRegister src) {
- emit_byte(0x66);
- // swap src/dst to get correct prefix
- int encode = prefixq_and_encode(src->encoding(), dst->encoding());
- emit_byte(0x0F);
- emit_byte(0x7E);
- emit_byte(0xC0 | encode);
-}
-
-void Assembler::pxor(XMMRegister dst, Address src) {
- InstructionMark im(this);
- emit_byte(0x66);
- prefix(src, dst);
- emit_byte(0x0F);
- emit_byte(0xEF);
- emit_operand(dst, src);
-}
-
-void Assembler::pxor(XMMRegister dst, XMMRegister src) {
- InstructionMark im(this);
- emit_byte(0x66);
- int encode = prefix_and_encode(dst->encoding(), src->encoding());
- emit_byte(0x0F);
- emit_byte(0xEF);
- emit_byte(0xC0 | encode);
-}
-
-void Assembler::movdqa(XMMRegister dst, Address src) {
- InstructionMark im(this);
- emit_byte(0x66);
- prefix(src, dst);
- emit_byte(0x0F);
- emit_byte(0x6F);
- emit_operand(dst, src);
-}
-
-void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
- emit_byte(0x66);
- int encode = prefixq_and_encode(dst->encoding(), src->encoding());
- emit_byte(0x0F);
- emit_byte(0x6F);
- emit_byte(0xC0 | encode);
-}
-
-void Assembler::movdqa(Address dst, XMMRegister src) {
- InstructionMark im(this);
- emit_byte(0x66);
- prefix(dst, src);
- emit_byte(0x0F);
- emit_byte(0x7F);
- emit_operand(src, dst);
-}
-
-void Assembler::movq(XMMRegister dst, Address src) {
- InstructionMark im(this);
- emit_byte(0xF3);
- prefix(src, dst);
- emit_byte(0x0F);
- emit_byte(0x7E);
- emit_operand(dst, src);
-}
-
-void Assembler::movq(Address dst, XMMRegister src) {
- InstructionMark im(this);
- emit_byte(0x66);
- prefix(dst, src);
- emit_byte(0x0F);
- emit_byte(0xD6);
- emit_operand(src, dst);
-}
-
-void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
- assert(isByte(mode), "invalid value");
- emit_byte(0x66);
- int encode = prefix_and_encode(dst->encoding(), src->encoding());
- emit_byte(0x0F);
- emit_byte(0x70);
- emit_byte(0xC0 | encode);
- emit_byte(mode & 0xFF);
-}
-
-void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
- assert(isByte(mode), "invalid value");
- InstructionMark im(this);
- emit_byte(0x66);
- emit_byte(0x0F);
- emit_byte(0x70);
- emit_operand(dst, src);
- emit_byte(mode & 0xFF);
-}
-
-void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
- assert(isByte(mode), "invalid value");
- emit_byte(0xF2);
- int encode = prefix_and_encode(dst->encoding(), src->encoding());
- emit_byte(0x0F);
- emit_byte(0x70);
- emit_byte(0xC0 | encode);
- emit_byte(mode & 0xFF);
-}
-
-void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
- assert(isByte(mode), "invalid value");
- InstructionMark im(this);
- emit_byte(0xF2);
- emit_byte(0x0F);
- emit_byte(0x70);
- emit_operand(dst, src);
- emit_byte(mode & 0xFF);
-}
-
-void Assembler::cmovl(Condition cc, Register dst, Register src) {
- int encode = prefix_and_encode(dst->encoding(), src->encoding());
- emit_byte(0x0F);
- emit_byte(0x40 | cc);
- emit_byte(0xC0 | encode);
-}
-
-void Assembler::cmovl(Condition cc, Register dst, Address src) {
- InstructionMark im(this);
- prefix(src, dst);
- emit_byte(0x0F);
- emit_byte(0x40 | cc);
- emit_operand(dst, src);
-}
-
-void Assembler::cmovq(Condition cc, Register dst, Register src) {
- int encode = prefixq_and_encode(dst->encoding(), src->encoding());
- emit_byte(0x0F);
- emit_byte(0x40 | cc);
- emit_byte(0xC0 | encode);
-}
-
-void Assembler::cmovq(Condition cc, Register dst, Address src) {
- InstructionMark im(this);
- prefixq(src, dst);
- emit_byte(0x0F);
- emit_byte(0x40 | cc);
- emit_operand(dst, src);
-}
-
-void Assembler::prefetch_prefix(Address src) {
- prefix(src);
- emit_byte(0x0F);
-}
-
-void Assembler::prefetcht0(Address src) {
- InstructionMark im(this);
- prefetch_prefix(src);
- emit_byte(0x18);
- emit_operand(rcx, src); // 1, src
-}
-
-void Assembler::prefetcht1(Address src) {
- InstructionMark im(this);
- prefetch_prefix(src);
- emit_byte(0x18);
- emit_operand(rdx, src); // 2, src
-}
-
-void Assembler::prefetcht2(Address src) {
- InstructionMark im(this);
- prefetch_prefix(src);
- emit_byte(0x18);
- emit_operand(rbx, src); // 3, src
-}
-
-void Assembler::prefetchnta(Address src) {
- InstructionMark im(this);
- prefetch_prefix(src);
- emit_byte(0x18);
- emit_operand(rax, src); // 0, src
-}
-
-void Assembler::prefetchw(Address src) {
- InstructionMark im(this);
- prefetch_prefix(src);
- emit_byte(0x0D);
- emit_operand(rcx, src); // 1, src
-}
-
-void Assembler::adcl(Register dst, int imm32) {
+void Assembler::adcl(Register dst, int32_t imm32) {
prefix(dst);
emit_arith(0x81, 0xD0, dst, imm32);
}
@@ -1755,27 +813,10 @@ void Assembler::adcl(Register dst, Register src) {
emit_arith(0x13, 0xC0, dst, src);
}
-void Assembler::adcq(Register dst, int imm32) {
- (void) prefixq_and_encode(dst->encoding());
- emit_arith(0x81, 0xD0, dst, imm32);
-}
-
-void Assembler::adcq(Register dst, Address src) {
- InstructionMark im(this);
- prefixq(src, dst);
- emit_byte(0x13);
- emit_operand(dst, src);
-}
-
-void Assembler::adcq(Register dst, Register src) {
- (int) prefixq_and_encode(dst->encoding(), src->encoding());
- emit_arith(0x13, 0xC0, dst, src);
-}
-
-void Assembler::addl(Address dst, int imm32) {
+void Assembler::addl(Address dst, int32_t imm32) {
InstructionMark im(this);
prefix(dst);
- emit_arith_operand(0x81, rax, dst,imm32);
+ emit_arith_operand(0x81, rax, dst, imm32);
}
void Assembler::addl(Address dst, Register src) {
@@ -1785,7 +826,7 @@ void Assembler::addl(Address dst, Register src) {
emit_operand(src, dst);
}
-void Assembler::addl(Register dst, int imm32) {
+void Assembler::addl(Register dst, int32_t imm32) {
prefix(dst);
emit_arith(0x81, 0xC0, dst, imm32);
}
@@ -1802,786 +843,6 @@ void Assembler::addl(Register dst, Register src) {
emit_arith(0x03, 0xC0, dst, src);
}
-void Assembler::addq(Address dst, int imm32) {
- InstructionMark im(this);
- prefixq(dst);
- emit_arith_operand(0x81, rax, dst,imm32);
-}
-
-void Assembler::addq(Address dst, Register src) {
- InstructionMark im(this);
- prefixq(dst, src);
- emit_byte(0x01);
- emit_operand(src, dst);
-}
-
-void Assembler::addq(Register dst, int imm32) {
- (void) prefixq_and_encode(dst->encoding());
- emit_arith(0x81, 0xC0, dst, imm32);
-}
-
-void Assembler::addq(Register dst, Address src) {
- InstructionMark im(this);
- prefixq(src, dst);
- emit_byte(0x03);
- emit_operand(dst, src);
-}
-
-void Assembler::addq(Register dst, Register src) {
- (void) prefixq_and_encode(dst->encoding(), src->encoding());
- emit_arith(0x03, 0xC0, dst, src);
-}
-
-void Assembler::andl(Register dst, int imm32) {
- prefix(dst);
- emit_arith(0x81, 0xE0, dst, imm32);
-}
-
-void Assembler::andl(Register dst, Address src) {
- InstructionMark im(this);
- prefix(src, dst);
- emit_byte(0x23);
- emit_operand(dst, src);
-}
-
-void Assembler::andl(Register dst, Register src) {
- (void) prefix_and_encode(dst->encoding(), src->encoding());
- emit_arith(0x23, 0xC0, dst, src);
-}
-
-void Assembler::andq(Register dst, int imm32) {
- (void) prefixq_and_encode(dst->encoding());
- emit_arith(0x81, 0xE0, dst, imm32);
-}
-
-void Assembler::andq(Register dst, Address src) {
- InstructionMark im(this);
- prefixq(src, dst);
- emit_byte(0x23);
- emit_operand(dst, src);
-}
-
-void Assembler::andq(Register dst, Register src) {
- (int) prefixq_and_encode(dst->encoding(), src->encoding());
- emit_arith(0x23, 0xC0, dst, src);
-}
-
-void Assembler::cmpb(Address dst, int imm8) {
- InstructionMark im(this);
- prefix(dst);
- emit_byte(0x80);
- emit_operand(rdi, dst, 1);
- emit_byte(imm8);
-}
-
-void Assembler::cmpl(Address dst, int imm32) {
- InstructionMark im(this);
- prefix(dst);
- emit_byte(0x81);
- emit_operand(rdi, dst, 4);
- emit_long(imm32);
-}
-
-void Assembler::cmpl(Register dst, int imm32) {
- prefix(dst);
- emit_arith(0x81, 0xF8, dst, imm32);
-}
-
-void Assembler::cmpl(Register dst, Register src) {
- (void) prefix_and_encode(dst->encoding(), src->encoding());
- emit_arith(0x3B, 0xC0, dst, src);
-}
-
-void Assembler::cmpl(Register dst, Address src) {
- InstructionMark im(this);
- prefix(src, dst);
- emit_byte(0x3B);
- emit_operand(dst, src);
-}
-
-void Assembler::cmpq(Address dst, int imm32) {
- InstructionMark im(this);
- prefixq(dst);
- emit_byte(0x81);
- emit_operand(rdi, dst, 4);
- emit_long(imm32);
-}
-
-void Assembler::cmpq(Register dst, int imm32) {
- (void) prefixq_and_encode(dst->encoding());
- emit_arith(0x81, 0xF8, dst, imm32);
-}
-
-void Assembler::cmpq(Address dst, Register src) {
- prefixq(dst, src);
- emit_byte(0x3B);
- emit_operand(src, dst);
-}
-
-void Assembler::cmpq(Register dst, Register src) {
- (void) prefixq_and_encode(dst->encoding(), src->encoding());
- emit_arith(0x3B, 0xC0, dst, src);
-}
-
-void Assembler::cmpq(Register dst, Address src) {
- InstructionMark im(this);
- prefixq(src, dst);
- emit_byte(0x3B);
- emit_operand(dst, src);
-}
-
-void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
- int encode = prefix_and_encode(dst->encoding(), src->encoding());
- emit_byte(0x0F);
- emit_byte(0x2E);
- emit_byte(0xC0 | encode);
-}
-
-void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
- emit_byte(0x66);
- ucomiss(dst, src);
-}
-
-void Assembler::decl(Register dst) {
- // Don't use it directly. Use MacroAssembler::decrementl() instead.
- // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
- int encode = prefix_and_encode(dst->encoding());
- emit_byte(0xFF);
- emit_byte(0xC8 | encode);
-}
-
-void Assembler::decl(Address dst) {
- // Don't use it directly. Use MacroAssembler::decrementl() instead.
- InstructionMark im(this);
- prefix(dst);
- emit_byte(0xFF);
- emit_operand(rcx, dst);
-}
-
-void Assembler::decq(Register dst) {
- // Don't use it directly. Use MacroAssembler::decrementq() instead.
- // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
- int encode = prefixq_and_encode(dst->encoding());
- emit_byte(0xFF);
- emit_byte(0xC8 | encode);
-}
-
-void Assembler::decq(Address dst) {
- // Don't use it directly. Use MacroAssembler::decrementq() instead.
- InstructionMark im(this);
- prefixq(dst);
- emit_byte(0xFF);
- emit_operand(rcx, dst);
-}
-
-void Assembler::idivl(Register src) {
- int encode = prefix_and_encode(src->encoding());
- emit_byte(0xF7);
- emit_byte(0xF8 | encode);
-}
-
-void Assembler::idivq(Register src) {
- int encode = prefixq_and_encode(src->encoding());
- emit_byte(0xF7);
- emit_byte(0xF8 | encode);
-}
-
-void Assembler::cdql() {
- emit_byte(0x99);
-}
-
-void Assembler::cdqq() {
- prefix(REX_W);
- emit_byte(0x99);
-}
-
-void Assembler::imull(Register dst, Register src) {
- int encode = prefix_and_encode(dst->encoding(), src->encoding());
- emit_byte(0x0F);
- emit_byte(0xAF);
- emit_byte(0xC0 | encode);
-}
-
-void Assembler::imull(Register dst, Register src, int value) {
- int encode = prefix_and_encode(dst->encoding(), src->encoding());
- if (is8bit(value)) {
- emit_byte(0x6B);
- emit_byte(0xC0 | encode);
- emit_byte(value);
- } else {
- emit_byte(0x69);
- emit_byte(0xC0 | encode);
- emit_long(value);
- }
-}
-
-void Assembler::imulq(Register dst, Register src) {
- int encode = prefixq_and_encode(dst->encoding(), src->encoding());
- emit_byte(0x0F);
- emit_byte(0xAF);
- emit_byte(0xC0 | encode);
-}
-
-void Assembler::imulq(Register dst, Register src, int value) {
- int encode = prefixq_and_encode(dst->encoding(), src->encoding());
- if (is8bit(value)) {
- emit_byte(0x6B);
- emit_byte(0xC0 | encode);
- emit_byte(value);
- } else {
- emit_byte(0x69);
- emit_byte(0xC0 | encode);
- emit_long(value);
- }
-}
-
-void Assembler::incl(Register dst) {
- // Don't use it directly. Use MacroAssembler::incrementl() instead.
- // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
- int encode = prefix_and_encode(dst->encoding());
- emit_byte(0xFF);
- emit_byte(0xC0 | encode);
-}
-
-void Assembler::incl(Address dst) {
- // Don't use it directly. Use MacroAssembler::incrementl() instead.
- InstructionMark im(this);
- prefix(dst);
- emit_byte(0xFF);
- emit_operand(rax, dst);
-}
-
-void Assembler::incq(Register dst) {
- // Don't use it directly. Use MacroAssembler::incrementq() instead.
- // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
- int encode = prefixq_and_encode(dst->encoding());
- emit_byte(0xFF);
- emit_byte(0xC0 | encode);
-}
-
-void Assembler::incq(Address dst) {
- // Don't use it directly. Use MacroAssembler::incrementq() instead.
- InstructionMark im(this);
- prefixq(dst);
- emit_byte(0xFF);
- emit_operand(rax, dst);
-}
-
-void Assembler::leal(Register dst, Address src) {
- InstructionMark im(this);
- emit_byte(0x67); // addr32
- prefix(src, dst);
- emit_byte(0x8D);
- emit_operand(dst, src);
-}
-
-void Assembler::leaq(Register dst, Address src) {
- InstructionMark im(this);
- prefixq(src, dst);
- emit_byte(0x8D);
- emit_operand(dst, src);
-}
-
-void Assembler::mull(Address src) {
- InstructionMark im(this);
- // was missing
- prefix(src);
- emit_byte(0xF7);
- emit_operand(rsp, src);
-}
-
-void Assembler::mull(Register src) {
- // was missing
- int encode = prefix_and_encode(src->encoding());
- emit_byte(0xF7);
- emit_byte(0xE0 | encode);
-}
-
-void Assembler::negl(Register dst) {
- int encode = prefix_and_encode(dst->encoding());
- emit_byte(0xF7);
- emit_byte(0xD8 | encode);
-}
-
-void Assembler::negq(Register dst) {
- int encode = prefixq_and_encode(dst->encoding());
- emit_byte(0xF7);
- emit_byte(0xD8 | encode);
-}
-
-void Assembler::notl(Register dst) {
- int encode = prefix_and_encode(dst->encoding());
- emit_byte(0xF7);
- emit_byte(0xD0 | encode);
-}
-
-void Assembler::notq(Register dst) {
- int encode = prefixq_and_encode(dst->encoding());
- emit_byte(0xF7);
- emit_byte(0xD0 | encode);
-}
-
-void Assembler::orl(Address dst, int imm32) {
- InstructionMark im(this);
- prefix(dst);
- emit_byte(0x81);
- emit_operand(rcx, dst, 4);
- emit_long(imm32);
-}
-
-void Assembler::orl(Register dst, int imm32) {
- prefix(dst);
- emit_arith(0x81, 0xC8, dst, imm32);
-}
-
-void Assembler::orl(Register dst, Address src) {
- InstructionMark im(this);
- prefix(src, dst);
- emit_byte(0x0B);
- emit_operand(dst, src);
-}
-
-void Assembler::orl(Register dst, Register src) {
- (void) prefix_and_encode(dst->encoding(), src->encoding());
- emit_arith(0x0B, 0xC0, dst, src);
-}
-
-void Assembler::orq(Address dst, int imm32) {
- InstructionMark im(this);
- prefixq(dst);
- emit_byte(0x81);
- emit_operand(rcx, dst, 4);
- emit_long(imm32);
-}
-
-void Assembler::orq(Register dst, int imm32) {
- (void) prefixq_and_encode(dst->encoding());
- emit_arith(0x81, 0xC8, dst, imm32);
-}
-
-void Assembler::orq(Register dst, Address src) {
- InstructionMark im(this);
- prefixq(src, dst);
- emit_byte(0x0B);
- emit_operand(dst, src);
-}
-
-void Assembler::orq(Register dst, Register src) {
- (void) prefixq_and_encode(dst->encoding(), src->encoding());
- emit_arith(0x0B, 0xC0, dst, src);
-}
-
-void Assembler::rcll(Register dst, int imm8) {
- assert(isShiftCount(imm8), "illegal shift count");
- int encode = prefix_and_encode(dst->encoding());
- if (imm8 == 1) {
- emit_byte(0xD1);
- emit_byte(0xD0 | encode);
- } else {
- emit_byte(0xC1);
- emit_byte(0xD0 | encode);
- emit_byte(imm8);
- }
-}
-
-void Assembler::rclq(Register dst, int imm8) {
- assert(isShiftCount(imm8 >> 1), "illegal shift count");
- int encode = prefixq_and_encode(dst->encoding());
- if (imm8 == 1) {
- emit_byte(0xD1);
- emit_byte(0xD0 | encode);
- } else {
- emit_byte(0xC1);
- emit_byte(0xD0 | encode);
- emit_byte(imm8);
- }
-}
-
-void Assembler::sarl(Register dst, int imm8) {
- int encode = prefix_and_encode(dst->encoding());
- assert(isShiftCount(imm8), "illegal shift count");
- if (imm8 == 1) {
- emit_byte(0xD1);
- emit_byte(0xF8 | encode);
- } else {
- emit_byte(0xC1);
- emit_byte(0xF8 | encode);
- emit_byte(imm8);
- }
-}
-
-void Assembler::sarl(Register dst) {
- int encode = prefix_and_encode(dst->encoding());
- emit_byte(0xD3);
- emit_byte(0xF8 | encode);
-}
-
-void Assembler::sarq(Register dst, int imm8) {
- assert(isShiftCount(imm8 >> 1), "illegal shift count");
- int encode = prefixq_and_encode(dst->encoding());
- if (imm8 == 1) {
- emit_byte(0xD1);
- emit_byte(0xF8 | encode);
- } else {
- emit_byte(0xC1);
- emit_byte(0xF8 | encode);
- emit_byte(imm8);
- }
-}
-
-void Assembler::sarq(Register dst) {
- int encode = prefixq_and_encode(dst->encoding());
- emit_byte(0xD3);
- emit_byte(0xF8 | encode);
-}
-
-void Assembler::sbbl(Address dst, int imm32) {
- InstructionMark im(this);
- prefix(dst);
- emit_arith_operand(0x81, rbx, dst, imm32);
-}
-
-void Assembler::sbbl(Register dst, int imm32) {
- prefix(dst);
- emit_arith(0x81, 0xD8, dst, imm32);
-}
-
-void Assembler::sbbl(Register dst, Address src) {
- InstructionMark im(this);
- prefix(src, dst);
- emit_byte(0x1B);
- emit_operand(dst, src);
-}
-
-void Assembler::sbbl(Register dst, Register src) {
- (void) prefix_and_encode(dst->encoding(), src->encoding());
- emit_arith(0x1B, 0xC0, dst, src);
-}
-
-void Assembler::sbbq(Address dst, int imm32) {
- InstructionMark im(this);
- prefixq(dst);
- emit_arith_operand(0x81, rbx, dst, imm32);
-}
-
-void Assembler::sbbq(Register dst, int imm32) {
- (void) prefixq_and_encode(dst->encoding());
- emit_arith(0x81, 0xD8, dst, imm32);
-}
-
-void Assembler::sbbq(Register dst, Address src) {
- InstructionMark im(this);
- prefixq(src, dst);
- emit_byte(0x1B);
- emit_operand(dst, src);
-}
-
-void Assembler::sbbq(Register dst, Register src) {
- (void) prefixq_and_encode(dst->encoding(), src->encoding());
- emit_arith(0x1B, 0xC0, dst, src);
-}
-
-void Assembler::shll(Register dst, int imm8) {
- assert(isShiftCount(imm8), "illegal shift count");
- int encode = prefix_and_encode(dst->encoding());
- if (imm8 == 1 ) {
- emit_byte(0xD1);
- emit_byte(0xE0 | encode);
- } else {
- emit_byte(0xC1);
- emit_byte(0xE0 | encode);
- emit_byte(imm8);
- }
-}
-
-void Assembler::shll(Register dst) {
- int encode = prefix_and_encode(dst->encoding());
- emit_byte(0xD3);
- emit_byte(0xE0 | encode);
-}
-
-void Assembler::shlq(Register dst, int imm8) {
- assert(isShiftCount(imm8 >> 1), "illegal shift count");
- int encode = prefixq_and_encode(dst->encoding());
- if (imm8 == 1) {
- emit_byte(0xD1);
- emit_byte(0xE0 | encode);
- } else {
- emit_byte(0xC1);
- emit_byte(0xE0 | encode);
- emit_byte(imm8);
- }
-}
-
-void Assembler::shlq(Register dst) {
- int encode = prefixq_and_encode(dst->encoding());
- emit_byte(0xD3);
- emit_byte(0xE0 | encode);
-}
-
-void Assembler::shrl(Register dst, int imm8) {
- assert(isShiftCount(imm8), "illegal shift count");
- int encode = prefix_and_encode(dst->encoding());
- emit_byte(0xC1);
- emit_byte(0xE8 | encode);
- emit_byte(imm8);
-}
-
-void Assembler::shrl(Register dst) {
- int encode = prefix_and_encode(dst->encoding());
- emit_byte(0xD3);
- emit_byte(0xE8 | encode);
-}
-
-void Assembler::shrq(Register dst, int imm8) {
- assert(isShiftCount(imm8 >> 1), "illegal shift count");
- int encode = prefixq_and_encode(dst->encoding());
- emit_byte(0xC1);
- emit_byte(0xE8 | encode);
- emit_byte(imm8);
-}
-
-void Assembler::shrq(Register dst) {
- int encode = prefixq_and_encode(dst->encoding());
- emit_byte(0xD3);
- emit_byte(0xE8 | encode);
-}
-
-void Assembler::subl(Address dst, int imm32) {
- InstructionMark im(this);
- prefix(dst);
- if (is8bit(imm32)) {
- emit_byte(0x83);
- emit_operand(rbp, dst, 1);
- emit_byte(imm32 & 0xFF);
- } else {
- emit_byte(0x81);
- emit_operand(rbp, dst, 4);
- emit_long(imm32);
- }
-}
-
-void Assembler::subl(Register dst, int imm32) {
- prefix(dst);
- emit_arith(0x81, 0xE8, dst, imm32);
-}
-
-void Assembler::subl(Address dst, Register src) {
- InstructionMark im(this);
- prefix(dst, src);
- emit_byte(0x29);
- emit_operand(src, dst);
-}
-
-void Assembler::subl(Register dst, Address src) {
- InstructionMark im(this);
- prefix(src, dst);
- emit_byte(0x2B);
- emit_operand(dst, src);
-}
-
-void Assembler::subl(Register dst, Register src) {
- (void) prefix_and_encode(dst->encoding(), src->encoding());
- emit_arith(0x2B, 0xC0, dst, src);
-}
-
-void Assembler::subq(Address dst, int imm32) {
- InstructionMark im(this);
- prefixq(dst);
- if (is8bit(imm32)) {
- emit_byte(0x83);
- emit_operand(rbp, dst, 1);
- emit_byte(imm32 & 0xFF);
- } else {
- emit_byte(0x81);
- emit_operand(rbp, dst, 4);
- emit_long(imm32);
- }
-}
-
-void Assembler::subq(Register dst, int imm32) {
- (void) prefixq_and_encode(dst->encoding());
- emit_arith(0x81, 0xE8, dst, imm32);
-}
-
-void Assembler::subq(Address dst, Register src) {
- InstructionMark im(this);
- prefixq(dst, src);
- emit_byte(0x29);
- emit_operand(src, dst);
-}
-
-void Assembler::subq(Register dst, Address src) {
- InstructionMark im(this);
- prefixq(src, dst);
- emit_byte(0x2B);
- emit_operand(dst, src);
-}
-
-void Assembler::subq(Register dst, Register src) {
- (void) prefixq_and_encode(dst->encoding(), src->encoding());
- emit_arith(0x2B, 0xC0, dst, src);
-}
-
-void Assembler::testb(Register dst, int imm8) {
- (void) prefix_and_encode(dst->encoding(), true);
- emit_arith_b(0xF6, 0xC0, dst, imm8);
-}
-
-void Assembler::testl(Register dst, int imm32) {
- // not using emit_arith because test
- // doesn't support sign-extension of
- // 8bit operands
- int encode = dst->encoding();
- if (encode == 0) {
- emit_byte(0xA9);
- } else {
- encode = prefix_and_encode(encode);
- emit_byte(0xF7);
- emit_byte(0xC0 | encode);
- }
- emit_long(imm32);
-}
-
-void Assembler::testl(Register dst, Register src) {
- (void) prefix_and_encode(dst->encoding(), src->encoding());
- emit_arith(0x85, 0xC0, dst, src);
-}
-
-void Assembler::testq(Register dst, int imm32) {
- // not using emit_arith because test
- // doesn't support sign-extension of
- // 8bit operands
- int encode = dst->encoding();
- if (encode == 0) {
- prefix(REX_W);
- emit_byte(0xA9);
- } else {
- encode = prefixq_and_encode(encode);
- emit_byte(0xF7);
- emit_byte(0xC0 | encode);
- }
- emit_long(imm32);
-}
-
-void Assembler::testq(Register dst, Register src) {
- (void) prefixq_and_encode(dst->encoding(), src->encoding());
- emit_arith(0x85, 0xC0, dst, src);
-}
-
-void Assembler::xaddl(Address dst, Register src) {
- InstructionMark im(this);
- prefix(dst, src);
- emit_byte(0x0F);
- emit_byte(0xC1);
- emit_operand(src, dst);
-}
-
-void Assembler::xaddq(Address dst, Register src) {
- InstructionMark im(this);
- prefixq(dst, src);
- emit_byte(0x0F);
- emit_byte(0xC1);
- emit_operand(src, dst);
-}
-
-void Assembler::xorl(Register dst, int imm32) {
- prefix(dst);
- emit_arith(0x81, 0xF0, dst, imm32);
-}
-
-void Assembler::xorl(Register dst, Register src) {
- (void) prefix_and_encode(dst->encoding(), src->encoding());
- emit_arith(0x33, 0xC0, dst, src);
-}
-
-void Assembler::xorl(Register dst, Address src) {
- InstructionMark im(this);
- prefix(src, dst);
- emit_byte(0x33);
- emit_operand(dst, src);
-}
-
-void Assembler::xorq(Register dst, int imm32) {
- (void) prefixq_and_encode(dst->encoding());
- emit_arith(0x81, 0xF0, dst, imm32);
-}
-
-void Assembler::xorq(Register dst, Register src) {
- (void) prefixq_and_encode(dst->encoding(), src->encoding());
- emit_arith(0x33, 0xC0, dst, src);
-}
-
-void Assembler::xorq(Register dst, Address src) {
- InstructionMark im(this);
- prefixq(src, dst);
- emit_byte(0x33);
- emit_operand(dst, src);
-}
-
-void Assembler::bswapl(Register reg) {
- int encode = prefix_and_encode(reg->encoding());
- emit_byte(0x0F);
- emit_byte(0xC8 | encode);
-}
-
-void Assembler::bswapq(Register reg) {
- int encode = prefixq_and_encode(reg->encoding());
- emit_byte(0x0F);
- emit_byte(0xC8 | encode);
-}
-
-void Assembler::lock() {
- emit_byte(0xF0);
-}
-
-void Assembler::xchgl(Register dst, Address src) {
- InstructionMark im(this);
- prefix(src, dst);
- emit_byte(0x87);
- emit_operand(dst, src);
-}
-
-void Assembler::xchgl(Register dst, Register src) {
- int encode = prefix_and_encode(dst->encoding(), src->encoding());
- emit_byte(0x87);
- emit_byte(0xc0 | encode);
-}
-
-void Assembler::xchgq(Register dst, Address src) {
- InstructionMark im(this);
- prefixq(src, dst);
- emit_byte(0x87);
- emit_operand(dst, src);
-}
-
-void Assembler::xchgq(Register dst, Register src) {
- int encode = prefixq_and_encode(dst->encoding(), src->encoding());
- emit_byte(0x87);
- emit_byte(0xc0 | encode);
-}
-
-void Assembler::cmpxchgl(Register reg, Address adr) {
- InstructionMark im(this);
- prefix(adr, reg);
- emit_byte(0x0F);
- emit_byte(0xB1);
- emit_operand(reg, adr);
-}
-
-void Assembler::cmpxchgq(Register reg, Address adr) {
- InstructionMark im(this);
- prefixq(adr, reg);
- emit_byte(0x0F);
- emit_byte(0xB1);
- emit_operand(reg, adr);
-}
-
-void Assembler::hlt() {
- emit_byte(0xF4);
-}
-
-
void Assembler::addr_nop_4() {
// 4 bytes: NOP DWORD PTR [EAX+0]
emit_byte(0x0F);
@@ -2616,8 +877,1009 @@ void Assembler::addr_nop_8() {
emit_long(0); // 32-bits offset (4 bytes)
}
+void Assembler::addsd(XMMRegister dst, XMMRegister src) {
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ emit_byte(0xF2);
+ int encode = prefix_and_encode(dst->encoding(), src->encoding());
+ emit_byte(0x0F);
+ emit_byte(0x58);
+ emit_byte(0xC0 | encode);
+}
+
+void Assembler::addsd(XMMRegister dst, Address src) {
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ InstructionMark im(this);
+ emit_byte(0xF2);
+ prefix(src, dst);
+ emit_byte(0x0F);
+ emit_byte(0x58);
+ emit_operand(dst, src);
+}
+
+void Assembler::addss(XMMRegister dst, XMMRegister src) {
+ NOT_LP64(assert(VM_Version::supports_sse(), ""));
+ emit_byte(0xF3);
+ int encode = prefix_and_encode(dst->encoding(), src->encoding());
+ emit_byte(0x0F);
+ emit_byte(0x58);
+ emit_byte(0xC0 | encode);
+}
+
+void Assembler::addss(XMMRegister dst, Address src) {
+ NOT_LP64(assert(VM_Version::supports_sse(), ""));
+ InstructionMark im(this);
+ emit_byte(0xF3);
+ prefix(src, dst);
+ emit_byte(0x0F);
+ emit_byte(0x58);
+ emit_operand(dst, src);
+}
+
+void Assembler::andl(Register dst, int32_t imm32) {
+ prefix(dst);
+ emit_arith(0x81, 0xE0, dst, imm32);
+}
+
+void Assembler::andl(Register dst, Address src) {
+ InstructionMark im(this);
+ prefix(src, dst);
+ emit_byte(0x23);
+ emit_operand(dst, src);
+}
+
+void Assembler::andl(Register dst, Register src) {
+ (void) prefix_and_encode(dst->encoding(), src->encoding());
+ emit_arith(0x23, 0xC0, dst, src);
+}
+
+void Assembler::andpd(XMMRegister dst, Address src) {
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ InstructionMark im(this);
+ emit_byte(0x66);
+ prefix(src, dst);
+ emit_byte(0x0F);
+ emit_byte(0x54);
+ emit_operand(dst, src);
+}
+
+void Assembler::bswapl(Register reg) { // bswap
+ int encode = prefix_and_encode(reg->encoding());
+ emit_byte(0x0F);
+ emit_byte(0xC8 | encode);
+}
+
+void Assembler::call(Label& L, relocInfo::relocType rtype) {
+ // suspect disp32 is always good
+ int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
+
+ if (L.is_bound()) {
+ const int long_size = 5;
+ int offs = (int)( target(L) - pc() );
+ assert(offs <= 0, "assembler error");
+ InstructionMark im(this);
+ // 1110 1000 #32-bit disp
+ emit_byte(0xE8);
+ emit_data(offs - long_size, rtype, operand);
+ } else {
+ InstructionMark im(this);
+ // 1110 1000 #32-bit disp
+ L.add_patch_at(code(), locator());
+
+ emit_byte(0xE8);
+ emit_data(int(0), rtype, operand);
+ }
+}
+
+void Assembler::call(Register dst) {
+ // This was originally using a 32bit register encoding
+ // and surely we want 64bit!
+ // this is a 32bit encoding but in 64bit mode the default
+ // operand size is 64bit so there is no need for the
+ // wide prefix. So prefix only happens if we use the
+ // new registers. Much like push/pop.
+ int x = offset();
+ // this may be true but dbx disassembles it as if it
+ // were 32bits...
+ // int encode = prefix_and_encode(dst->encoding());
+ // if (offset() != x) assert(dst->encoding() >= 8, "what?");
+ int encode = prefixq_and_encode(dst->encoding());
+
+ emit_byte(0xFF);
+ emit_byte(0xD0 | encode);
+}
+
+
+void Assembler::call(Address adr) {
+ InstructionMark im(this);
+ prefix(adr);
+ emit_byte(0xFF);
+ emit_operand(rdx, adr);
+}
+
+void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
+ assert(entry != NULL, "call most probably wrong");
+ InstructionMark im(this);
+ emit_byte(0xE8);
+ intptr_t disp = entry - (_code_pos + sizeof(int32_t));
+ assert(is_simm32(disp), "must be 32bit offset (call2)");
+ // Technically, should use call32_operand, but this format is
+ // implied by the fact that we're emitting a call instruction.
+
+ int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
+ emit_data((int) disp, rspec, operand);
+}
+
+void Assembler::cdql() {
+ emit_byte(0x99);
+}
+
+void Assembler::cmovl(Condition cc, Register dst, Register src) {
+ NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
+ int encode = prefix_and_encode(dst->encoding(), src->encoding());
+ emit_byte(0x0F);
+ emit_byte(0x40 | cc);
+ emit_byte(0xC0 | encode);
+}
+
+
+void Assembler::cmovl(Condition cc, Register dst, Address src) {
+ NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
+ prefix(src, dst);
+ emit_byte(0x0F);
+ emit_byte(0x40 | cc);
+ emit_operand(dst, src);
+}
+
+void Assembler::cmpb(Address dst, int imm8) {
+ InstructionMark im(this);
+ prefix(dst);
+ emit_byte(0x80);
+ emit_operand(rdi, dst, 1);
+ emit_byte(imm8);
+}
+
+void Assembler::cmpl(Address dst, int32_t imm32) {
+ InstructionMark im(this);
+ prefix(dst);
+ emit_byte(0x81);
+ emit_operand(rdi, dst, 4);
+ emit_long(imm32);
+}
+
+void Assembler::cmpl(Register dst, int32_t imm32) {
+ prefix(dst);
+ emit_arith(0x81, 0xF8, dst, imm32);
+}
+
+void Assembler::cmpl(Register dst, Register src) {
+ (void) prefix_and_encode(dst->encoding(), src->encoding());
+ emit_arith(0x3B, 0xC0, dst, src);
+}
+
+
+void Assembler::cmpl(Register dst, Address src) {
+ InstructionMark im(this);
+ prefix(src, dst);
+ emit_byte(0x3B);
+ emit_operand(dst, src);
+}
+
+void Assembler::cmpw(Address dst, int imm16) {
+ InstructionMark im(this);
+ assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
+ emit_byte(0x66);
+ emit_byte(0x81);
+ emit_operand(rdi, dst, 2);
+ emit_word(imm16);
+}
+
+// The 32-bit cmpxchg compares the value at adr with the contents of rax,
+// and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
+// The ZF is set if the compared values were equal, and cleared otherwise.
+void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
+ if (Atomics & 2) {
+ // caveat: no instructionmark, so this isn't relocatable.
+ // Emit a synthetic, non-atomic, CAS equivalent.
+ // Beware. The synthetic form sets all ICCs, not just ZF.
+ // cmpxchg r,[m] is equivalent to rax, = CAS (m, rax, r)
+ cmpl(rax, adr);
+ movl(rax, adr);
+ if (reg != rax) {
+ Label L ;
+ jcc(Assembler::notEqual, L);
+ movl(adr, reg);
+ bind(L);
+ }
+ } else {
+ InstructionMark im(this);
+ prefix(adr, reg);
+ emit_byte(0x0F);
+ emit_byte(0xB1);
+ emit_operand(reg, adr);
+ }
+}
+
+void Assembler::comisd(XMMRegister dst, Address src) {
+ // NOTE: dbx seems to decode this as comiss even though the
+ // 0x66 is there. Strangly ucomisd comes out correct
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ emit_byte(0x66);
+ comiss(dst, src);
+}
+
+void Assembler::comiss(XMMRegister dst, Address src) {
+ NOT_LP64(assert(VM_Version::supports_sse(), ""));
+
+ InstructionMark im(this);
+ prefix(src, dst);
+ emit_byte(0x0F);
+ emit_byte(0x2F);
+ emit_operand(dst, src);
+}
+
+void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ emit_byte(0xF3);
+ int encode = prefix_and_encode(dst->encoding(), src->encoding());
+ emit_byte(0x0F);
+ emit_byte(0xE6);
+ emit_byte(0xC0 | encode);
+}
+
+void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ int encode = prefix_and_encode(dst->encoding(), src->encoding());
+ emit_byte(0x0F);
+ emit_byte(0x5B);
+ emit_byte(0xC0 | encode);
+}
+
+void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ emit_byte(0xF2);
+ int encode = prefix_and_encode(dst->encoding(), src->encoding());
+ emit_byte(0x0F);
+ emit_byte(0x5A);
+ emit_byte(0xC0 | encode);
+}
+
+void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ emit_byte(0xF2);
+ int encode = prefix_and_encode(dst->encoding(), src->encoding());
+ emit_byte(0x0F);
+ emit_byte(0x2A);
+ emit_byte(0xC0 | encode);
+}
+
+void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
+ NOT_LP64(assert(VM_Version::supports_sse(), ""));
+ emit_byte(0xF3);
+ int encode = prefix_and_encode(dst->encoding(), src->encoding());
+ emit_byte(0x0F);
+ emit_byte(0x2A);
+ emit_byte(0xC0 | encode);
+}
+
+void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ emit_byte(0xF3);
+ int encode = prefix_and_encode(dst->encoding(), src->encoding());
+ emit_byte(0x0F);
+ emit_byte(0x5A);
+ emit_byte(0xC0 | encode);
+}
+
+void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ emit_byte(0xF2);
+ int encode = prefix_and_encode(dst->encoding(), src->encoding());
+ emit_byte(0x0F);
+ emit_byte(0x2C);
+ emit_byte(0xC0 | encode);
+}
+
+void Assembler::cvttss2sil(Register dst, XMMRegister src) {
+ NOT_LP64(assert(VM_Version::supports_sse(), ""));
+ emit_byte(0xF3);
+ int encode = prefix_and_encode(dst->encoding(), src->encoding());
+ emit_byte(0x0F);
+ emit_byte(0x2C);
+ emit_byte(0xC0 | encode);
+}
+
+void Assembler::decl(Address dst) {
+ // Don't use it directly. Use MacroAssembler::decrement() instead.
+ InstructionMark im(this);
+ prefix(dst);
+ emit_byte(0xFF);
+ emit_operand(rcx, dst);
+}
+
+void Assembler::divsd(XMMRegister dst, Address src) {
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ InstructionMark im(this);
+ emit_byte(0xF2);
+ prefix(src, dst);
+ emit_byte(0x0F);
+ emit_byte(0x5E);
+ emit_operand(dst, src);
+}
+
+void Assembler::divsd(XMMRegister dst, XMMRegister src) {
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ emit_byte(0xF2);
+ int encode = prefix_and_encode(dst->encoding(), src->encoding());
+ emit_byte(0x0F);
+ emit_byte(0x5E);
+ emit_byte(0xC0 | encode);
+}
+
+void Assembler::divss(XMMRegister dst, Address src) {
+ NOT_LP64(assert(VM_Version::supports_sse(), ""));
+ InstructionMark im(this);
+ emit_byte(0xF3);
+ prefix(src, dst);
+ emit_byte(0x0F);
+ emit_byte(0x5E);
+ emit_operand(dst, src);
+}
+
+void Assembler::divss(XMMRegister dst, XMMRegister src) {
+ NOT_LP64(assert(VM_Version::supports_sse(), ""));
+ emit_byte(0xF3);
+ int encode = prefix_and_encode(dst->encoding(), src->encoding());
+ emit_byte(0x0F);
+ emit_byte(0x5E);
+ emit_byte(0xC0 | encode);
+}
+
+void Assembler::emms() {
+ NOT_LP64(assert(VM_Version::supports_mmx(), ""));
+ emit_byte(0x0F);
+ emit_byte(0x77);
+}
+
+void Assembler::hlt() {
+ emit_byte(0xF4);
+}
+
+void Assembler::idivl(Register src) {
+ int encode = prefix_and_encode(src->encoding());
+ emit_byte(0xF7);
+ emit_byte(0xF8 | encode);
+}
+
+void Assembler::imull(Register dst, Register src) {
+ int encode = prefix_and_encode(dst->encoding(), src->encoding());
+ emit_byte(0x0F);
+ emit_byte(0xAF);
+ emit_byte(0xC0 | encode);
+}
+
+
+void Assembler::imull(Register dst, Register src, int value) {
+ int encode = prefix_and_encode(dst->encoding(), src->encoding());
+ if (is8bit(value)) {
+ emit_byte(0x6B);
+ emit_byte(0xC0 | encode);
+ emit_byte(value);
+ } else {
+ emit_byte(0x69);
+ emit_byte(0xC0 | encode);
+ emit_long(value);
+ }
+}
+
+void Assembler::incl(Address dst) {
+ // Don't use it directly. Use MacroAssembler::increment() instead.
+ InstructionMark im(this);
+ prefix(dst);
+ emit_byte(0xFF);
+ emit_operand(rax, dst);
+}
+
+void Assembler::jcc(Condition cc, Label& L, relocInfo::relocType rtype) {
+ InstructionMark im(this);
+ relocate(rtype);
+ assert((0 <= cc) && (cc < 16), "illegal cc");
+ if (L.is_bound()) {
+ address dst = target(L);
+ assert(dst != NULL, "jcc most probably wrong");
+
+ const int short_size = 2;
+ const int long_size = 6;
+ intptr_t offs = (intptr_t)dst - (intptr_t)_code_pos;
+ if (rtype == relocInfo::none && is8bit(offs - short_size)) {
+ // 0111 tttn #8-bit disp
+ emit_byte(0x70 | cc);
+ emit_byte((offs - short_size) & 0xFF);
+ } else {
+ // 0000 1111 1000 tttn #32-bit disp
+ assert(is_simm32(offs - long_size),
+ "must be 32bit offset (call4)");
+ emit_byte(0x0F);
+ emit_byte(0x80 | cc);
+ emit_long(offs - long_size);
+ }
+ } else {
+ // Note: could eliminate cond. jumps to this jump if condition
+ // is the same however, seems to be rather unlikely case.
+ // Note: use jccb() if label to be bound is very close to get
+ // an 8-bit displacement
+ L.add_patch_at(code(), locator());
+ emit_byte(0x0F);
+ emit_byte(0x80 | cc);
+ emit_long(0);
+ }
+}
+
+void Assembler::jccb(Condition cc, Label& L) {
+ if (L.is_bound()) {
+ const int short_size = 2;
+ address entry = target(L);
+ assert(is8bit((intptr_t)entry - ((intptr_t)_code_pos + short_size)),
+ "Dispacement too large for a short jmp");
+ intptr_t offs = (intptr_t)entry - (intptr_t)_code_pos;
+ // 0111 tttn #8-bit disp
+ emit_byte(0x70 | cc);
+ emit_byte((offs - short_size) & 0xFF);
+ } else {
+ InstructionMark im(this);
+ L.add_patch_at(code(), locator());
+ emit_byte(0x70 | cc);
+ emit_byte(0);
+ }
+}
+
+void Assembler::jmp(Address adr) {
+ InstructionMark im(this);
+ prefix(adr);
+ emit_byte(0xFF);
+ emit_operand(rsp, adr);
+}
+
+void Assembler::jmp(Label& L, relocInfo::relocType rtype) {
+ if (L.is_bound()) {
+ address entry = target(L);
+ assert(entry != NULL, "jmp most probably wrong");
+ InstructionMark im(this);
+ const int short_size = 2;
+ const int long_size = 5;
+ intptr_t offs = entry - _code_pos;
+ if (rtype == relocInfo::none && is8bit(offs - short_size)) {
+ emit_byte(0xEB);
+ emit_byte((offs - short_size) & 0xFF);
+ } else {
+ emit_byte(0xE9);
+ emit_long(offs - long_size);
+ }
+ } else {
+ // By default, forward jumps are always 32-bit displacements, since
+ // we can't yet know where the label will be bound. If you're sure that
+ // the forward jump will not run beyond 256 bytes, use jmpb to
+ // force an 8-bit displacement.
+ InstructionMark im(this);
+ relocate(rtype);
+ L.add_patch_at(code(), locator());
+ emit_byte(0xE9);
+ emit_long(0);
+ }
+}
+
+void Assembler::jmp(Register entry) {
+ int encode = prefix_and_encode(entry->encoding());
+ emit_byte(0xFF);
+ emit_byte(0xE0 | encode);
+}
+
+void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
+ InstructionMark im(this);
+ emit_byte(0xE9);
+ assert(dest != NULL, "must have a target");
+ intptr_t disp = dest - (_code_pos + sizeof(int32_t));
+ assert(is_simm32(disp), "must be 32bit offset (jmp)");
+ emit_data(disp, rspec.reloc(), call32_operand);
+}
+
+void Assembler::jmpb(Label& L) {
+ if (L.is_bound()) {
+ const int short_size = 2;
+ address entry = target(L);
+ assert(is8bit((entry - _code_pos) + short_size),
+ "Dispacement too large for a short jmp");
+ assert(entry != NULL, "jmp most probably wrong");
+ intptr_t offs = entry - _code_pos;
+ emit_byte(0xEB);
+ emit_byte((offs - short_size) & 0xFF);
+ } else {
+ InstructionMark im(this);
+ L.add_patch_at(code(), locator());
+ emit_byte(0xEB);
+ emit_byte(0);
+ }
+}
+
+void Assembler::ldmxcsr( Address src) {
+ NOT_LP64(assert(VM_Version::supports_sse(), ""));
+ InstructionMark im(this);
+ prefix(src);
+ emit_byte(0x0F);
+ emit_byte(0xAE);
+ emit_operand(as_Register(2), src);
+}
+
+void Assembler::leal(Register dst, Address src) {
+ InstructionMark im(this);
+#ifdef _LP64
+ emit_byte(0x67); // addr32
+ prefix(src, dst);
+#endif // LP64
+ emit_byte(0x8D);
+ emit_operand(dst, src);
+}
+
+void Assembler::lock() {
+ if (Atomics & 1) {
+ // Emit either nothing, a NOP, or a NOP: prefix
+ emit_byte(0x90) ;
+ } else {
+ emit_byte(0xF0);
+ }
+}
+
+// Serializes memory.
+void Assembler::mfence() {
+ // Memory barriers are only needed on multiprocessors
+ if (os::is_MP()) {
+ if( LP64_ONLY(true ||) VM_Version::supports_sse2() ) {
+ emit_byte( 0x0F ); // MFENCE; faster blows no regs
+ emit_byte( 0xAE );
+ emit_byte( 0xF0 );
+ } else {
+ // All usable chips support "locked" instructions which suffice
+ // as barriers, and are much faster than the alternative of
+ // using cpuid instruction. We use here a locked add [esp],0.
+ // This is conveniently otherwise a no-op except for blowing
+ // flags (which we save and restore.)
+ pushf(); // Save eflags register
+ lock();
+ addl(Address(rsp, 0), 0);// Assert the lock# signal here
+ popf(); // Restore eflags register
+ }
+ }
+}
+
+void Assembler::mov(Register dst, Register src) {
+ LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
+}
+
+void Assembler::movapd(XMMRegister dst, XMMRegister src) {
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ int dstenc = dst->encoding();
+ int srcenc = src->encoding();
+ emit_byte(0x66);
+ if (dstenc < 8) {
+ if (srcenc >= 8) {
+ prefix(REX_B);
+ srcenc -= 8;
+ }
+ } else {
+ if (srcenc < 8) {
+ prefix(REX_R);
+ } else {
+ prefix(REX_RB);
+ srcenc -= 8;
+ }
+ dstenc -= 8;
+ }
+ emit_byte(0x0F);
+ emit_byte(0x28);
+ emit_byte(0xC0 | dstenc << 3 | srcenc);
+}
+
+void Assembler::movaps(XMMRegister dst, XMMRegister src) {
+ NOT_LP64(assert(VM_Version::supports_sse(), ""));
+ int dstenc = dst->encoding();
+ int srcenc = src->encoding();
+ if (dstenc < 8) {
+ if (srcenc >= 8) {
+ prefix(REX_B);
+ srcenc -= 8;
+ }
+ } else {
+ if (srcenc < 8) {
+ prefix(REX_R);
+ } else {
+ prefix(REX_RB);
+ srcenc -= 8;
+ }
+ dstenc -= 8;
+ }
+ emit_byte(0x0F);
+ emit_byte(0x28);
+ emit_byte(0xC0 | dstenc << 3 | srcenc);
+}
+
+void Assembler::movb(Register dst, Address src) {
+ NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
+ InstructionMark im(this);
+ prefix(src, dst, true);
+ emit_byte(0x8A);
+ emit_operand(dst, src);
+}
+
+
+void Assembler::movb(Address dst, int imm8) {
+ InstructionMark im(this);
+ prefix(dst);
+ emit_byte(0xC6);
+ emit_operand(rax, dst, 1);
+ emit_byte(imm8);
+}
+
+
+void Assembler::movb(Address dst, Register src) {
+ assert(src->has_byte_register(), "must have byte register");
+ InstructionMark im(this);
+ prefix(dst, src, true);
+ emit_byte(0x88);
+ emit_operand(src, dst);
+}
+
+void Assembler::movdl(XMMRegister dst, Register src) {
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ emit_byte(0x66);
+ int encode = prefix_and_encode(dst->encoding(), src->encoding());
+ emit_byte(0x0F);
+ emit_byte(0x6E);
+ emit_byte(0xC0 | encode);
+}
+
+void Assembler::movdl(Register dst, XMMRegister src) {
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ emit_byte(0x66);
+ // swap src/dst to get correct prefix
+ int encode = prefix_and_encode(src->encoding(), dst->encoding());
+ emit_byte(0x0F);
+ emit_byte(0x7E);
+ emit_byte(0xC0 | encode);
+}
+
+void Assembler::movdqa(XMMRegister dst, Address src) {
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ InstructionMark im(this);
+ emit_byte(0x66);
+ prefix(src, dst);
+ emit_byte(0x0F);
+ emit_byte(0x6F);
+ emit_operand(dst, src);
+}
+
+void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ emit_byte(0x66);
+ int encode = prefixq_and_encode(dst->encoding(), src->encoding());
+ emit_byte(0x0F);
+ emit_byte(0x6F);
+ emit_byte(0xC0 | encode);
+}
+
+void Assembler::movdqa(Address dst, XMMRegister src) {
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ InstructionMark im(this);
+ emit_byte(0x66);
+ prefix(dst, src);
+ emit_byte(0x0F);
+ emit_byte(0x7F);
+ emit_operand(src, dst);
+}
+
+// Uses zero extension on 64bit
+
+void Assembler::movl(Register dst, int32_t imm32) {
+ int encode = prefix_and_encode(dst->encoding());
+ emit_byte(0xB8 | encode);
+ emit_long(imm32);
+}
+
+void Assembler::movl(Register dst, Register src) {
+ int encode = prefix_and_encode(dst->encoding(), src->encoding());
+ emit_byte(0x8B);
+ emit_byte(0xC0 | encode);
+}
+
+void Assembler::movl(Register dst, Address src) {
+ InstructionMark im(this);
+ prefix(src, dst);
+ emit_byte(0x8B);
+ emit_operand(dst, src);
+}
+
+void Assembler::movl(Address dst, int32_t imm32) {
+ InstructionMark im(this);
+ prefix(dst);
+ emit_byte(0xC7);
+ emit_operand(rax, dst, 4);
+ emit_long(imm32);
+}
+
+void Assembler::movl(Address dst, Register src) {
+ InstructionMark im(this);
+ prefix(dst, src);
+ emit_byte(0x89);
+ emit_operand(src, dst);
+}
+
+// New cpus require to use movsd and movss to avoid partial register stall
+// when loading from memory. But for old Opteron use movlpd instead of movsd.
+// The selection is done in MacroAssembler::movdbl() and movflt().
+void Assembler::movlpd(XMMRegister dst, Address src) {
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ InstructionMark im(this);
+ emit_byte(0x66);
+ prefix(src, dst);
+ emit_byte(0x0F);
+ emit_byte(0x12);
+ emit_operand(dst, src);
+}
+
+void Assembler::movq( MMXRegister dst, Address src ) {
+ assert( VM_Version::supports_mmx(), "" );
+ emit_byte(0x0F);
+ emit_byte(0x6F);
+ emit_operand(dst, src);
+}
+
+void Assembler::movq( Address dst, MMXRegister src ) {
+ assert( VM_Version::supports_mmx(), "" );
+ emit_byte(0x0F);
+ emit_byte(0x7F);
+ // workaround gcc (3.2.1-7a) bug
+ // In that version of gcc with only an emit_operand(MMX, Address)
+ // gcc will tail jump and try and reverse the parameters completely
+ // obliterating dst in the process. By having a version available
+ // that doesn't need to swap the args at the tail jump the bug is
+ // avoided.
+ emit_operand(dst, src);
+}
+
+void Assembler::movq(XMMRegister dst, Address src) {
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ InstructionMark im(this);
+ emit_byte(0xF3);
+ prefix(src, dst);
+ emit_byte(0x0F);
+ emit_byte(0x7E);
+ emit_operand(dst, src);
+}
+
+void Assembler::movq(Address dst, XMMRegister src) {
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ InstructionMark im(this);
+ emit_byte(0x66);
+ prefix(dst, src);
+ emit_byte(0x0F);
+ emit_byte(0xD6);
+ emit_operand(src, dst);
+}
+
+void Assembler::movsbl(Register dst, Address src) { // movsxb
+ InstructionMark im(this);
+ prefix(src, dst);
+ emit_byte(0x0F);
+ emit_byte(0xBE);
+ emit_operand(dst, src);
+}
+
+void Assembler::movsbl(Register dst, Register src) { // movsxb
+ NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
+ int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
+ emit_byte(0x0F);
+ emit_byte(0xBE);
+ emit_byte(0xC0 | encode);
+}
+
+void Assembler::movsd(XMMRegister dst, XMMRegister src) {
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ emit_byte(0xF2);
+ int encode = prefix_and_encode(dst->encoding(), src->encoding());
+ emit_byte(0x0F);
+ emit_byte(0x10);
+ emit_byte(0xC0 | encode);
+}
+
+void Assembler::movsd(XMMRegister dst, Address src) {
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ InstructionMark im(this);
+ emit_byte(0xF2);
+ prefix(src, dst);
+ emit_byte(0x0F);
+ emit_byte(0x10);
+ emit_operand(dst, src);
+}
+
+void Assembler::movsd(Address dst, XMMRegister src) {
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ InstructionMark im(this);
+ emit_byte(0xF2);
+ prefix(dst, src);
+ emit_byte(0x0F);
+ emit_byte(0x11);
+ emit_operand(src, dst);
+}
+
+void Assembler::movss(XMMRegister dst, XMMRegister src) {
+ NOT_LP64(assert(VM_Version::supports_sse(), ""));
+ emit_byte(0xF3);
+ int encode = prefix_and_encode(dst->encoding(), src->encoding());
+ emit_byte(0x0F);
+ emit_byte(0x10);
+ emit_byte(0xC0 | encode);
+}
+
+void Assembler::movss(XMMRegister dst, Address src) {
+ NOT_LP64(assert(VM_Version::supports_sse(), ""));
+ InstructionMark im(this);
+ emit_byte(0xF3);
+ prefix(src, dst);
+ emit_byte(0x0F);
+ emit_byte(0x10);
+ emit_operand(dst, src);
+}
+
+void Assembler::movss(Address dst, XMMRegister src) {
+ NOT_LP64(assert(VM_Version::supports_sse(), ""));
+ InstructionMark im(this);
+ emit_byte(0xF3);
+ prefix(dst, src);
+ emit_byte(0x0F);
+ emit_byte(0x11);
+ emit_operand(src, dst);
+}
+
+void Assembler::movswl(Register dst, Address src) { // movsxw
+ InstructionMark im(this);
+ prefix(src, dst);
+ emit_byte(0x0F);
+ emit_byte(0xBF);
+ emit_operand(dst, src);
+}
+
+void Assembler::movswl(Register dst, Register src) { // movsxw
+ int encode = prefix_and_encode(dst->encoding(), src->encoding());
+ emit_byte(0x0F);
+ emit_byte(0xBF);
+ emit_byte(0xC0 | encode);
+}
+
+void Assembler::movw(Address dst, int imm16) {
+ InstructionMark im(this);
+
+ emit_byte(0x66); // switch to 16-bit mode
+ prefix(dst);
+ emit_byte(0xC7);
+ emit_operand(rax, dst, 2);
+ emit_word(imm16);
+}
+
+void Assembler::movw(Register dst, Address src) {
+ InstructionMark im(this);
+ emit_byte(0x66);
+ prefix(src, dst);
+ emit_byte(0x8B);
+ emit_operand(dst, src);
+}
+
+void Assembler::movw(Address dst, Register src) {
+ InstructionMark im(this);
+ emit_byte(0x66);
+ prefix(dst, src);
+ emit_byte(0x89);
+ emit_operand(src, dst);
+}
+
+void Assembler::movzbl(Register dst, Address src) { // movzxb
+ InstructionMark im(this);
+ prefix(src, dst);
+ emit_byte(0x0F);
+ emit_byte(0xB6);
+ emit_operand(dst, src);
+}
+
+void Assembler::movzbl(Register dst, Register src) { // movzxb
+ NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
+ int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
+ emit_byte(0x0F);
+ emit_byte(0xB6);
+ emit_byte(0xC0 | encode);
+}
+
+void Assembler::movzwl(Register dst, Address src) { // movzxw
+ InstructionMark im(this);
+ prefix(src, dst);
+ emit_byte(0x0F);
+ emit_byte(0xB7);
+ emit_operand(dst, src);
+}
+
+void Assembler::movzwl(Register dst, Register src) { // movzxw
+ int encode = prefix_and_encode(dst->encoding(), src->encoding());
+ emit_byte(0x0F);
+ emit_byte(0xB7);
+ emit_byte(0xC0 | encode);
+}
+
+void Assembler::mull(Address src) {
+ InstructionMark im(this);
+ prefix(src);
+ emit_byte(0xF7);
+ emit_operand(rsp, src);
+}
+
+void Assembler::mull(Register src) {
+ int encode = prefix_and_encode(src->encoding());
+ emit_byte(0xF7);
+ emit_byte(0xE0 | encode);
+}
+
+void Assembler::mulsd(XMMRegister dst, Address src) {
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ InstructionMark im(this);
+ emit_byte(0xF2);
+ prefix(src, dst);
+ emit_byte(0x0F);
+ emit_byte(0x59);
+ emit_operand(dst, src);
+}
+
+void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ emit_byte(0xF2);
+ int encode = prefix_and_encode(dst->encoding(), src->encoding());
+ emit_byte(0x0F);
+ emit_byte(0x59);
+ emit_byte(0xC0 | encode);
+}
+
+void Assembler::mulss(XMMRegister dst, Address src) {
+ NOT_LP64(assert(VM_Version::supports_sse(), ""));
+ InstructionMark im(this);
+ emit_byte(0xF3);
+ prefix(src, dst);
+ emit_byte(0x0F);
+ emit_byte(0x59);
+ emit_operand(dst, src);
+}
+
+void Assembler::mulss(XMMRegister dst, XMMRegister src) {
+ NOT_LP64(assert(VM_Version::supports_sse(), ""));
+ emit_byte(0xF3);
+ int encode = prefix_and_encode(dst->encoding(), src->encoding());
+ emit_byte(0x0F);
+ emit_byte(0x59);
+ emit_byte(0xC0 | encode);
+}
+
+void Assembler::negl(Register dst) {
+ int encode = prefix_and_encode(dst->encoding());
+ emit_byte(0xF7);
+ emit_byte(0xD8 | encode);
+}
+
void Assembler::nop(int i) {
+#ifdef ASSERT
assert(i > 0, " ");
+ // The fancy nops aren't currently recognized by debuggers making it a
+ // pain to disassemble code while debugging. If asserts are on clearly
+ // speed is not an issue so simply use the single byte traditional nop
+ // to do alignment.
+
+ for (; i > 0 ; i--) emit_byte(0x90);
+ return;
+
+#endif // ASSERT
+
if (UseAddressNop && VM_Version::is_intel()) {
//
// Using multi-bytes nops "0x0F 0x1F [address]" for Intel
@@ -2853,6 +2115,281 @@ void Assembler::nop(int i) {
}
}
+void Assembler::notl(Register dst) {
+ int encode = prefix_and_encode(dst->encoding());
+ emit_byte(0xF7);
+ emit_byte(0xD0 | encode );
+}
+
+void Assembler::orl(Address dst, int32_t imm32) {
+ InstructionMark im(this);
+ prefix(dst);
+ emit_byte(0x81);
+ emit_operand(rcx, dst, 4);
+ emit_long(imm32);
+}
+
+void Assembler::orl(Register dst, int32_t imm32) {
+ prefix(dst);
+ emit_arith(0x81, 0xC8, dst, imm32);
+}
+
+
+void Assembler::orl(Register dst, Address src) {
+ InstructionMark im(this);
+ prefix(src, dst);
+ emit_byte(0x0B);
+ emit_operand(dst, src);
+}
+
+
+void Assembler::orl(Register dst, Register src) {
+ (void) prefix_and_encode(dst->encoding(), src->encoding());
+ emit_arith(0x0B, 0xC0, dst, src);
+}
+
+// generic
+void Assembler::pop(Register dst) {
+ int encode = prefix_and_encode(dst->encoding());
+ emit_byte(0x58 | encode);
+}
+
+void Assembler::popf() {
+ emit_byte(0x9D);
+}
+
+void Assembler::popl(Address dst) {
+ // NOTE: this will adjust stack by 8byte on 64bits
+ InstructionMark im(this);
+ prefix(dst);
+ emit_byte(0x8F);
+ emit_operand(rax, dst);
+}
+
+void Assembler::prefetch_prefix(Address src) {
+ prefix(src);
+ emit_byte(0x0F);
+}
+
+void Assembler::prefetchnta(Address src) {
+ NOT_LP64(assert(VM_Version::supports_sse2(), "must support"));
+ InstructionMark im(this);
+ prefetch_prefix(src);
+ emit_byte(0x18);
+ emit_operand(rax, src); // 0, src
+}
+
+void Assembler::prefetchr(Address src) {
+ NOT_LP64(assert(VM_Version::supports_3dnow(), "must support"));
+ InstructionMark im(this);
+ prefetch_prefix(src);
+ emit_byte(0x0D);
+ emit_operand(rax, src); // 0, src
+}
+
+void Assembler::prefetcht0(Address src) {
+ NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
+ InstructionMark im(this);
+ prefetch_prefix(src);
+ emit_byte(0x18);
+ emit_operand(rcx, src); // 1, src
+}
+
+void Assembler::prefetcht1(Address src) {
+ NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
+ InstructionMark im(this);
+ prefetch_prefix(src);
+ emit_byte(0x18);
+ emit_operand(rdx, src); // 2, src
+}
+
+void Assembler::prefetcht2(Address src) {
+ NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
+ InstructionMark im(this);
+ prefetch_prefix(src);
+ emit_byte(0x18);
+ emit_operand(rbx, src); // 3, src
+}
+
+void Assembler::prefetchw(Address src) {
+ NOT_LP64(assert(VM_Version::supports_3dnow(), "must support"));
+ InstructionMark im(this);
+ prefetch_prefix(src);
+ emit_byte(0x0D);
+ emit_operand(rcx, src); // 1, src
+}
+
+void Assembler::prefix(Prefix p) {
+ a_byte(p);
+}
+
+void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
+ assert(isByte(mode), "invalid value");
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+
+ emit_byte(0x66);
+ int encode = prefix_and_encode(dst->encoding(), src->encoding());
+ emit_byte(0x0F);
+ emit_byte(0x70);
+ emit_byte(0xC0 | encode);
+ emit_byte(mode & 0xFF);
+
+}
+
+void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
+ assert(isByte(mode), "invalid value");
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+
+ InstructionMark im(this);
+ emit_byte(0x66);
+ prefix(src, dst);
+ emit_byte(0x0F);
+ emit_byte(0x70);
+ emit_operand(dst, src);
+ emit_byte(mode & 0xFF);
+}
+
+void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
+ assert(isByte(mode), "invalid value");
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+
+ emit_byte(0xF2);
+ int encode = prefix_and_encode(dst->encoding(), src->encoding());
+ emit_byte(0x0F);
+ emit_byte(0x70);
+ emit_byte(0xC0 | encode);
+ emit_byte(mode & 0xFF);
+}
+
+void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
+ assert(isByte(mode), "invalid value");
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+
+ InstructionMark im(this);
+ emit_byte(0xF2);
+ prefix(src, dst); // QQ new
+ emit_byte(0x0F);
+ emit_byte(0x70);
+ emit_operand(dst, src);
+ emit_byte(mode & 0xFF);
+}
+
+void Assembler::psrlq(XMMRegister dst, int shift) {
+ // HMM Table D-1 says sse2 or mmx
+ NOT_LP64(assert(VM_Version::supports_sse(), ""));
+
+ int encode = prefixq_and_encode(xmm2->encoding(), dst->encoding());
+ emit_byte(0x66);
+ emit_byte(0x0F);
+ emit_byte(0x73);
+ emit_byte(0xC0 | encode);
+ emit_byte(shift);
+}
+
+void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ emit_byte(0x66);
+ int encode = prefix_and_encode(dst->encoding(), src->encoding());
+ emit_byte(0x0F);
+ emit_byte(0x60);
+ emit_byte(0xC0 | encode);
+}
+
+void Assembler::push(int32_t imm32) {
+ // in 64bits we push 64bits onto the stack but only
+ // take a 32bit immediate
+ emit_byte(0x68);
+ emit_long(imm32);
+}
+
+void Assembler::push(Register src) {
+ int encode = prefix_and_encode(src->encoding());
+
+ emit_byte(0x50 | encode);
+}
+
+void Assembler::pushf() {
+ emit_byte(0x9C);
+}
+
+void Assembler::pushl(Address src) {
+ // Note this will push 64bit on 64bit
+ InstructionMark im(this);
+ prefix(src);
+ emit_byte(0xFF);
+ emit_operand(rsi, src);
+}
+
+void Assembler::pxor(XMMRegister dst, Address src) {
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ InstructionMark im(this);
+ emit_byte(0x66);
+ prefix(src, dst);
+ emit_byte(0x0F);
+ emit_byte(0xEF);
+ emit_operand(dst, src);
+}
+
+void Assembler::pxor(XMMRegister dst, XMMRegister src) {
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ InstructionMark im(this);
+ emit_byte(0x66);
+ int encode = prefix_and_encode(dst->encoding(), src->encoding());
+ emit_byte(0x0F);
+ emit_byte(0xEF);
+ emit_byte(0xC0 | encode);
+}
+
+void Assembler::rcll(Register dst, int imm8) {
+ assert(isShiftCount(imm8), "illegal shift count");
+ int encode = prefix_and_encode(dst->encoding());
+ if (imm8 == 1) {
+ emit_byte(0xD1);
+ emit_byte(0xD0 | encode);
+ } else {
+ emit_byte(0xC1);
+ emit_byte(0xD0 | encode);
+ emit_byte(imm8);
+ }
+}
+
+// copies data from [esi] to [edi] using rcx pointer sized words
+// generic
+void Assembler::rep_mov() {
+ emit_byte(0xF3);
+ // MOVSQ
+ LP64_ONLY(prefix(REX_W));
+ emit_byte(0xA5);
+}
+
+// sets rcx pointer sized words with rax, value at [edi]
+// generic
+void Assembler::rep_set() { // rep_set
+ emit_byte(0xF3);
+ // STOSQ
+ LP64_ONLY(prefix(REX_W));
+ emit_byte(0xAB);
+}
+
+// scans rcx pointer sized words at [edi] for occurance of rax,
+// generic
+void Assembler::repne_scan() { // repne_scan
+ emit_byte(0xF2);
+ // SCASQ
+ LP64_ONLY(prefix(REX_W));
+ emit_byte(0xAF);
+}
+
+#ifdef _LP64
+// scans rcx 4 byte words at [edi] for occurance of rax,
+// generic
+void Assembler::repne_scanl() { // repne_scan
+ emit_byte(0xF2);
+ // SCASL
+ emit_byte(0xAF);
+}
+#endif
+
void Assembler::ret(int imm16) {
if (imm16 == 0) {
emit_byte(0xC3);
@@ -2862,53 +2399,56 @@ void Assembler::ret(int imm16) {
}
}
-// copies a single word from [esi] to [edi]
-void Assembler::smovl() {
- emit_byte(0xA5);
+void Assembler::sahf() {
+#ifdef _LP64
+ // Not supported in 64bit mode
+ ShouldNotReachHere();
+#endif
+ emit_byte(0x9E);
}
-// copies data from [rsi] to [rdi] using rcx words (m32)
-void Assembler::rep_movl() {
- // REP
- emit_byte(0xF3);
- // MOVSL
- emit_byte(0xA5);
+void Assembler::sarl(Register dst, int imm8) {
+ int encode = prefix_and_encode(dst->encoding());
+ assert(isShiftCount(imm8), "illegal shift count");
+ if (imm8 == 1) {
+ emit_byte(0xD1);
+ emit_byte(0xF8 | encode);
+ } else {
+ emit_byte(0xC1);
+ emit_byte(0xF8 | encode);
+ emit_byte(imm8);
+ }
}
-// copies data from [rsi] to [rdi] using rcx double words (m64)
-void Assembler::rep_movq() {
- // REP
- emit_byte(0xF3);
- // MOVSQ
- prefix(REX_W);
- emit_byte(0xA5);
+void Assembler::sarl(Register dst) {
+ int encode = prefix_and_encode(dst->encoding());
+ emit_byte(0xD3);
+ emit_byte(0xF8 | encode);
}
-// sets rcx double words (m64) with rax value at [rdi]
-void Assembler::rep_set() {
- // REP
- emit_byte(0xF3);
- // STOSQ
- prefix(REX_W);
- emit_byte(0xAB);
+void Assembler::sbbl(Address dst, int32_t imm32) {
+ InstructionMark im(this);
+ prefix(dst);
+ emit_arith_operand(0x81, rbx, dst, imm32);
}
-// scans rcx double words (m64) at [rdi] for occurance of rax
-void Assembler::repne_scanq() {
- // REPNE/REPNZ
- emit_byte(0xF2);
- // SCASQ
- prefix(REX_W);
- emit_byte(0xAF);
+void Assembler::sbbl(Register dst, int32_t imm32) {
+ prefix(dst);
+ emit_arith(0x81, 0xD8, dst, imm32);
}
-void Assembler::repne_scanl() {
- // REPNE/REPNZ
- emit_byte(0xF2);
- // SCASL
- emit_byte(0xAF);
+
+void Assembler::sbbl(Register dst, Address src) {
+ InstructionMark im(this);
+ prefix(src, dst);
+ emit_byte(0x1B);
+ emit_operand(dst, src);
}
+void Assembler::sbbl(Register dst, Register src) {
+ (void) prefix_and_encode(dst->encoding(), src->encoding());
+ emit_arith(0x1B, 0xC0, dst, src);
+}
void Assembler::setb(Condition cc, Register dst) {
assert(0 <= cc && cc < 16, "illegal cc");
@@ -2918,6 +2458,1155 @@ void Assembler::setb(Condition cc, Register dst) {
emit_byte(0xC0 | encode);
}
+void Assembler::shll(Register dst, int imm8) {
+ assert(isShiftCount(imm8), "illegal shift count");
+ int encode = prefix_and_encode(dst->encoding());
+ if (imm8 == 1 ) {
+ emit_byte(0xD1);
+ emit_byte(0xE0 | encode);
+ } else {
+ emit_byte(0xC1);
+ emit_byte(0xE0 | encode);
+ emit_byte(imm8);
+ }
+}
+
+void Assembler::shll(Register dst) {
+ int encode = prefix_and_encode(dst->encoding());
+ emit_byte(0xD3);
+ emit_byte(0xE0 | encode);
+}
+
+void Assembler::shrl(Register dst, int imm8) {
+ assert(isShiftCount(imm8), "illegal shift count");
+ int encode = prefix_and_encode(dst->encoding());
+ emit_byte(0xC1);
+ emit_byte(0xE8 | encode);
+ emit_byte(imm8);
+}
+
+void Assembler::shrl(Register dst) {
+ int encode = prefix_and_encode(dst->encoding());
+ emit_byte(0xD3);
+ emit_byte(0xE8 | encode);
+}
+
+// copies a single word from [esi] to [edi]
+void Assembler::smovl() {
+ emit_byte(0xA5);
+}
+
+void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
+ // HMM Table D-1 says sse2
+ // NOT_LP64(assert(VM_Version::supports_sse(), ""));
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ emit_byte(0xF2);
+ int encode = prefix_and_encode(dst->encoding(), src->encoding());
+ emit_byte(0x0F);
+ emit_byte(0x51);
+ emit_byte(0xC0 | encode);
+}
+
+void Assembler::stmxcsr( Address dst) {
+ NOT_LP64(assert(VM_Version::supports_sse(), ""));
+ InstructionMark im(this);
+ prefix(dst);
+ emit_byte(0x0F);
+ emit_byte(0xAE);
+ emit_operand(as_Register(3), dst);
+}
+
+void Assembler::subl(Address dst, int32_t imm32) {
+ InstructionMark im(this);
+ prefix(dst);
+ if (is8bit(imm32)) {
+ emit_byte(0x83);
+ emit_operand(rbp, dst, 1);
+ emit_byte(imm32 & 0xFF);
+ } else {
+ emit_byte(0x81);
+ emit_operand(rbp, dst, 4);
+ emit_long(imm32);
+ }
+}
+
+void Assembler::subl(Register dst, int32_t imm32) {
+ prefix(dst);
+ emit_arith(0x81, 0xE8, dst, imm32);
+}
+
+void Assembler::subl(Address dst, Register src) {
+ InstructionMark im(this);
+ prefix(dst, src);
+ emit_byte(0x29);
+ emit_operand(src, dst);
+}
+
+void Assembler::subl(Register dst, Address src) {
+ InstructionMark im(this);
+ prefix(src, dst);
+ emit_byte(0x2B);
+ emit_operand(dst, src);
+}
+
+void Assembler::subl(Register dst, Register src) {
+ (void) prefix_and_encode(dst->encoding(), src->encoding());
+ emit_arith(0x2B, 0xC0, dst, src);
+}
+
+void Assembler::subsd(XMMRegister dst, XMMRegister src) {
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ emit_byte(0xF2);
+ int encode = prefix_and_encode(dst->encoding(), src->encoding());
+ emit_byte(0x0F);
+ emit_byte(0x5C);
+ emit_byte(0xC0 | encode);
+}
+
+void Assembler::subsd(XMMRegister dst, Address src) {
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ InstructionMark im(this);
+ emit_byte(0xF2);
+ prefix(src, dst);
+ emit_byte(0x0F);
+ emit_byte(0x5C);
+ emit_operand(dst, src);
+}
+
+void Assembler::subss(XMMRegister dst, XMMRegister src) {
+ NOT_LP64(assert(VM_Version::supports_sse(), ""));
+ emit_byte(0xF3);
+ int encode = prefix_and_encode(dst->encoding(), src->encoding());
+ emit_byte(0x0F);
+ emit_byte(0x5C);
+ emit_byte(0xC0 | encode);
+}
+
+void Assembler::subss(XMMRegister dst, Address src) {
+ NOT_LP64(assert(VM_Version::supports_sse(), ""));
+ InstructionMark im(this);
+ emit_byte(0xF3);
+ prefix(src, dst);
+ emit_byte(0x0F);
+ emit_byte(0x5C);
+ emit_operand(dst, src);
+}
+
+void Assembler::testb(Register dst, int imm8) {
+ NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
+ (void) prefix_and_encode(dst->encoding(), true);
+ emit_arith_b(0xF6, 0xC0, dst, imm8);
+}
+
+void Assembler::testl(Register dst, int32_t imm32) {
+ // not using emit_arith because test
+ // doesn't support sign-extension of
+ // 8bit operands
+ int encode = dst->encoding();
+ if (encode == 0) {
+ emit_byte(0xA9);
+ } else {
+ encode = prefix_and_encode(encode);
+ emit_byte(0xF7);
+ emit_byte(0xC0 | encode);
+ }
+ emit_long(imm32);
+}
+
+void Assembler::testl(Register dst, Register src) {
+ (void) prefix_and_encode(dst->encoding(), src->encoding());
+ emit_arith(0x85, 0xC0, dst, src);
+}
+
+void Assembler::testl(Register dst, Address src) {
+ InstructionMark im(this);
+ prefix(src, dst);
+ emit_byte(0x85);
+ emit_operand(dst, src);
+}
+
+void Assembler::ucomisd(XMMRegister dst, Address src) {
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ emit_byte(0x66);
+ ucomiss(dst, src);
+}
+
+void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ emit_byte(0x66);
+ ucomiss(dst, src);
+}
+
+void Assembler::ucomiss(XMMRegister dst, Address src) {
+ NOT_LP64(assert(VM_Version::supports_sse(), ""));
+
+ InstructionMark im(this);
+ prefix(src, dst);
+ emit_byte(0x0F);
+ emit_byte(0x2E);
+ emit_operand(dst, src);
+}
+
+void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
+ NOT_LP64(assert(VM_Version::supports_sse(), ""));
+ int encode = prefix_and_encode(dst->encoding(), src->encoding());
+ emit_byte(0x0F);
+ emit_byte(0x2E);
+ emit_byte(0xC0 | encode);
+}
+
+
+void Assembler::xaddl(Address dst, Register src) {
+ InstructionMark im(this);
+ prefix(dst, src);
+ emit_byte(0x0F);
+ emit_byte(0xC1);
+ emit_operand(src, dst);
+}
+
+void Assembler::xchgl(Register dst, Address src) { // xchg
+ InstructionMark im(this);
+ prefix(src, dst);
+ emit_byte(0x87);
+ emit_operand(dst, src);
+}
+
+void Assembler::xchgl(Register dst, Register src) {
+ int encode = prefix_and_encode(dst->encoding(), src->encoding());
+ emit_byte(0x87);
+ emit_byte(0xc0 | encode);
+}
+
+void Assembler::xorl(Register dst, int32_t imm32) {
+ prefix(dst);
+ emit_arith(0x81, 0xF0, dst, imm32);
+}
+
+void Assembler::xorl(Register dst, Address src) {
+ InstructionMark im(this);
+ prefix(src, dst);
+ emit_byte(0x33);
+ emit_operand(dst, src);
+}
+
+void Assembler::xorl(Register dst, Register src) {
+ (void) prefix_and_encode(dst->encoding(), src->encoding());
+ emit_arith(0x33, 0xC0, dst, src);
+}
+
+void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ emit_byte(0x66);
+ xorps(dst, src);
+}
+
+void Assembler::xorpd(XMMRegister dst, Address src) {
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ InstructionMark im(this);
+ emit_byte(0x66);
+ prefix(src, dst);
+ emit_byte(0x0F);
+ emit_byte(0x57);
+ emit_operand(dst, src);
+}
+
+
+void Assembler::xorps(XMMRegister dst, XMMRegister src) {
+ NOT_LP64(assert(VM_Version::supports_sse(), ""));
+ int encode = prefix_and_encode(dst->encoding(), src->encoding());
+ emit_byte(0x0F);
+ emit_byte(0x57);
+ emit_byte(0xC0 | encode);
+}
+
+void Assembler::xorps(XMMRegister dst, Address src) {
+ NOT_LP64(assert(VM_Version::supports_sse(), ""));
+ InstructionMark im(this);
+ prefix(src, dst);
+ emit_byte(0x0F);
+ emit_byte(0x57);
+ emit_operand(dst, src);
+}
+
+#ifndef _LP64
+// 32bit only pieces of the assembler
+
+void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
+ // NO PREFIX AS NEVER 64BIT
+ InstructionMark im(this);
+ emit_byte(0x81);
+ emit_byte(0xF8 | src1->encoding());
+ emit_data(imm32, rspec, 0);
+}
+
+void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
+ // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
+ InstructionMark im(this);
+ emit_byte(0x81);
+ emit_operand(rdi, src1);
+ emit_data(imm32, rspec, 0);
+}
+
+// The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
+// and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
+// into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
+void Assembler::cmpxchg8(Address adr) {
+ InstructionMark im(this);
+ emit_byte(0x0F);
+ emit_byte(0xc7);
+ emit_operand(rcx, adr);
+}
+
+void Assembler::decl(Register dst) {
+ // Don't use it directly. Use MacroAssembler::decrementl() instead.
+ emit_byte(0x48 | dst->encoding());
+}
+
+#endif // _LP64
+
+// 64bit typically doesn't use the x87 but needs to for the trig funcs
+
+void Assembler::fabs() {
+ emit_byte(0xD9);
+ emit_byte(0xE1);
+}
+
+void Assembler::fadd(int i) {
+ emit_farith(0xD8, 0xC0, i);
+}
+
+void Assembler::fadd_d(Address src) {
+ InstructionMark im(this);
+ emit_byte(0xDC);
+ emit_operand32(rax, src);
+}
+
+void Assembler::fadd_s(Address src) {
+ InstructionMark im(this);
+ emit_byte(0xD8);
+ emit_operand32(rax, src);
+}
+
+void Assembler::fadda(int i) {
+ emit_farith(0xDC, 0xC0, i);
+}
+
+void Assembler::faddp(int i) {
+ emit_farith(0xDE, 0xC0, i);
+}
+
+void Assembler::fchs() {
+ emit_byte(0xD9);
+ emit_byte(0xE0);
+}
+
+void Assembler::fcom(int i) {
+ emit_farith(0xD8, 0xD0, i);
+}
+
+void Assembler::fcomp(int i) {
+ emit_farith(0xD8, 0xD8, i);
+}
+
+void Assembler::fcomp_d(Address src) {
+ InstructionMark im(this);
+ emit_byte(0xDC);
+ emit_operand32(rbx, src);
+}
+
+void Assembler::fcomp_s(Address src) {
+ InstructionMark im(this);
+ emit_byte(0xD8);
+ emit_operand32(rbx, src);
+}
+
+void Assembler::fcompp() {
+ emit_byte(0xDE);
+ emit_byte(0xD9);
+}
+
+void Assembler::fcos() {
+ emit_byte(0xD9);
+ emit_byte(0xFF);
+}
+
+void Assembler::fdecstp() {
+ emit_byte(0xD9);
+ emit_byte(0xF6);
+}
+
+void Assembler::fdiv(int i) {
+ emit_farith(0xD8, 0xF0, i);
+}
+
+void Assembler::fdiv_d(Address src) {
+ InstructionMark im(this);
+ emit_byte(0xDC);
+ emit_operand32(rsi, src);
+}
+
+void Assembler::fdiv_s(Address src) {
+ InstructionMark im(this);
+ emit_byte(0xD8);
+ emit_operand32(rsi, src);
+}
+
+void Assembler::fdiva(int i) {
+ emit_farith(0xDC, 0xF8, i);
+}
+
+// Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
+// is erroneous for some of the floating-point instructions below.
+
+void Assembler::fdivp(int i) {
+ emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
+}
+
+void Assembler::fdivr(int i) {
+ emit_farith(0xD8, 0xF8, i);
+}
+
+void Assembler::fdivr_d(Address src) {
+ InstructionMark im(this);
+ emit_byte(0xDC);
+ emit_operand32(rdi, src);
+}
+
+void Assembler::fdivr_s(Address src) {
+ InstructionMark im(this);
+ emit_byte(0xD8);
+ emit_operand32(rdi, src);
+}
+
+void Assembler::fdivra(int i) {
+ emit_farith(0xDC, 0xF0, i);
+}
+
+void Assembler::fdivrp(int i) {
+ emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
+}
+
+void Assembler::ffree(int i) {
+ emit_farith(0xDD, 0xC0, i);
+}
+
+void Assembler::fild_d(Address adr) {
+ InstructionMark im(this);
+ emit_byte(0xDF);
+ emit_operand32(rbp, adr);
+}
+
+void Assembler::fild_s(Address adr) {
+ InstructionMark im(this);
+ emit_byte(0xDB);
+ emit_operand32(rax, adr);
+}
+
+void Assembler::fincstp() {
+ emit_byte(0xD9);
+ emit_byte(0xF7);
+}
+
+void Assembler::finit() {
+ emit_byte(0x9B);
+ emit_byte(0xDB);
+ emit_byte(0xE3);
+}
+
+void Assembler::fist_s(Address adr) {
+ InstructionMark im(this);
+ emit_byte(0xDB);
+ emit_operand32(rdx, adr);
+}
+
+void Assembler::fistp_d(Address adr) {
+ InstructionMark im(this);
+ emit_byte(0xDF);
+ emit_operand32(rdi, adr);
+}
+
+void Assembler::fistp_s(Address adr) {
+ InstructionMark im(this);
+ emit_byte(0xDB);
+ emit_operand32(rbx, adr);
+}
+
+void Assembler::fld1() {
+ emit_byte(0xD9);
+ emit_byte(0xE8);
+}
+
+void Assembler::fld_d(Address adr) {
+ InstructionMark im(this);
+ emit_byte(0xDD);
+ emit_operand32(rax, adr);
+}
+
+void Assembler::fld_s(Address adr) {
+ InstructionMark im(this);
+ emit_byte(0xD9);
+ emit_operand32(rax, adr);
+}
+
+
+void Assembler::fld_s(int index) {
+ emit_farith(0xD9, 0xC0, index);
+}
+
+void Assembler::fld_x(Address adr) {
+ InstructionMark im(this);
+ emit_byte(0xDB);
+ emit_operand32(rbp, adr);
+}
+
+void Assembler::fldcw(Address src) {
+ InstructionMark im(this);
+ emit_byte(0xd9);
+ emit_operand32(rbp, src);
+}
+
+void Assembler::fldenv(Address src) {
+ InstructionMark im(this);
+ emit_byte(0xD9);
+ emit_operand32(rsp, src);
+}
+
+void Assembler::fldlg2() {
+ emit_byte(0xD9);
+ emit_byte(0xEC);
+}
+
+void Assembler::fldln2() {
+ emit_byte(0xD9);
+ emit_byte(0xED);
+}
+
+void Assembler::fldz() {
+ emit_byte(0xD9);
+ emit_byte(0xEE);
+}
+
+void Assembler::flog() {
+ fldln2();
+ fxch();
+ fyl2x();
+}
+
+void Assembler::flog10() {
+ fldlg2();
+ fxch();
+ fyl2x();
+}
+
+void Assembler::fmul(int i) {
+ emit_farith(0xD8, 0xC8, i);
+}
+
+void Assembler::fmul_d(Address src) {
+ InstructionMark im(this);
+ emit_byte(0xDC);
+ emit_operand32(rcx, src);
+}
+
+void Assembler::fmul_s(Address src) {
+ InstructionMark im(this);
+ emit_byte(0xD8);
+ emit_operand32(rcx, src);
+}
+
+void Assembler::fmula(int i) {
+ emit_farith(0xDC, 0xC8, i);
+}
+
+void Assembler::fmulp(int i) {
+ emit_farith(0xDE, 0xC8, i);
+}
+
+void Assembler::fnsave(Address dst) {
+ InstructionMark im(this);
+ emit_byte(0xDD);
+ emit_operand32(rsi, dst);
+}
+
+void Assembler::fnstcw(Address src) {
+ InstructionMark im(this);
+ emit_byte(0x9B);
+ emit_byte(0xD9);
+ emit_operand32(rdi, src);
+}
+
+void Assembler::fnstsw_ax() {
+ emit_byte(0xdF);
+ emit_byte(0xE0);
+}
+
+void Assembler::fprem() {
+ emit_byte(0xD9);
+ emit_byte(0xF8);
+}
+
+void Assembler::fprem1() {
+ emit_byte(0xD9);
+ emit_byte(0xF5);
+}
+
+void Assembler::frstor(Address src) {
+ InstructionMark im(this);
+ emit_byte(0xDD);
+ emit_operand32(rsp, src);
+}
+
+void Assembler::fsin() {
+ emit_byte(0xD9);
+ emit_byte(0xFE);
+}
+
+void Assembler::fsqrt() {
+ emit_byte(0xD9);
+ emit_byte(0xFA);
+}
+
+void Assembler::fst_d(Address adr) {
+ InstructionMark im(this);
+ emit_byte(0xDD);
+ emit_operand32(rdx, adr);
+}
+
+void Assembler::fst_s(Address adr) {
+ InstructionMark im(this);
+ emit_byte(0xD9);
+ emit_operand32(rdx, adr);
+}
+
+void Assembler::fstp_d(Address adr) {
+ InstructionMark im(this);
+ emit_byte(0xDD);
+ emit_operand32(rbx, adr);
+}
+
+void Assembler::fstp_d(int index) {
+ emit_farith(0xDD, 0xD8, index);
+}
+
+void Assembler::fstp_s(Address adr) {
+ InstructionMark im(this);
+ emit_byte(0xD9);
+ emit_operand32(rbx, adr);
+}
+
+void Assembler::fstp_x(Address adr) {
+ InstructionMark im(this);
+ emit_byte(0xDB);
+ emit_operand32(rdi, adr);
+}
+
+void Assembler::fsub(int i) {
+ emit_farith(0xD8, 0xE0, i);
+}
+
+void Assembler::fsub_d(Address src) {
+ InstructionMark im(this);
+ emit_byte(0xDC);
+ emit_operand32(rsp, src);
+}
+
+void Assembler::fsub_s(Address src) {
+ InstructionMark im(this);
+ emit_byte(0xD8);
+ emit_operand32(rsp, src);
+}
+
+void Assembler::fsuba(int i) {
+ emit_farith(0xDC, 0xE8, i);
+}
+
+void Assembler::fsubp(int i) {
+ emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
+}
+
+void Assembler::fsubr(int i) {
+ emit_farith(0xD8, 0xE8, i);
+}
+
+void Assembler::fsubr_d(Address src) {
+ InstructionMark im(this);
+ emit_byte(0xDC);
+ emit_operand32(rbp, src);
+}
+
+void Assembler::fsubr_s(Address src) {
+ InstructionMark im(this);
+ emit_byte(0xD8);
+ emit_operand32(rbp, src);
+}
+
+void Assembler::fsubra(int i) {
+ emit_farith(0xDC, 0xE0, i);
+}
+
+void Assembler::fsubrp(int i) {
+ emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
+}
+
+void Assembler::ftan() {
+ emit_byte(0xD9);
+ emit_byte(0xF2);
+ emit_byte(0xDD);
+ emit_byte(0xD8);
+}
+
+void Assembler::ftst() {
+ emit_byte(0xD9);
+ emit_byte(0xE4);
+}
+
+void Assembler::fucomi(int i) {
+ // make sure the instruction is supported (introduced for P6, together with cmov)
+ guarantee(VM_Version::supports_cmov(), "illegal instruction");
+ emit_farith(0xDB, 0xE8, i);
+}
+
+void Assembler::fucomip(int i) {
+ // make sure the instruction is supported (introduced for P6, together with cmov)
+ guarantee(VM_Version::supports_cmov(), "illegal instruction");
+ emit_farith(0xDF, 0xE8, i);
+}
+
+void Assembler::fwait() {
+ emit_byte(0x9B);
+}
+
+void Assembler::fxch(int i) {
+ emit_farith(0xD9, 0xC8, i);
+}
+
+void Assembler::fyl2x() {
+ emit_byte(0xD9);
+ emit_byte(0xF1);
+}
+
+void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec, int format) {
+ InstructionMark im(this);
+ int encode = prefix_and_encode(dst->encoding());
+ emit_byte(0xB8 | encode);
+ emit_data((int)imm32, rspec, format);
+}
+
+#ifndef _LP64
+
+void Assembler::incl(Register dst) {
+ // Don't use it directly. Use MacroAssembler::incrementl() instead.
+ emit_byte(0x40 | dst->encoding());
+}
+
+void Assembler::lea(Register dst, Address src) {
+ leal(dst, src);
+}
+
+void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
+ InstructionMark im(this);
+ emit_byte(0xC7);
+ emit_operand(rax, dst);
+ emit_data((int)imm32, rspec, 0);
+}
+
+
+void Assembler::popa() { // 32bit
+ emit_byte(0x61);
+}
+
+void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
+ InstructionMark im(this);
+ emit_byte(0x68);
+ emit_data(imm32, rspec, 0);
+}
+
+void Assembler::pusha() { // 32bit
+ emit_byte(0x60);
+}
+
+void Assembler::set_byte_if_not_zero(Register dst) {
+ emit_byte(0x0F);
+ emit_byte(0x95);
+ emit_byte(0xE0 | dst->encoding());
+}
+
+void Assembler::shldl(Register dst, Register src) {
+ emit_byte(0x0F);
+ emit_byte(0xA5);
+ emit_byte(0xC0 | src->encoding() << 3 | dst->encoding());
+}
+
+void Assembler::shrdl(Register dst, Register src) {
+ emit_byte(0x0F);
+ emit_byte(0xAD);
+ emit_byte(0xC0 | src->encoding() << 3 | dst->encoding());
+}
+
+#else // LP64
+
+// 64bit only pieces of the assembler
+// This should only be used by 64bit instructions that can use rip-relative
+// it cannot be used by instructions that want an immediate value.
+
+bool Assembler::reachable(AddressLiteral adr) {
+ int64_t disp;
+ // None will force a 64bit literal to the code stream. Likely a placeholder
+ // for something that will be patched later and we need to certain it will
+ // always be reachable.
+ if (adr.reloc() == relocInfo::none) {
+ return false;
+ }
+ if (adr.reloc() == relocInfo::internal_word_type) {
+ // This should be rip relative and easily reachable.
+ return true;
+ }
+ if (adr.reloc() == relocInfo::virtual_call_type ||
+ adr.reloc() == relocInfo::opt_virtual_call_type ||
+ adr.reloc() == relocInfo::static_call_type ||
+ adr.reloc() == relocInfo::static_stub_type ) {
+ // This should be rip relative within the code cache and easily
+ // reachable until we get huge code caches. (At which point
+ // ic code is going to have issues).
+ return true;
+ }
+ if (adr.reloc() != relocInfo::external_word_type &&
+ adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
+ adr.reloc() != relocInfo::poll_type && // relocs to identify them
+ adr.reloc() != relocInfo::runtime_call_type ) {
+ return false;
+ }
+
+ // Stress the correction code
+ if (ForceUnreachable) {
+ // Must be runtimecall reloc, see if it is in the codecache
+ // Flipping stuff in the codecache to be unreachable causes issues
+ // with things like inline caches where the additional instructions
+ // are not handled.
+ if (CodeCache::find_blob(adr._target) == NULL) {
+ return false;
+ }
+ }
+ // For external_word_type/runtime_call_type if it is reachable from where we
+ // are now (possibly a temp buffer) and where we might end up
+ // anywhere in the codeCache then we are always reachable.
+ // This would have to change if we ever save/restore shared code
+ // to be more pessimistic.
+
+ disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
+ if (!is_simm32(disp)) return false;
+ disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
+ if (!is_simm32(disp)) return false;
+
+ disp = (int64_t)adr._target - ((int64_t)_code_pos + sizeof(int));
+
+ // Because rip relative is a disp + address_of_next_instruction and we
+ // don't know the value of address_of_next_instruction we apply a fudge factor
+ // to make sure we will be ok no matter the size of the instruction we get placed into.
+ // We don't have to fudge the checks above here because they are already worst case.
+
+ // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
+ // + 4 because better safe than sorry.
+ const int fudge = 12 + 4;
+ if (disp < 0) {
+ disp -= fudge;
+ } else {
+ disp += fudge;
+ }
+ return is_simm32(disp);
+}
+
+void Assembler::emit_data64(jlong data,
+ relocInfo::relocType rtype,
+ int format) {
+ if (rtype == relocInfo::none) {
+ emit_long64(data);
+ } else {
+ emit_data64(data, Relocation::spec_simple(rtype), format);
+ }
+}
+
+void Assembler::emit_data64(jlong data,
+ RelocationHolder const& rspec,
+ int format) {
+ assert(imm_operand == 0, "default format must be immediate in this file");
+ assert(imm_operand == format, "must be immediate");
+ assert(inst_mark() != NULL, "must be inside InstructionMark");
+ // Do not use AbstractAssembler::relocate, which is not intended for
+ // embedded words. Instead, relocate to the enclosing instruction.
+ code_section()->relocate(inst_mark(), rspec, format);
+#ifdef ASSERT
+ check_relocation(rspec, format);
+#endif
+ emit_long64(data);
+}
+
+int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
+ if (reg_enc >= 8) {
+ prefix(REX_B);
+ reg_enc -= 8;
+ } else if (byteinst && reg_enc >= 4) {
+ prefix(REX);
+ }
+ return reg_enc;
+}
+
+int Assembler::prefixq_and_encode(int reg_enc) {
+ if (reg_enc < 8) {
+ prefix(REX_W);
+ } else {
+ prefix(REX_WB);
+ reg_enc -= 8;
+ }
+ return reg_enc;
+}
+
+int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) {
+ if (dst_enc < 8) {
+ if (src_enc >= 8) {
+ prefix(REX_B);
+ src_enc -= 8;
+ } else if (byteinst && src_enc >= 4) {
+ prefix(REX);
+ }
+ } else {
+ if (src_enc < 8) {
+ prefix(REX_R);
+ } else {
+ prefix(REX_RB);
+ src_enc -= 8;
+ }
+ dst_enc -= 8;
+ }
+ return dst_enc << 3 | src_enc;
+}
+
+int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
+ if (dst_enc < 8) {
+ if (src_enc < 8) {
+ prefix(REX_W);
+ } else {
+ prefix(REX_WB);
+ src_enc -= 8;
+ }
+ } else {
+ if (src_enc < 8) {
+ prefix(REX_WR);
+ } else {
+ prefix(REX_WRB);
+ src_enc -= 8;
+ }
+ dst_enc -= 8;
+ }
+ return dst_enc << 3 | src_enc;
+}
+
+void Assembler::prefix(Register reg) {
+ if (reg->encoding() >= 8) {
+ prefix(REX_B);
+ }
+}
+
+void Assembler::prefix(Address adr) {
+ if (adr.base_needs_rex()) {
+ if (adr.index_needs_rex()) {
+ prefix(REX_XB);
+ } else {
+ prefix(REX_B);
+ }
+ } else {
+ if (adr.index_needs_rex()) {
+ prefix(REX_X);
+ }
+ }
+}
+
+void Assembler::prefixq(Address adr) {
+ if (adr.base_needs_rex()) {
+ if (adr.index_needs_rex()) {
+ prefix(REX_WXB);
+ } else {
+ prefix(REX_WB);
+ }
+ } else {
+ if (adr.index_needs_rex()) {
+ prefix(REX_WX);
+ } else {
+ prefix(REX_W);
+ }
+ }
+}
+
+
+void Assembler::prefix(Address adr, Register reg, bool byteinst) {
+ if (reg->encoding() < 8) {
+ if (adr.base_needs_rex()) {
+ if (adr.index_needs_rex()) {
+ prefix(REX_XB);
+ } else {
+ prefix(REX_B);
+ }
+ } else {
+ if (adr.index_needs_rex()) {
+ prefix(REX_X);
+ } else if (reg->encoding() >= 4 ) {
+ prefix(REX);
+ }
+ }
+ } else {
+ if (adr.base_needs_rex()) {
+ if (adr.index_needs_rex()) {
+ prefix(REX_RXB);
+ } else {
+ prefix(REX_RB);
+ }
+ } else {
+ if (adr.index_needs_rex()) {
+ prefix(REX_RX);
+ } else {
+ prefix(REX_R);
+ }
+ }
+ }
+}
+
+void Assembler::prefixq(Address adr, Register src) {
+ if (src->encoding() < 8) {
+ if (adr.base_needs_rex()) {
+ if (adr.index_needs_rex()) {
+ prefix(REX_WXB);
+ } else {
+ prefix(REX_WB);
+ }
+ } else {
+ if (adr.index_needs_rex()) {
+ prefix(REX_WX);
+ } else {
+ prefix(REX_W);
+ }
+ }
+ } else {
+ if (adr.base_needs_rex()) {
+ if (adr.index_needs_rex()) {
+ prefix(REX_WRXB);
+ } else {
+ prefix(REX_WRB);
+ }
+ } else {
+ if (adr.index_needs_rex()) {
+ prefix(REX_WRX);
+ } else {
+ prefix(REX_WR);
+ }
+ }
+ }
+}
+
+void Assembler::prefix(Address adr, XMMRegister reg) {
+ if (reg->encoding() < 8) {
+ if (adr.base_needs_rex()) {
+ if (adr.index_needs_rex()) {
+ prefix(REX_XB);
+ } else {
+ prefix(REX_B);
+ }
+ } else {
+ if (adr.index_needs_rex()) {
+ prefix(REX_X);
+ }
+ }
+ } else {
+ if (adr.base_needs_rex()) {
+ if (adr.index_needs_rex()) {
+ prefix(REX_RXB);
+ } else {
+ prefix(REX_RB);
+ }
+ } else {
+ if (adr.index_needs_rex()) {
+ prefix(REX_RX);
+ } else {
+ prefix(REX_R);
+ }
+ }
+ }
+}
+
+void Assembler::adcq(Register dst, int32_t imm32) {
+ (void) prefixq_and_encode(dst->encoding());
+ emit_arith(0x81, 0xD0, dst, imm32);
+}
+
+void Assembler::adcq(Register dst, Address src) {
+ InstructionMark im(this);
+ prefixq(src, dst);
+ emit_byte(0x13);
+ emit_operand(dst, src);
+}
+
+void Assembler::adcq(Register dst, Register src) {
+ (int) prefixq_and_encode(dst->encoding(), src->encoding());
+ emit_arith(0x13, 0xC0, dst, src);
+}
+
+void Assembler::addq(Address dst, int32_t imm32) {
+ InstructionMark im(this);
+ prefixq(dst);
+ emit_arith_operand(0x81, rax, dst,imm32);
+}
+
+void Assembler::addq(Address dst, Register src) {
+ InstructionMark im(this);
+ prefixq(dst, src);
+ emit_byte(0x01);
+ emit_operand(src, dst);
+}
+
+void Assembler::addq(Register dst, int32_t imm32) {
+ (void) prefixq_and_encode(dst->encoding());
+ emit_arith(0x81, 0xC0, dst, imm32);
+}
+
+void Assembler::addq(Register dst, Address src) {
+ InstructionMark im(this);
+ prefixq(src, dst);
+ emit_byte(0x03);
+ emit_operand(dst, src);
+}
+
+void Assembler::addq(Register dst, Register src) {
+ (void) prefixq_and_encode(dst->encoding(), src->encoding());
+ emit_arith(0x03, 0xC0, dst, src);
+}
+
+void Assembler::andq(Register dst, int32_t imm32) {
+ (void) prefixq_and_encode(dst->encoding());
+ emit_arith(0x81, 0xE0, dst, imm32);
+}
+
+void Assembler::andq(Register dst, Address src) {
+ InstructionMark im(this);
+ prefixq(src, dst);
+ emit_byte(0x23);
+ emit_operand(dst, src);
+}
+
+void Assembler::andq(Register dst, Register src) {
+ (int) prefixq_and_encode(dst->encoding(), src->encoding());
+ emit_arith(0x23, 0xC0, dst, src);
+}
+
+void Assembler::bswapq(Register reg) {
+ int encode = prefixq_and_encode(reg->encoding());
+ emit_byte(0x0F);
+ emit_byte(0xC8 | encode);
+}
+
+void Assembler::cdqq() {
+ prefix(REX_W);
+ emit_byte(0x99);
+}
+
void Assembler::clflush(Address adr) {
prefix(adr);
emit_byte(0x0F);
@@ -2925,185 +3614,119 @@ void Assembler::clflush(Address adr) {
emit_operand(rdi, adr);
}
-void Assembler::call(Label& L, relocInfo::relocType rtype) {
- if (L.is_bound()) {
- const int long_size = 5;
- int offs = (int)( target(L) - pc() );
- assert(offs <= 0, "assembler error");
- InstructionMark im(this);
- // 1110 1000 #32-bit disp
- emit_byte(0xE8);
- emit_data(offs - long_size, rtype, disp32_operand);
- } else {
- InstructionMark im(this);
- // 1110 1000 #32-bit disp
- L.add_patch_at(code(), locator());
-
- emit_byte(0xE8);
- emit_data(int(0), rtype, disp32_operand);
- }
+void Assembler::cmovq(Condition cc, Register dst, Register src) {
+ int encode = prefixq_and_encode(dst->encoding(), src->encoding());
+ emit_byte(0x0F);
+ emit_byte(0x40 | cc);
+ emit_byte(0xC0 | encode);
}
-void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
- assert(entry != NULL, "call most probably wrong");
+void Assembler::cmovq(Condition cc, Register dst, Address src) {
InstructionMark im(this);
- emit_byte(0xE8);
- intptr_t disp = entry - (_code_pos + sizeof(int32_t));
- assert(is_simm32(disp), "must be 32bit offset (call2)");
- // Technically, should use call32_operand, but this format is
- // implied by the fact that we're emitting a call instruction.
- emit_data((int) disp, rspec, disp32_operand);
+ prefixq(src, dst);
+ emit_byte(0x0F);
+ emit_byte(0x40 | cc);
+ emit_operand(dst, src);
}
+void Assembler::cmpq(Address dst, int32_t imm32) {
+ InstructionMark im(this);
+ prefixq(dst);
+ emit_byte(0x81);
+ emit_operand(rdi, dst, 4);
+ emit_long(imm32);
+}
-void Assembler::call(Register dst) {
- // This was originally using a 32bit register encoding
- // and surely we want 64bit!
- // this is a 32bit encoding but in 64bit mode the default
- // operand size is 64bit so there is no need for the
- // wide prefix. So prefix only happens if we use the
- // new registers. Much like push/pop.
+void Assembler::cmpq(Register dst, int32_t imm32) {
+ (void) prefixq_and_encode(dst->encoding());
+ emit_arith(0x81, 0xF8, dst, imm32);
+}
+
+void Assembler::cmpq(Address dst, Register src) {
+ InstructionMark im(this);
+ prefixq(dst, src);
+ emit_byte(0x3B);
+ emit_operand(src, dst);
+}
+
+void Assembler::cmpq(Register dst, Register src) {
+ (void) prefixq_and_encode(dst->encoding(), src->encoding());
+ emit_arith(0x3B, 0xC0, dst, src);
+}
+
+void Assembler::cmpq(Register dst, Address src) {
+ InstructionMark im(this);
+ prefixq(src, dst);
+ emit_byte(0x3B);
+ emit_operand(dst, src);
+}
+
+void Assembler::cmpxchgq(Register reg, Address adr) {
+ InstructionMark im(this);
+ prefixq(adr, reg);
+ emit_byte(0x0F);
+ emit_byte(0xB1);
+ emit_operand(reg, adr);
+}
+
+void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ emit_byte(0xF2);
+ int encode = prefixq_and_encode(dst->encoding(), src->encoding());
+ emit_byte(0x0F);
+ emit_byte(0x2A);
+ emit_byte(0xC0 | encode);
+}
+
+void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
+ NOT_LP64(assert(VM_Version::supports_sse(), ""));
+ emit_byte(0xF3);
+ int encode = prefixq_and_encode(dst->encoding(), src->encoding());
+ emit_byte(0x0F);
+ emit_byte(0x2A);
+ emit_byte(0xC0 | encode);
+}
+
+void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+ emit_byte(0xF2);
+ int encode = prefixq_and_encode(dst->encoding(), src->encoding());
+ emit_byte(0x0F);
+ emit_byte(0x2C);
+ emit_byte(0xC0 | encode);
+}
+
+void Assembler::cvttss2siq(Register dst, XMMRegister src) {
+ NOT_LP64(assert(VM_Version::supports_sse(), ""));
+ emit_byte(0xF3);
+ int encode = prefixq_and_encode(dst->encoding(), src->encoding());
+ emit_byte(0x0F);
+ emit_byte(0x2C);
+ emit_byte(0xC0 | encode);
+}
+
+void Assembler::decl(Register dst) {
+ // Don't use it directly. Use MacroAssembler::decrementl() instead.
+ // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
+ int encode = prefix_and_encode(dst->encoding());
+ emit_byte(0xFF);
+ emit_byte(0xC8 | encode);
+}
+
+void Assembler::decq(Register dst) {
+ // Don't use it directly. Use MacroAssembler::decrementq() instead.
+ // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
int encode = prefixq_and_encode(dst->encoding());
emit_byte(0xFF);
- emit_byte(0xD0 | encode);
+ emit_byte(0xC8 | encode);
}
-void Assembler::call(Address adr) {
+void Assembler::decq(Address dst) {
+ // Don't use it directly. Use MacroAssembler::decrementq() instead.
InstructionMark im(this);
- prefix(adr);
- emit_byte(0xFF);
- emit_operand(rdx, adr);
-}
-
-void Assembler::jmp(Register reg) {
- int encode = prefix_and_encode(reg->encoding());
- emit_byte(0xFF);
- emit_byte(0xE0 | encode);
-}
-
-void Assembler::jmp(Address adr) {
- InstructionMark im(this);
- prefix(adr);
- emit_byte(0xFF);
- emit_operand(rsp, adr);
-}
-
-void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
- InstructionMark im(this);
- emit_byte(0xE9);
- assert(dest != NULL, "must have a target");
- intptr_t disp = dest - (_code_pos + sizeof(int32_t));
- assert(is_simm32(disp), "must be 32bit offset (jmp)");
- emit_data(disp, rspec.reloc(), call32_operand);
-}
-
-void Assembler::jmp(Label& L, relocInfo::relocType rtype) {
- if (L.is_bound()) {
- address entry = target(L);
- assert(entry != NULL, "jmp most probably wrong");
- InstructionMark im(this);
- const int short_size = 2;
- const int long_size = 5;
- intptr_t offs = entry - _code_pos;
- if (rtype == relocInfo::none && is8bit(offs - short_size)) {
- emit_byte(0xEB);
- emit_byte((offs - short_size) & 0xFF);
- } else {
- emit_byte(0xE9);
- emit_long(offs - long_size);
- }
- } else {
- // By default, forward jumps are always 32-bit displacements, since
- // we can't yet know where the label will be bound. If you're sure that
- // the forward jump will not run beyond 256 bytes, use jmpb to
- // force an 8-bit displacement.
- InstructionMark im(this);
- relocate(rtype);
- L.add_patch_at(code(), locator());
- emit_byte(0xE9);
- emit_long(0);
- }
-}
-
-void Assembler::jmpb(Label& L) {
- if (L.is_bound()) {
- const int short_size = 2;
- address entry = target(L);
- assert(is8bit((entry - _code_pos) + short_size),
- "Dispacement too large for a short jmp");
- assert(entry != NULL, "jmp most probably wrong");
- intptr_t offs = entry - _code_pos;
- emit_byte(0xEB);
- emit_byte((offs - short_size) & 0xFF);
- } else {
- InstructionMark im(this);
- L.add_patch_at(code(), locator());
- emit_byte(0xEB);
- emit_byte(0);
- }
-}
-
-void Assembler::jcc(Condition cc, Label& L, relocInfo::relocType rtype) {
- InstructionMark im(this);
- relocate(rtype);
- assert((0 <= cc) && (cc < 16), "illegal cc");
- if (L.is_bound()) {
- address dst = target(L);
- assert(dst != NULL, "jcc most probably wrong");
-
- const int short_size = 2;
- const int long_size = 6;
- intptr_t offs = (intptr_t)dst - (intptr_t)_code_pos;
- if (rtype == relocInfo::none && is8bit(offs - short_size)) {
- // 0111 tttn #8-bit disp
- emit_byte(0x70 | cc);
- emit_byte((offs - short_size) & 0xFF);
- } else {
- // 0000 1111 1000 tttn #32-bit disp
- assert(is_simm32(offs - long_size),
- "must be 32bit offset (call4)");
- emit_byte(0x0F);
- emit_byte(0x80 | cc);
- emit_long(offs - long_size);
- }
- } else {
- // Note: could eliminate cond. jumps to this jump if condition
- // is the same however, seems to be rather unlikely case.
- // Note: use jccb() if label to be bound is very close to get
- // an 8-bit displacement
- L.add_patch_at(code(), locator());
- emit_byte(0x0F);
- emit_byte(0x80 | cc);
- emit_long(0);
- }
-}
-
-void Assembler::jccb(Condition cc, Label& L) {
- if (L.is_bound()) {
- const int short_size = 2;
- const int long_size = 6;
- address entry = target(L);
- assert(is8bit((intptr_t)entry - ((intptr_t)_code_pos + short_size)),
- "Dispacement too large for a short jmp");
- intptr_t offs = (intptr_t)entry - (intptr_t)_code_pos;
- // 0111 tttn #8-bit disp
- emit_byte(0x70 | cc);
- emit_byte((offs - short_size) & 0xFF);
- } else {
- InstructionMark im(this);
- L.add_patch_at(code(), locator());
- emit_byte(0x70 | cc);
- emit_byte(0);
- }
-}
-
-// FP instructions
-
-void Assembler::fxsave(Address dst) {
prefixq(dst);
- emit_byte(0x0F);
- emit_byte(0xAE);
- emit_operand(as_Register(0), dst);
+ emit_byte(0xFF);
+ emit_operand(rcx, dst);
}
void Assembler::fxrstor(Address src) {
@@ -3113,167 +3736,347 @@ void Assembler::fxrstor(Address src) {
emit_operand(as_Register(1), src);
}
-void Assembler::ldmxcsr(Address src) {
- InstructionMark im(this);
- prefix(src);
+void Assembler::fxsave(Address dst) {
+ prefixq(dst);
emit_byte(0x0F);
emit_byte(0xAE);
- emit_operand(as_Register(2), src);
+ emit_operand(as_Register(0), dst);
}
-void Assembler::stmxcsr(Address dst) {
- InstructionMark im(this);
- prefix(dst);
- emit_byte(0x0F);
- emit_byte(0xAE);
- emit_operand(as_Register(3), dst);
+void Assembler::idivq(Register src) {
+ int encode = prefixq_and_encode(src->encoding());
+ emit_byte(0xF7);
+ emit_byte(0xF8 | encode);
}
-void Assembler::addss(XMMRegister dst, XMMRegister src) {
- emit_byte(0xF3);
- int encode = prefix_and_encode(dst->encoding(), src->encoding());
+void Assembler::imulq(Register dst, Register src) {
+ int encode = prefixq_and_encode(dst->encoding(), src->encoding());
emit_byte(0x0F);
- emit_byte(0x58);
+ emit_byte(0xAF);
emit_byte(0xC0 | encode);
}
-void Assembler::addss(XMMRegister dst, Address src) {
+void Assembler::imulq(Register dst, Register src, int value) {
+ int encode = prefixq_and_encode(dst->encoding(), src->encoding());
+ if (is8bit(value)) {
+ emit_byte(0x6B);
+ emit_byte(0xC0 | encode);
+ emit_byte(value);
+ } else {
+ emit_byte(0x69);
+ emit_byte(0xC0 | encode);
+ emit_long(value);
+ }
+}
+
+void Assembler::incl(Register dst) {
+ // Don't use it directly. Use MacroAssembler::incrementl() instead.
+ // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
+ int encode = prefix_and_encode(dst->encoding());
+ emit_byte(0xFF);
+ emit_byte(0xC0 | encode);
+}
+
+void Assembler::incq(Register dst) {
+ // Don't use it directly. Use MacroAssembler::incrementq() instead.
+ // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
+ int encode = prefixq_and_encode(dst->encoding());
+ emit_byte(0xFF);
+ emit_byte(0xC0 | encode);
+}
+
+void Assembler::incq(Address dst) {
+ // Don't use it directly. Use MacroAssembler::incrementq() instead.
InstructionMark im(this);
- emit_byte(0xF3);
- prefix(src, dst);
- emit_byte(0x0F);
- emit_byte(0x58);
+ prefixq(dst);
+ emit_byte(0xFF);
+ emit_operand(rax, dst);
+}
+
+void Assembler::lea(Register dst, Address src) {
+ leaq(dst, src);
+}
+
+void Assembler::leaq(Register dst, Address src) {
+ InstructionMark im(this);
+ prefixq(src, dst);
+ emit_byte(0x8D);
emit_operand(dst, src);
}
-void Assembler::subss(XMMRegister dst, XMMRegister src) {
- emit_byte(0xF3);
- int encode = prefix_and_encode(dst->encoding(), src->encoding());
+void Assembler::mov64(Register dst, int64_t imm64) {
+ InstructionMark im(this);
+ int encode = prefixq_and_encode(dst->encoding());
+ emit_byte(0xB8 | encode);
+ emit_long64(imm64);
+}
+
+void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
+ InstructionMark im(this);
+ int encode = prefixq_and_encode(dst->encoding());
+ emit_byte(0xB8 | encode);
+ emit_data64(imm64, rspec);
+}
+
+void Assembler::movdq(XMMRegister dst, Register src) {
+ // table D-1 says MMX/SSE2
+ NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), ""));
+ emit_byte(0x66);
+ int encode = prefixq_and_encode(dst->encoding(), src->encoding());
emit_byte(0x0F);
- emit_byte(0x5C);
+ emit_byte(0x6E);
emit_byte(0xC0 | encode);
}
-void Assembler::subss(XMMRegister dst, Address src) {
- InstructionMark im(this);
- emit_byte(0xF3);
- prefix(src, dst);
+void Assembler::movdq(Register dst, XMMRegister src) {
+ // table D-1 says MMX/SSE2
+ NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), ""));
+ emit_byte(0x66);
+ // swap src/dst to get correct prefix
+ int encode = prefixq_and_encode(src->encoding(), dst->encoding());
emit_byte(0x0F);
- emit_byte(0x5C);
+ emit_byte(0x7E);
+ emit_byte(0xC0 | encode);
+}
+
+void Assembler::movq(Register dst, Register src) {
+ int encode = prefixq_and_encode(dst->encoding(), src->encoding());
+ emit_byte(0x8B);
+ emit_byte(0xC0 | encode);
+}
+
+void Assembler::movq(Register dst, Address src) {
+ InstructionMark im(this);
+ prefixq(src, dst);
+ emit_byte(0x8B);
emit_operand(dst, src);
}
-void Assembler::mulss(XMMRegister dst, XMMRegister src) {
- emit_byte(0xF3);
- int encode = prefix_and_encode(dst->encoding(), src->encoding());
- emit_byte(0x0F);
- emit_byte(0x59);
- emit_byte(0xC0 | encode);
+void Assembler::movq(Address dst, Register src) {
+ InstructionMark im(this);
+ prefixq(dst, src);
+ emit_byte(0x89);
+ emit_operand(src, dst);
}
-void Assembler::mulss(XMMRegister dst, Address src) {
+void Assembler::movslq(Register dst, int32_t imm32) {
+ // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
+ // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
+ // as a result we shouldn't use until tested at runtime...
+ ShouldNotReachHere();
InstructionMark im(this);
- emit_byte(0xF3);
- prefix(src, dst);
- emit_byte(0x0F);
- emit_byte(0x59);
+ int encode = prefixq_and_encode(dst->encoding());
+ emit_byte(0xC7 | encode);
+ emit_long(imm32);
+}
+
+void Assembler::movslq(Address dst, int32_t imm32) {
+ assert(is_simm32(imm32), "lost bits");
+ InstructionMark im(this);
+ prefixq(dst);
+ emit_byte(0xC7);
+ emit_operand(rax, dst, 4);
+ emit_long(imm32);
+}
+
+void Assembler::movslq(Register dst, Address src) {
+ InstructionMark im(this);
+ prefixq(src, dst);
+ emit_byte(0x63);
emit_operand(dst, src);
}
-void Assembler::divss(XMMRegister dst, XMMRegister src) {
- emit_byte(0xF3);
- int encode = prefix_and_encode(dst->encoding(), src->encoding());
- emit_byte(0x0F);
- emit_byte(0x5E);
+void Assembler::movslq(Register dst, Register src) {
+ int encode = prefixq_and_encode(dst->encoding(), src->encoding());
+ emit_byte(0x63);
emit_byte(0xC0 | encode);
}
-void Assembler::divss(XMMRegister dst, Address src) {
+void Assembler::negq(Register dst) {
+ int encode = prefixq_and_encode(dst->encoding());
+ emit_byte(0xF7);
+ emit_byte(0xD8 | encode);
+}
+
+void Assembler::notq(Register dst) {
+ int encode = prefixq_and_encode(dst->encoding());
+ emit_byte(0xF7);
+ emit_byte(0xD0 | encode);
+}
+
+void Assembler::orq(Address dst, int32_t imm32) {
InstructionMark im(this);
- emit_byte(0xF3);
- prefix(src, dst);
- emit_byte(0x0F);
- emit_byte(0x5E);
+ prefixq(dst);
+ emit_byte(0x81);
+ emit_operand(rcx, dst, 4);
+ emit_long(imm32);
+}
+
+void Assembler::orq(Register dst, int32_t imm32) {
+ (void) prefixq_and_encode(dst->encoding());
+ emit_arith(0x81, 0xC8, dst, imm32);
+}
+
+void Assembler::orq(Register dst, Address src) {
+ InstructionMark im(this);
+ prefixq(src, dst);
+ emit_byte(0x0B);
emit_operand(dst, src);
}
-void Assembler::addsd(XMMRegister dst, XMMRegister src) {
- emit_byte(0xF2);
- int encode = prefix_and_encode(dst->encoding(), src->encoding());
- emit_byte(0x0F);
- emit_byte(0x58);
- emit_byte(0xC0 | encode);
+void Assembler::orq(Register dst, Register src) {
+ (void) prefixq_and_encode(dst->encoding(), src->encoding());
+ emit_arith(0x0B, 0xC0, dst, src);
}
-void Assembler::addsd(XMMRegister dst, Address src) {
+void Assembler::popa() { // 64bit
+ movq(r15, Address(rsp, 0));
+ movq(r14, Address(rsp, wordSize));
+ movq(r13, Address(rsp, 2 * wordSize));
+ movq(r12, Address(rsp, 3 * wordSize));
+ movq(r11, Address(rsp, 4 * wordSize));
+ movq(r10, Address(rsp, 5 * wordSize));
+ movq(r9, Address(rsp, 6 * wordSize));
+ movq(r8, Address(rsp, 7 * wordSize));
+ movq(rdi, Address(rsp, 8 * wordSize));
+ movq(rsi, Address(rsp, 9 * wordSize));
+ movq(rbp, Address(rsp, 10 * wordSize));
+ // skip rsp
+ movq(rbx, Address(rsp, 12 * wordSize));
+ movq(rdx, Address(rsp, 13 * wordSize));
+ movq(rcx, Address(rsp, 14 * wordSize));
+ movq(rax, Address(rsp, 15 * wordSize));
+
+ addq(rsp, 16 * wordSize);
+}
+
+void Assembler::popq(Address dst) {
InstructionMark im(this);
- emit_byte(0xF2);
- prefix(src, dst);
- emit_byte(0x0F);
- emit_byte(0x58);
+ prefixq(dst);
+ emit_byte(0x8F);
+ emit_operand(rax, dst);
+}
+
+void Assembler::pusha() { // 64bit
+ // we have to store original rsp. ABI says that 128 bytes
+ // below rsp are local scratch.
+ movq(Address(rsp, -5 * wordSize), rsp);
+
+ subq(rsp, 16 * wordSize);
+
+ movq(Address(rsp, 15 * wordSize), rax);
+ movq(Address(rsp, 14 * wordSize), rcx);
+ movq(Address(rsp, 13 * wordSize), rdx);
+ movq(Address(rsp, 12 * wordSize), rbx);
+ // skip rsp
+ movq(Address(rsp, 10 * wordSize), rbp);
+ movq(Address(rsp, 9 * wordSize), rsi);
+ movq(Address(rsp, 8 * wordSize), rdi);
+ movq(Address(rsp, 7 * wordSize), r8);
+ movq(Address(rsp, 6 * wordSize), r9);
+ movq(Address(rsp, 5 * wordSize), r10);
+ movq(Address(rsp, 4 * wordSize), r11);
+ movq(Address(rsp, 3 * wordSize), r12);
+ movq(Address(rsp, 2 * wordSize), r13);
+ movq(Address(rsp, wordSize), r14);
+ movq(Address(rsp, 0), r15);
+}
+
+void Assembler::pushq(Address src) {
+ InstructionMark im(this);
+ prefixq(src);
+ emit_byte(0xFF);
+ emit_operand(rsi, src);
+}
+
+void Assembler::rclq(Register dst, int imm8) {
+ assert(isShiftCount(imm8 >> 1), "illegal shift count");
+ int encode = prefixq_and_encode(dst->encoding());
+ if (imm8 == 1) {
+ emit_byte(0xD1);
+ emit_byte(0xD0 | encode);
+ } else {
+ emit_byte(0xC1);
+ emit_byte(0xD0 | encode);
+ emit_byte(imm8);
+ }
+}
+void Assembler::sarq(Register dst, int imm8) {
+ assert(isShiftCount(imm8 >> 1), "illegal shift count");
+ int encode = prefixq_and_encode(dst->encoding());
+ if (imm8 == 1) {
+ emit_byte(0xD1);
+ emit_byte(0xF8 | encode);
+ } else {
+ emit_byte(0xC1);
+ emit_byte(0xF8 | encode);
+ emit_byte(imm8);
+ }
+}
+
+void Assembler::sarq(Register dst) {
+ int encode = prefixq_and_encode(dst->encoding());
+ emit_byte(0xD3);
+ emit_byte(0xF8 | encode);
+}
+void Assembler::sbbq(Address dst, int32_t imm32) {
+ InstructionMark im(this);
+ prefixq(dst);
+ emit_arith_operand(0x81, rbx, dst, imm32);
+}
+
+void Assembler::sbbq(Register dst, int32_t imm32) {
+ (void) prefixq_and_encode(dst->encoding());
+ emit_arith(0x81, 0xD8, dst, imm32);
+}
+
+void Assembler::sbbq(Register dst, Address src) {
+ InstructionMark im(this);
+ prefixq(src, dst);
+ emit_byte(0x1B);
emit_operand(dst, src);
}
-void Assembler::subsd(XMMRegister dst, XMMRegister src) {
- emit_byte(0xF2);
- int encode = prefix_and_encode(dst->encoding(), src->encoding());
- emit_byte(0x0F);
- emit_byte(0x5C);
- emit_byte(0xC0 | encode);
+void Assembler::sbbq(Register dst, Register src) {
+ (void) prefixq_and_encode(dst->encoding(), src->encoding());
+ emit_arith(0x1B, 0xC0, dst, src);
}
-void Assembler::subsd(XMMRegister dst, Address src) {
- InstructionMark im(this);
- emit_byte(0xF2);
- prefix(src, dst);
- emit_byte(0x0F);
- emit_byte(0x5C);
- emit_operand(dst, src);
+void Assembler::shlq(Register dst, int imm8) {
+ assert(isShiftCount(imm8 >> 1), "illegal shift count");
+ int encode = prefixq_and_encode(dst->encoding());
+ if (imm8 == 1) {
+ emit_byte(0xD1);
+ emit_byte(0xE0 | encode);
+ } else {
+ emit_byte(0xC1);
+ emit_byte(0xE0 | encode);
+ emit_byte(imm8);
+ }
}
-void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
- emit_byte(0xF2);
- int encode = prefix_and_encode(dst->encoding(), src->encoding());
- emit_byte(0x0F);
- emit_byte(0x59);
- emit_byte(0xC0 | encode);
+void Assembler::shlq(Register dst) {
+ int encode = prefixq_and_encode(dst->encoding());
+ emit_byte(0xD3);
+ emit_byte(0xE0 | encode);
}
-void Assembler::mulsd(XMMRegister dst, Address src) {
- InstructionMark im(this);
- emit_byte(0xF2);
- prefix(src, dst);
- emit_byte(0x0F);
- emit_byte(0x59);
- emit_operand(dst, src);
+void Assembler::shrq(Register dst, int imm8) {
+ assert(isShiftCount(imm8 >> 1), "illegal shift count");
+ int encode = prefixq_and_encode(dst->encoding());
+ emit_byte(0xC1);
+ emit_byte(0xE8 | encode);
+ emit_byte(imm8);
}
-void Assembler::divsd(XMMRegister dst, XMMRegister src) {
- emit_byte(0xF2);
- int encode = prefix_and_encode(dst->encoding(), src->encoding());
- emit_byte(0x0F);
- emit_byte(0x5E);
- emit_byte(0xC0 | encode);
-}
-
-void Assembler::divsd(XMMRegister dst, Address src) {
- InstructionMark im(this);
- emit_byte(0xF2);
- prefix(src, dst);
- emit_byte(0x0F);
- emit_byte(0x5E);
- emit_operand(dst, src);
-}
-
-void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
- emit_byte(0xF2);
- int encode = prefix_and_encode(dst->encoding(), src->encoding());
- emit_byte(0x0F);
- emit_byte(0x51);
- emit_byte(0xC0 | encode);
+void Assembler::shrq(Register dst) {
+ int encode = prefixq_and_encode(dst->encoding());
+ emit_byte(0xD3);
+ emit_byte(0xE8 | encode);
}
void Assembler::sqrtsd(XMMRegister dst, Address src) {
+ NOT_LP64(assert(VM_Version::supports_sse2(), ""));
InstructionMark im(this);
emit_byte(0xF2);
prefix(src, dst);
@@ -3282,171 +4085,99 @@ void Assembler::sqrtsd(XMMRegister dst, Address src) {
emit_operand(dst, src);
}
-void Assembler::xorps(XMMRegister dst, XMMRegister src) {
- int encode = prefix_and_encode(dst->encoding(), src->encoding());
- emit_byte(0x0F);
- emit_byte(0x57);
- emit_byte(0xC0 | encode);
+void Assembler::subq(Address dst, int32_t imm32) {
+ InstructionMark im(this);
+ prefixq(dst);
+ if (is8bit(imm32)) {
+ emit_byte(0x83);
+ emit_operand(rbp, dst, 1);
+ emit_byte(imm32 & 0xFF);
+ } else {
+ emit_byte(0x81);
+ emit_operand(rbp, dst, 4);
+ emit_long(imm32);
+ }
}
-void Assembler::xorps(XMMRegister dst, Address src) {
+void Assembler::subq(Register dst, int32_t imm32) {
+ (void) prefixq_and_encode(dst->encoding());
+ emit_arith(0x81, 0xE8, dst, imm32);
+}
+
+void Assembler::subq(Address dst, Register src) {
InstructionMark im(this);
- prefix(src, dst);
- emit_byte(0x0F);
- emit_byte(0x57);
+ prefixq(dst, src);
+ emit_byte(0x29);
+ emit_operand(src, dst);
+}
+
+void Assembler::subq(Register dst, Address src) {
+ InstructionMark im(this);
+ prefixq(src, dst);
+ emit_byte(0x2B);
emit_operand(dst, src);
}
-void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
- emit_byte(0x66);
- xorps(dst, src);
+void Assembler::subq(Register dst, Register src) {
+ (void) prefixq_and_encode(dst->encoding(), src->encoding());
+ emit_arith(0x2B, 0xC0, dst, src);
}
-void Assembler::xorpd(XMMRegister dst, Address src) {
+void Assembler::testq(Register dst, int32_t imm32) {
+ // not using emit_arith because test
+ // doesn't support sign-extension of
+ // 8bit operands
+ int encode = dst->encoding();
+ if (encode == 0) {
+ prefix(REX_W);
+ emit_byte(0xA9);
+ } else {
+ encode = prefixq_and_encode(encode);
+ emit_byte(0xF7);
+ emit_byte(0xC0 | encode);
+ }
+ emit_long(imm32);
+}
+
+void Assembler::testq(Register dst, Register src) {
+ (void) prefixq_and_encode(dst->encoding(), src->encoding());
+ emit_arith(0x85, 0xC0, dst, src);
+}
+
+void Assembler::xaddq(Address dst, Register src) {
InstructionMark im(this);
- emit_byte(0x66);
- prefix(src, dst);
+ prefixq(dst, src);
emit_byte(0x0F);
- emit_byte(0x57);
+ emit_byte(0xC1);
+ emit_operand(src, dst);
+}
+
+void Assembler::xchgq(Register dst, Address src) {
+ InstructionMark im(this);
+ prefixq(src, dst);
+ emit_byte(0x87);
emit_operand(dst, src);
}
-void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
- emit_byte(0xF3);
- int encode = prefix_and_encode(dst->encoding(), src->encoding());
- emit_byte(0x0F);
- emit_byte(0x2A);
- emit_byte(0xC0 | encode);
-}
-
-void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
- emit_byte(0xF3);
+void Assembler::xchgq(Register dst, Register src) {
int encode = prefixq_and_encode(dst->encoding(), src->encoding());
- emit_byte(0x0F);
- emit_byte(0x2A);
- emit_byte(0xC0 | encode);
+ emit_byte(0x87);
+ emit_byte(0xc0 | encode);
}
-void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
- emit_byte(0xF2);
- int encode = prefix_and_encode(dst->encoding(), src->encoding());
- emit_byte(0x0F);
- emit_byte(0x2A);
- emit_byte(0xC0 | encode);
+void Assembler::xorq(Register dst, Register src) {
+ (void) prefixq_and_encode(dst->encoding(), src->encoding());
+ emit_arith(0x33, 0xC0, dst, src);
}
-void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
- emit_byte(0xF2);
- int encode = prefixq_and_encode(dst->encoding(), src->encoding());
- emit_byte(0x0F);
- emit_byte(0x2A);
- emit_byte(0xC0 | encode);
+void Assembler::xorq(Register dst, Address src) {
+ InstructionMark im(this);
+ prefixq(src, dst);
+ emit_byte(0x33);
+ emit_operand(dst, src);
}
-void Assembler::cvttss2sil(Register dst, XMMRegister src) {
- emit_byte(0xF3);
- int encode = prefix_and_encode(dst->encoding(), src->encoding());
- emit_byte(0x0F);
- emit_byte(0x2C);
- emit_byte(0xC0 | encode);
-}
-
-void Assembler::cvttss2siq(Register dst, XMMRegister src) {
- emit_byte(0xF3);
- int encode = prefixq_and_encode(dst->encoding(), src->encoding());
- emit_byte(0x0F);
- emit_byte(0x2C);
- emit_byte(0xC0 | encode);
-}
-
-void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
- emit_byte(0xF2);
- int encode = prefix_and_encode(dst->encoding(), src->encoding());
- emit_byte(0x0F);
- emit_byte(0x2C);
- emit_byte(0xC0 | encode);
-}
-
-void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
- emit_byte(0xF2);
- int encode = prefixq_and_encode(dst->encoding(), src->encoding());
- emit_byte(0x0F);
- emit_byte(0x2C);
- emit_byte(0xC0 | encode);
-}
-
-void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
- emit_byte(0xF3);
- int encode = prefix_and_encode(dst->encoding(), src->encoding());
- emit_byte(0x0F);
- emit_byte(0x5A);
- emit_byte(0xC0 | encode);
-}
-
-void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
- emit_byte(0xF3);
- int encode = prefix_and_encode(dst->encoding(), src->encoding());
- emit_byte(0x0F);
- emit_byte(0xE6);
- emit_byte(0xC0 | encode);
-}
-
-void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
- int encode = prefix_and_encode(dst->encoding(), src->encoding());
- emit_byte(0x0F);
- emit_byte(0x5B);
- emit_byte(0xC0 | encode);
-}
-
-void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
- emit_byte(0xF2);
- int encode = prefix_and_encode(dst->encoding(), src->encoding());
- emit_byte(0x0F);
- emit_byte(0x5A);
- emit_byte(0xC0 | encode);
-}
-
-void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
- emit_byte(0x66);
- int encode = prefix_and_encode(dst->encoding(), src->encoding());
- emit_byte(0x0F);
- emit_byte(0x60);
- emit_byte(0xC0 | encode);
-}
-
-// Implementation of MacroAssembler
-
-// On 32 bit it returns a vanilla displacement on 64 bit is a rip relative displacement
-Address MacroAssembler::as_Address(AddressLiteral adr) {
- assert(!adr.is_lval(), "must be rval");
- assert(reachable(adr), "must be");
- return Address((int)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
-}
-
-Address MacroAssembler::as_Address(ArrayAddress adr) {
-#ifdef _LP64
- AddressLiteral base = adr.base();
- lea(rscratch1, base);
- Address index = adr.index();
- assert(index._disp == 0, "must not have disp"); // maybe it can?
- Address array(rscratch1, index._index, index._scale, index._disp);
- return array;
-#else
- return Address::make_array(adr);
-#endif // _LP64
-
-}
-
-void MacroAssembler::fat_nop() {
- // A 5 byte nop that is safe for patching (see patch_verified_entry)
- // Recommened sequence from 'Software Optimization Guide for the AMD
- // Hammer Processor'
- emit_byte(0x66);
- emit_byte(0x66);
- emit_byte(0x90);
- emit_byte(0x66);
- emit_byte(0x90);
-}
+#endif // !LP64
static Assembler::Condition reverse[] = {
Assembler::noOverflow /* overflow = 0x0 */ ,
@@ -3468,1515 +4199,613 @@ static Assembler::Condition reverse[] = {
};
+
+// Implementation of MacroAssembler
+
+// First all the versions that have distinct versions depending on 32/64 bit
+// Unless the difference is trivial (1 line or so).
+
+#ifndef _LP64
+
+// 32bit versions
+
+Address MacroAssembler::as_Address(AddressLiteral adr) {
+ return Address(adr.target(), adr.rspec());
+}
+
+Address MacroAssembler::as_Address(ArrayAddress adr) {
+ return Address::make_array(adr);
+}
+
+int MacroAssembler::biased_locking_enter(Register lock_reg,
+ Register obj_reg,
+ Register swap_reg,
+ Register tmp_reg,
+ bool swap_reg_contains_mark,
+ Label& done,
+ Label* slow_case,
+ BiasedLockingCounters* counters) {
+ assert(UseBiasedLocking, "why call this otherwise?");
+ assert(swap_reg == rax, "swap_reg must be rax, for cmpxchg");
+ assert_different_registers(lock_reg, obj_reg, swap_reg);
+
+ if (PrintBiasedLockingStatistics && counters == NULL)
+ counters = BiasedLocking::counters();
+
+ bool need_tmp_reg = false;
+ if (tmp_reg == noreg) {
+ need_tmp_reg = true;
+ tmp_reg = lock_reg;
+ } else {
+ assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
+ }
+ assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
+ Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
+ Address klass_addr (obj_reg, oopDesc::klass_offset_in_bytes());
+ Address saved_mark_addr(lock_reg, 0);
+
+ // Biased locking
+ // See whether the lock is currently biased toward our thread and
+ // whether the epoch is still valid
+ // Note that the runtime guarantees sufficient alignment of JavaThread
+ // pointers to allow age to be placed into low bits
+ // First check to see whether biasing is even enabled for this object
+ Label cas_label;
+ int null_check_offset = -1;
+ if (!swap_reg_contains_mark) {
+ null_check_offset = offset();
+ movl(swap_reg, mark_addr);
+ }
+ if (need_tmp_reg) {
+ push(tmp_reg);
+ }
+ movl(tmp_reg, swap_reg);
+ andl(tmp_reg, markOopDesc::biased_lock_mask_in_place);
+ cmpl(tmp_reg, markOopDesc::biased_lock_pattern);
+ if (need_tmp_reg) {
+ pop(tmp_reg);
+ }
+ jcc(Assembler::notEqual, cas_label);
+ // The bias pattern is present in the object's header. Need to check
+ // whether the bias owner and the epoch are both still current.
+ // Note that because there is no current thread register on x86 we
+ // need to store off the mark word we read out of the object to
+ // avoid reloading it and needing to recheck invariants below. This
+ // store is unfortunate but it makes the overall code shorter and
+ // simpler.
+ movl(saved_mark_addr, swap_reg);
+ if (need_tmp_reg) {
+ push(tmp_reg);
+ }
+ get_thread(tmp_reg);
+ xorl(swap_reg, tmp_reg);
+ if (swap_reg_contains_mark) {
+ null_check_offset = offset();
+ }
+ movl(tmp_reg, klass_addr);
+ xorl(swap_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
+ andl(swap_reg, ~((int) markOopDesc::age_mask_in_place));
+ if (need_tmp_reg) {
+ pop(tmp_reg);
+ }
+ if (counters != NULL) {
+ cond_inc32(Assembler::zero,
+ ExternalAddress((address)counters->biased_lock_entry_count_addr()));
+ }
+ jcc(Assembler::equal, done);
+
+ Label try_revoke_bias;
+ Label try_rebias;
+
+ // At this point we know that the header has the bias pattern and
+ // that we are not the bias owner in the current epoch. We need to
+ // figure out more details about the state of the header in order to
+ // know what operations can be legally performed on the object's
+ // header.
+
+ // If the low three bits in the xor result aren't clear, that means
+ // the prototype header is no longer biased and we have to revoke
+ // the bias on this object.
+ testl(swap_reg, markOopDesc::biased_lock_mask_in_place);
+ jcc(Assembler::notZero, try_revoke_bias);
+
+ // Biasing is still enabled for this data type. See whether the
+ // epoch of the current bias is still valid, meaning that the epoch
+ // bits of the mark word are equal to the epoch bits of the
+ // prototype header. (Note that the prototype header's epoch bits
+ // only change at a safepoint.) If not, attempt to rebias the object
+ // toward the current thread. Note that we must be absolutely sure
+ // that the current epoch is invalid in order to do this because
+ // otherwise the manipulations it performs on the mark word are
+ // illegal.
+ testl(swap_reg, markOopDesc::epoch_mask_in_place);
+ jcc(Assembler::notZero, try_rebias);
+
+ // The epoch of the current bias is still valid but we know nothing
+ // about the owner; it might be set or it might be clear. Try to
+ // acquire the bias of the object using an atomic operation. If this
+ // fails we will go in to the runtime to revoke the object's bias.
+ // Note that we first construct the presumed unbiased header so we
+ // don't accidentally blow away another thread's valid bias.
+ movl(swap_reg, saved_mark_addr);
+ andl(swap_reg,
+ markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
+ if (need_tmp_reg) {
+ push(tmp_reg);
+ }
+ get_thread(tmp_reg);
+ orl(tmp_reg, swap_reg);
+ if (os::is_MP()) {
+ lock();
+ }
+ cmpxchgptr(tmp_reg, Address(obj_reg, 0));
+ if (need_tmp_reg) {
+ pop(tmp_reg);
+ }
+ // If the biasing toward our thread failed, this means that
+ // another thread succeeded in biasing it toward itself and we
+ // need to revoke that bias. The revocation will occur in the
+ // interpreter runtime in the slow case.
+ if (counters != NULL) {
+ cond_inc32(Assembler::zero,
+ ExternalAddress((address)counters->anonymously_biased_lock_entry_count_addr()));
+ }
+ if (slow_case != NULL) {
+ jcc(Assembler::notZero, *slow_case);
+ }
+ jmp(done);
+
+ bind(try_rebias);
+ // At this point we know the epoch has expired, meaning that the
+ // current "bias owner", if any, is actually invalid. Under these
+ // circumstances _only_, we are allowed to use the current header's
+ // value as the comparison value when doing the cas to acquire the
+ // bias in the current epoch. In other words, we allow transfer of
+ // the bias from one thread to another directly in this situation.
+ //
+ // FIXME: due to a lack of registers we currently blow away the age
+ // bits in this situation. Should attempt to preserve them.
+ if (need_tmp_reg) {
+ push(tmp_reg);
+ }
+ get_thread(tmp_reg);
+ movl(swap_reg, klass_addr);
+ orl(tmp_reg, Address(swap_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
+ movl(swap_reg, saved_mark_addr);
+ if (os::is_MP()) {
+ lock();
+ }
+ cmpxchgptr(tmp_reg, Address(obj_reg, 0));
+ if (need_tmp_reg) {
+ pop(tmp_reg);
+ }
+ // If the biasing toward our thread failed, then another thread
+ // succeeded in biasing it toward itself and we need to revoke that
+ // bias. The revocation will occur in the runtime in the slow case.
+ if (counters != NULL) {
+ cond_inc32(Assembler::zero,
+ ExternalAddress((address)counters->rebiased_lock_entry_count_addr()));
+ }
+ if (slow_case != NULL) {
+ jcc(Assembler::notZero, *slow_case);
+ }
+ jmp(done);
+
+ bind(try_revoke_bias);
+ // The prototype mark in the klass doesn't have the bias bit set any
+ // more, indicating that objects of this data type are not supposed
+ // to be biased any more. We are going to try to reset the mark of
+ // this object to the prototype value and fall through to the
+ // CAS-based locking scheme. Note that if our CAS fails, it means
+ // that another thread raced us for the privilege of revoking the
+ // bias of this particular object, so it's okay to continue in the
+ // normal locking code.
+ //
+ // FIXME: due to a lack of registers we currently blow away the age
+ // bits in this situation. Should attempt to preserve them.
+ movl(swap_reg, saved_mark_addr);
+ if (need_tmp_reg) {
+ push(tmp_reg);
+ }
+ movl(tmp_reg, klass_addr);
+ movl(tmp_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
+ if (os::is_MP()) {
+ lock();
+ }
+ cmpxchgptr(tmp_reg, Address(obj_reg, 0));
+ if (need_tmp_reg) {
+ pop(tmp_reg);
+ }
+ // Fall through to the normal CAS-based lock, because no matter what
+ // the result of the above CAS, some thread must have succeeded in
+ // removing the bias bit from the object's header.
+ if (counters != NULL) {
+ cond_inc32(Assembler::zero,
+ ExternalAddress((address)counters->revoked_lock_entry_count_addr()));
+ }
+
+ bind(cas_label);
+
+ return null_check_offset;
+}
+void MacroAssembler::call_VM_leaf_base(address entry_point,
+ int number_of_arguments) {
+ call(RuntimeAddress(entry_point));
+ increment(rsp, number_of_arguments * wordSize);
+}
+
+void MacroAssembler::cmpoop(Address src1, jobject obj) {
+ cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
+}
+
+void MacroAssembler::cmpoop(Register src1, jobject obj) {
+ cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
+}
+
+void MacroAssembler::extend_sign(Register hi, Register lo) {
+ // According to Intel Doc. AP-526, "Integer Divide", p.18.
+ if (VM_Version::is_P6() && hi == rdx && lo == rax) {
+ cdql();
+ } else {
+ movl(hi, lo);
+ sarl(hi, 31);
+ }
+}
+
+void MacroAssembler::fat_nop() {
+ // A 5 byte nop that is safe for patching (see patch_verified_entry)
+ emit_byte(0x26); // es:
+ emit_byte(0x2e); // cs:
+ emit_byte(0x64); // fs:
+ emit_byte(0x65); // gs:
+ emit_byte(0x90);
+}
+
+void MacroAssembler::jC2(Register tmp, Label& L) {
+ // set parity bit if FPU flag C2 is set (via rax)
+ save_rax(tmp);
+ fwait(); fnstsw_ax();
+ sahf();
+ restore_rax(tmp);
+ // branch
+ jcc(Assembler::parity, L);
+}
+
+void MacroAssembler::jnC2(Register tmp, Label& L) {
+ // set parity bit if FPU flag C2 is set (via rax)
+ save_rax(tmp);
+ fwait(); fnstsw_ax();
+ sahf();
+ restore_rax(tmp);
+ // branch
+ jcc(Assembler::noParity, L);
+}
+
// 32bit can do a case table jump in one instruction but we no longer allow the base
// to be installed in the Address class
void MacroAssembler::jump(ArrayAddress entry) {
-#ifdef _LP64
- lea(rscratch1, entry.base());
- Address dispatch = entry.index();
- assert(dispatch._base == noreg, "must be");
- dispatch._base = rscratch1;
- jmp(dispatch);
-#else
jmp(as_Address(entry));
-#endif // _LP64
}
-void MacroAssembler::jump(AddressLiteral dst) {
- if (reachable(dst)) {
- jmp_literal(dst.target(), dst.rspec());
- } else {
- lea(rscratch1, dst);
- jmp(rscratch1);
- }
-}
+// Note: y_lo will be destroyed
+void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
+ // Long compare for Java (semantics as described in JVM spec.)
+ Label high, low, done;
-void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
- if (reachable(dst)) {
- InstructionMark im(this);
- relocate(dst.reloc());
- const int short_size = 2;
- const int long_size = 6;
- int offs = (intptr_t)dst.target() - ((intptr_t)_code_pos);
- if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
- // 0111 tttn #8-bit disp
- emit_byte(0x70 | cc);
- emit_byte((offs - short_size) & 0xFF);
- } else {
- // 0000 1111 1000 tttn #32-bit disp
- emit_byte(0x0F);
- emit_byte(0x80 | cc);
- emit_long(offs - long_size);
- }
- } else {
-#ifdef ASSERT
- warning("reversing conditional branch");
-#endif /* ASSERT */
- Label skip;
- jccb(reverse[cc], skip);
- lea(rscratch1, dst);
- Assembler::jmp(rscratch1);
- bind(skip);
- }
-}
+ cmpl(x_hi, y_hi);
+ jcc(Assembler::less, low);
+ jcc(Assembler::greater, high);
+ // x_hi is the return register
+ xorl(x_hi, x_hi);
+ cmpl(x_lo, y_lo);
+ jcc(Assembler::below, low);
+ jcc(Assembler::equal, done);
-// Wouldn't need if AddressLiteral version had new name
-void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
- Assembler::call(L, rtype);
-}
+ bind(high);
+ xorl(x_hi, x_hi);
+ increment(x_hi);
+ jmp(done);
-// Wouldn't need if AddressLiteral version had new name
-void MacroAssembler::call(Register entry) {
- Assembler::call(entry);
-}
+ bind(low);
+ xorl(x_hi, x_hi);
+ decrementl(x_hi);
-void MacroAssembler::call(AddressLiteral entry) {
- if (reachable(entry)) {
- Assembler::call_literal(entry.target(), entry.rspec());
- } else {
- lea(rscratch1, entry);
- Assembler::call(rscratch1);
- }
-}
-
-void MacroAssembler::cmp8(AddressLiteral src1, int8_t src2) {
- if (reachable(src1)) {
- cmpb(as_Address(src1), src2);
- } else {
- lea(rscratch1, src1);
- cmpb(Address(rscratch1, 0), src2);
- }
-}
-
-void MacroAssembler::cmp32(AddressLiteral src1, int32_t src2) {
- if (reachable(src1)) {
- cmpl(as_Address(src1), src2);
- } else {
- lea(rscratch1, src1);
- cmpl(Address(rscratch1, 0), src2);
- }
-}
-
-void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
- if (reachable(src2)) {
- cmpl(src1, as_Address(src2));
- } else {
- lea(rscratch1, src2);
- cmpl(src1, Address(rscratch1, 0));
- }
-}
-
-void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
-#ifdef _LP64
- if (src2.is_lval()) {
- movptr(rscratch1, src2);
- Assembler::cmpq(src1, rscratch1);
- } else if (reachable(src2)) {
- cmpq(src1, as_Address(src2));
- } else {
- lea(rscratch1, src2);
- Assembler::cmpq(src1, Address(rscratch1, 0));
- }
-#else
- if (src2.is_lval()) {
- cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
- } else {
- cmpl(src1, as_Address(src2));
- }
-#endif // _LP64
-}
-
-void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
- assert(src2.is_lval(), "not a mem-mem compare");
-#ifdef _LP64
- // moves src2's literal address
- movptr(rscratch1, src2);
- Assembler::cmpq(src1, rscratch1);
-#else
- cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
-#endif // _LP64
-}
-
-void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
- assert(!src2.is_lval(), "should use cmpptr");
-
- if (reachable(src2)) {
-#ifdef _LP64
- cmpq(src1, as_Address(src2));
-#else
- ShouldNotReachHere();
-#endif // _LP64
- } else {
- lea(rscratch1, src2);
- Assembler::cmpq(src1, Address(rscratch1, 0));
- }
-}
-
-void MacroAssembler::cmpxchgptr(Register reg, AddressLiteral adr) {
- if (reachable(adr)) {
-#ifdef _LP64
- cmpxchgq(reg, as_Address(adr));
-#else
- cmpxchgl(reg, as_Address(adr));
-#endif // _LP64
- } else {
- lea(rscratch1, adr);
- cmpxchgq(reg, Address(rscratch1, 0));
- }
-}
-
-void MacroAssembler::incrementl(AddressLiteral dst) {
- if (reachable(dst)) {
- incrementl(as_Address(dst));
- } else {
- lea(rscratch1, dst);
- incrementl(Address(rscratch1, 0));
- }
-}
-
-void MacroAssembler::incrementl(ArrayAddress dst) {
- incrementl(as_Address(dst));
-}
-
-void MacroAssembler::lea(Register dst, Address src) {
-#ifdef _LP64
- leaq(dst, src);
-#else
- leal(dst, src);
-#endif // _LP64
+ bind(done);
}
void MacroAssembler::lea(Register dst, AddressLiteral src) {
-#ifdef _LP64
- mov_literal64(dst, (intptr_t)src.target(), src.rspec());
-#else
- mov_literal32(dst, (intptr_t)src.target(), src.rspec());
-#endif // _LP64
+ mov_literal32(dst, (int32_t)src.target(), src.rspec());
}
-void MacroAssembler::mov32(AddressLiteral dst, Register src) {
- if (reachable(dst)) {
- movl(as_Address(dst), src);
- } else {
- lea(rscratch1, dst);
- movl(Address(rscratch1, 0), src);
- }
-}
-
-void MacroAssembler::mov32(Register dst, AddressLiteral src) {
- if (reachable(src)) {
- movl(dst, as_Address(src));
- } else {
- lea(rscratch1, src);
- movl(dst, Address(rscratch1, 0));
- }
-}
-
-void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
- if (reachable(src)) {
- if (UseXmmLoadAndClearUpper) {
- movsd (dst, as_Address(src));
- } else {
- movlpd(dst, as_Address(src));
- }
- } else {
- lea(rscratch1, src);
- if (UseXmmLoadAndClearUpper) {
- movsd (dst, Address(rscratch1, 0));
- } else {
- movlpd(dst, Address(rscratch1, 0));
- }
- }
-}
-
-void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
- if (reachable(src)) {
- movss(dst, as_Address(src));
- } else {
- lea(rscratch1, src);
- movss(dst, Address(rscratch1, 0));
- }
-}
-
-void MacroAssembler::movoop(Register dst, jobject obj) {
- mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
-}
-
-void MacroAssembler::movoop(Address dst, jobject obj) {
- mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
- movq(dst, rscratch1);
-}
-
-void MacroAssembler::movptr(Register dst, AddressLiteral src) {
-#ifdef _LP64
- if (src.is_lval()) {
- mov_literal64(dst, (intptr_t)src.target(), src.rspec());
- } else {
- if (reachable(src)) {
- movq(dst, as_Address(src));
- } else {
- lea(rscratch1, src);
- movq(dst, Address(rscratch1,0));
- }
- }
-#else
- if (src.is_lval()) {
- mov_literal32(dst, (intptr_t)src.target(), src.rspec());
- } else {
- movl(dst, as_Address(src));
- }
-#endif // LP64
-}
-
-void MacroAssembler::movptr(ArrayAddress dst, Register src) {
-#ifdef _LP64
- movq(as_Address(dst), src);
-#else
- movl(as_Address(dst), src);
-#endif // _LP64
-}
-
-void MacroAssembler::pushoop(jobject obj) {
-#ifdef _LP64
- movoop(rscratch1, obj);
- pushq(rscratch1);
-#else
- push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
-#endif // _LP64
-}
-
-void MacroAssembler::pushptr(AddressLiteral src) {
-#ifdef _LP64
- lea(rscratch1, src);
- if (src.is_lval()) {
- pushq(rscratch1);
- } else {
- pushq(Address(rscratch1, 0));
- }
-#else
- if (src.is_lval()) {
- push_literal((int32_t)src.target(), src.rspec());
- else {
- pushl(as_Address(src));
- }
-#endif // _LP64
-}
-
-void MacroAssembler::ldmxcsr(AddressLiteral src) {
- if (reachable(src)) {
- Assembler::ldmxcsr(as_Address(src));
- } else {
- lea(rscratch1, src);
- Assembler::ldmxcsr(Address(rscratch1, 0));
- }
-}
-
-void MacroAssembler::movlpd(XMMRegister dst, AddressLiteral src) {
- if (reachable(src)) {
- movlpd(dst, as_Address(src));
- } else {
- lea(rscratch1, src);
- movlpd(dst, Address(rscratch1, 0));
- }
-}
-
-void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
- if (reachable(src)) {
- movss(dst, as_Address(src));
- } else {
- lea(rscratch1, src);
- movss(dst, Address(rscratch1, 0));
- }
-}
-void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
- if (reachable(src)) {
- xorpd(dst, as_Address(src));
- } else {
- lea(rscratch1, src);
- xorpd(dst, Address(rscratch1, 0));
- }
-}
-
-void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
- if (reachable(src)) {
- xorps(dst, as_Address(src));
- } else {
- lea(rscratch1, src);
- xorps(dst, Address(rscratch1, 0));
- }
-}
-
-void MacroAssembler::null_check(Register reg, int offset) {
- if (needs_explicit_null_check(offset)) {
- // provoke OS NULL exception if reg = NULL by
- // accessing M[reg] w/o changing any (non-CC) registers
- cmpq(rax, Address(reg, 0));
- // Note: should probably use testl(rax, Address(reg, 0));
- // may be shorter code (however, this version of
- // testl needs to be implemented first)
- } else {
- // nothing to do, (later) access of M[reg + offset]
- // will provoke OS NULL exception if reg = NULL
- }
-}
-
-int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
- int off = offset();
- movzbl(dst, src);
- return off;
-}
-
-int MacroAssembler::load_unsigned_word(Register dst, Address src) {
- int off = offset();
- movzwl(dst, src);
- return off;
-}
-
-int MacroAssembler::load_signed_byte(Register dst, Address src) {
- int off = offset();
- movsbl(dst, src);
- return off;
-}
-
-int MacroAssembler::load_signed_word(Register dst, Address src) {
- int off = offset();
- movswl(dst, src);
- return off;
-}
-
-void MacroAssembler::incrementl(Register reg, int value) {
- if (value == min_jint) { addl(reg, value); return; }
- if (value < 0) { decrementl(reg, -value); return; }
- if (value == 0) { ; return; }
- if (value == 1 && UseIncDec) { incl(reg) ; return; }
- /* else */ { addl(reg, value) ; return; }
-}
-
-void MacroAssembler::decrementl(Register reg, int value) {
- if (value == min_jint) { subl(reg, value); return; }
- if (value < 0) { incrementl(reg, -value); return; }
- if (value == 0) { ; return; }
- if (value == 1 && UseIncDec) { decl(reg) ; return; }
- /* else */ { subl(reg, value) ; return; }
-}
-
-void MacroAssembler::incrementq(Register reg, int value) {
- if (value == min_jint) { addq(reg, value); return; }
- if (value < 0) { decrementq(reg, -value); return; }
- if (value == 0) { ; return; }
- if (value == 1 && UseIncDec) { incq(reg) ; return; }
- /* else */ { addq(reg, value) ; return; }
-}
-
-void MacroAssembler::decrementq(Register reg, int value) {
- if (value == min_jint) { subq(reg, value); return; }
- if (value < 0) { incrementq(reg, -value); return; }
- if (value == 0) { ; return; }
- if (value == 1 && UseIncDec) { decq(reg) ; return; }
- /* else */ { subq(reg, value) ; return; }
-}
-
-void MacroAssembler::incrementl(Address dst, int value) {
- if (value == min_jint) { addl(dst, value); return; }
- if (value < 0) { decrementl(dst, -value); return; }
- if (value == 0) { ; return; }
- if (value == 1 && UseIncDec) { incl(dst) ; return; }
- /* else */ { addl(dst, value) ; return; }
-}
-
-void MacroAssembler::decrementl(Address dst, int value) {
- if (value == min_jint) { subl(dst, value); return; }
- if (value < 0) { incrementl(dst, -value); return; }
- if (value == 0) { ; return; }
- if (value == 1 && UseIncDec) { decl(dst) ; return; }
- /* else */ { subl(dst, value) ; return; }
-}
-
-void MacroAssembler::incrementq(Address dst, int value) {
- if (value == min_jint) { addq(dst, value); return; }
- if (value < 0) { decrementq(dst, -value); return; }
- if (value == 0) { ; return; }
- if (value == 1 && UseIncDec) { incq(dst) ; return; }
- /* else */ { addq(dst, value) ; return; }
-}
-
-void MacroAssembler::decrementq(Address dst, int value) {
- if (value == min_jint) { subq(dst, value); return; }
- if (value < 0) { incrementq(dst, -value); return; }
- if (value == 0) { ; return; }
- if (value == 1 && UseIncDec) { decq(dst) ; return; }
- /* else */ { subq(dst, value) ; return; }
-}
-
-void MacroAssembler::align(int modulus) {
- if (offset() % modulus != 0) {
- nop(modulus - (offset() % modulus));
- }
-}
-
-void MacroAssembler::enter() {
- pushq(rbp);
- movq(rbp, rsp);
+void MacroAssembler::lea(Address dst, AddressLiteral adr) {
+ // leal(dst, as_Address(adr));
+ // see note in movl as to why we must use a move
+ mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
}
void MacroAssembler::leave() {
- emit_byte(0xC9); // LEAVE
+ mov(rsp, rbp);
+ pop(rbp);
}
-// C++ bool manipulation
-
-void MacroAssembler::movbool(Register dst, Address src) {
- if(sizeof(bool) == 1)
- movb(dst, src);
- else if(sizeof(bool) == 2)
- movw(dst, src);
- else if(sizeof(bool) == 4)
- movl(dst, src);
- else {
- // unsupported
- ShouldNotReachHere();
- }
+void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
+ // Multiplication of two Java long values stored on the stack
+ // as illustrated below. Result is in rdx:rax.
+ //
+ // rsp ---> [ ?? ] \ \
+ // .... | y_rsp_offset |
+ // [ y_lo ] / (in bytes) | x_rsp_offset
+ // [ y_hi ] | (in bytes)
+ // .... |
+ // [ x_lo ] /
+ // [ x_hi ]
+ // ....
+ //
+ // Basic idea: lo(result) = lo(x_lo * y_lo)
+ // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
+ Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
+ Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
+ Label quick;
+ // load x_hi, y_hi and check if quick
+ // multiplication is possible
+ movl(rbx, x_hi);
+ movl(rcx, y_hi);
+ movl(rax, rbx);
+ orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
+ jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
+ // do full multiplication
+ // 1st step
+ mull(y_lo); // x_hi * y_lo
+ movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
+ // 2nd step
+ movl(rax, x_lo);
+ mull(rcx); // x_lo * y_hi
+ addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
+ // 3rd step
+ bind(quick); // note: rbx, = 0 if quick multiply!
+ movl(rax, x_lo);
+ mull(y_lo); // x_lo * y_lo
+ addl(rdx, rbx); // correct hi(x_lo * y_lo)
}
-void MacroAssembler::movbool(Address dst, bool boolconst) {
- if(sizeof(bool) == 1)
- movb(dst, (int) boolconst);
- else if(sizeof(bool) == 2)
- movw(dst, (int) boolconst);
- else if(sizeof(bool) == 4)
- movl(dst, (int) boolconst);
- else {
- // unsupported
- ShouldNotReachHere();
- }
+void MacroAssembler::lneg(Register hi, Register lo) {
+ negl(lo);
+ adcl(hi, 0);
+ negl(hi);
}
-void MacroAssembler::movbool(Address dst, Register src) {
- if(sizeof(bool) == 1)
- movb(dst, src);
- else if(sizeof(bool) == 2)
- movw(dst, src);
- else if(sizeof(bool) == 4)
- movl(dst, src);
- else {
- // unsupported
- ShouldNotReachHere();
- }
-}
-
-void MacroAssembler::testbool(Register dst) {
- if(sizeof(bool) == 1)
- testb(dst, (int) 0xff);
- else if(sizeof(bool) == 2) {
- // need testw impl
- ShouldNotReachHere();
- } else if(sizeof(bool) == 4)
- testl(dst, dst);
- else {
- // unsupported
- ShouldNotReachHere();
- }
-}
-
-void MacroAssembler::set_last_Java_frame(Register last_java_sp,
- Register last_java_fp,
- address last_java_pc) {
- // determine last_java_sp register
- if (!last_java_sp->is_valid()) {
- last_java_sp = rsp;
- }
-
- // last_java_fp is optional
- if (last_java_fp->is_valid()) {
- movq(Address(r15_thread, JavaThread::last_Java_fp_offset()),
- last_java_fp);
- }
-
- // last_java_pc is optional
- if (last_java_pc != NULL) {
- Address java_pc(r15_thread,
- JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
- lea(rscratch1, InternalAddress(last_java_pc));
- movq(java_pc, rscratch1);
- }
-
- movq(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
-}
-
-void MacroAssembler::reset_last_Java_frame(bool clear_fp,
- bool clear_pc) {
- // we must set sp to zero to clear frame
- movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
- // must clear fp, so that compiled frames are not confused; it is
- // possible that we need it only for debugging
- if (clear_fp) {
- movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
- }
-
- if (clear_pc) {
- movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
- }
+void MacroAssembler::lshl(Register hi, Register lo) {
+ // Java shift left long support (semantics as described in JVM spec., p.305)
+ // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
+ // shift value is in rcx !
+ assert(hi != rcx, "must not use rcx");
+ assert(lo != rcx, "must not use rcx");
+ const Register s = rcx; // shift count
+ const int n = BitsPerWord;
+ Label L;
+ andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
+ cmpl(s, n); // if (s < n)
+ jcc(Assembler::less, L); // else (s >= n)
+ movl(hi, lo); // x := x << n
+ xorl(lo, lo);
+ // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
+ bind(L); // s (mod n) < n
+ shldl(hi, lo); // x := x << s
+ shll(lo);
}
-// Implementation of call_VM versions
-
-void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
- Label L, E;
-
-#ifdef _WIN64
- // Windows always allocates space for it's register args
- assert(num_args <= 4, "only register arguments supported");
- subq(rsp, frame::arg_reg_save_area_bytes);
-#endif
-
- // Align stack if necessary
- testl(rsp, 15);
- jcc(Assembler::zero, L);
-
- subq(rsp, 8);
- {
- call(RuntimeAddress(entry_point));
- }
- addq(rsp, 8);
- jmp(E);
-
- bind(L);
- {
- call(RuntimeAddress(entry_point));
- }
-
- bind(E);
-
-#ifdef _WIN64
- // restore stack pointer
- addq(rsp, frame::arg_reg_save_area_bytes);
-#endif
-
+void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
+ // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
+ // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
+ assert(hi != rcx, "must not use rcx");
+ assert(lo != rcx, "must not use rcx");
+ const Register s = rcx; // shift count
+ const int n = BitsPerWord;
+ Label L;
+ andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
+ cmpl(s, n); // if (s < n)
+ jcc(Assembler::less, L); // else (s >= n)
+ movl(lo, hi); // x := x >> n
+ if (sign_extension) sarl(hi, 31);
+ else xorl(hi, hi);
+ // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
+ bind(L); // s (mod n) < n
+ shrdl(lo, hi); // x := x >> s
+ if (sign_extension) sarl(hi);
+ else shrl(hi);
}
-
-void MacroAssembler::call_VM_base(Register oop_result,
- Register java_thread,
- Register last_java_sp,
- address entry_point,
- int num_args,
- bool check_exceptions) {
- // determine last_java_sp register
- if (!last_java_sp->is_valid()) {
- last_java_sp = rsp;
- }
-
- // debugging support
- assert(num_args >= 0, "cannot have negative number of arguments");
- assert(r15_thread != oop_result,
- "cannot use the same register for java_thread & oop_result");
- assert(r15_thread != last_java_sp,
- "cannot use the same register for java_thread & last_java_sp");
-
- // set last Java frame before call
-
- // This sets last_Java_fp which is only needed from interpreted frames
- // and should really be done only from the interp_masm version before
- // calling the underlying call_VM. That doesn't happen yet so we set
- // last_Java_fp here even though some callers don't need it and
- // also clear it below.
- set_last_Java_frame(last_java_sp, rbp, NULL);
-
- {
- Label L, E;
-
- // Align stack if necessary
-#ifdef _WIN64
- assert(num_args <= 4, "only register arguments supported");
- // Windows always allocates space for it's register args
- subq(rsp, frame::arg_reg_save_area_bytes);
-#endif
- testl(rsp, 15);
- jcc(Assembler::zero, L);
-
- subq(rsp, 8);
- {
- call(RuntimeAddress(entry_point));
- }
- addq(rsp, 8);
- jmp(E);
-
-
- bind(L);
- {
- call(RuntimeAddress(entry_point));
- }
-
- bind(E);
-
-#ifdef _WIN64
- // restore stack pointer
- addq(rsp, frame::arg_reg_save_area_bytes);
-#endif
- }
-
-#ifdef ASSERT
- pushq(rax);
- {
- Label L;
- get_thread(rax);
- cmpq(r15_thread, rax);
- jcc(Assembler::equal, L);
- stop("MacroAssembler::call_VM_base: register not callee saved?");
- bind(L);
- }
- popq(rax);
-#endif
-
- // reset last Java frame
- // This really shouldn't have to clear fp set note above at the
- // call to set_last_Java_frame
- reset_last_Java_frame(true, false);
-
- check_and_handle_popframe(noreg);
- check_and_handle_earlyret(noreg);
-
- if (check_exceptions) {
- cmpq(Address(r15_thread, Thread::pending_exception_offset()), (int) NULL);
- // This used to conditionally jump to forward_exception however it is
- // possible if we relocate that the branch will not reach. So we must jump
- // around so we can always reach
- Label ok;
- jcc(Assembler::equal, ok);
- jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
- bind(ok);
- }
-
- // get oop result if there is one and reset the value in the thread
- if (oop_result->is_valid()) {
- movq(oop_result, Address(r15_thread, JavaThread::vm_result_offset()));
- movptr(Address(r15_thread, JavaThread::vm_result_offset()), NULL_WORD);
- verify_oop(oop_result, "broken oop in call_VM_base");
- }
+void MacroAssembler::movoop(Register dst, jobject obj) {
+ mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
}
-void MacroAssembler::check_and_handle_popframe(Register java_thread) {}
-void MacroAssembler::check_and_handle_earlyret(Register java_thread) {}
-
-void MacroAssembler::call_VM_helper(Register oop_result,
- address entry_point,
- int num_args,
- bool check_exceptions) {
- // Java thread becomes first argument of C function
- movq(c_rarg0, r15_thread);
-
- // We've pushed one address, correct last_Java_sp
- leaq(rax, Address(rsp, wordSize));
-
- call_VM_base(oop_result, noreg, rax, entry_point, num_args,
- check_exceptions);
+void MacroAssembler::movoop(Address dst, jobject obj) {
+ mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
}
-
-void MacroAssembler::call_VM(Register oop_result,
- address entry_point,
- bool check_exceptions) {
- Label C, E;
- Assembler::call(C, relocInfo::none);
- jmp(E);
-
- bind(C);
- call_VM_helper(oop_result, entry_point, 0, check_exceptions);
- ret(0);
-
- bind(E);
-}
-
-
-void MacroAssembler::call_VM(Register oop_result,
- address entry_point,
- Register arg_1,
- bool check_exceptions) {
- assert(rax != arg_1, "smashed argument");
- assert(c_rarg0 != arg_1, "smashed argument");
-
- Label C, E;
- Assembler::call(C, relocInfo::none);
- jmp(E);
-
- bind(C);
- // c_rarg0 is reserved for thread
- if (c_rarg1 != arg_1) {
- movq(c_rarg1, arg_1);
- }
- call_VM_helper(oop_result, entry_point, 1, check_exceptions);
- ret(0);
-
- bind(E);
-}
-
-void MacroAssembler::call_VM(Register oop_result,
- address entry_point,
- Register arg_1,
- Register arg_2,
- bool check_exceptions) {
- assert(rax != arg_1, "smashed argument");
- assert(rax != arg_2, "smashed argument");
- assert(c_rarg0 != arg_1, "smashed argument");
- assert(c_rarg0 != arg_2, "smashed argument");
- assert(c_rarg1 != arg_2, "smashed argument");
- assert(c_rarg2 != arg_1, "smashed argument");
-
- Label C, E;
- Assembler::call(C, relocInfo::none);
- jmp(E);
-
- bind(C);
- // c_rarg0 is reserved for thread
- if (c_rarg1 != arg_1) {
- movq(c_rarg1, arg_1);
- }
- if (c_rarg2 != arg_2) {
- movq(c_rarg2, arg_2);
- }
- call_VM_helper(oop_result, entry_point, 2, check_exceptions);
- ret(0);
-
- bind(E);
-}
-
-
-void MacroAssembler::call_VM(Register oop_result,
- address entry_point,
- Register arg_1,
- Register arg_2,
- Register arg_3,
- bool check_exceptions) {
- assert(rax != arg_1, "smashed argument");
- assert(rax != arg_2, "smashed argument");
- assert(rax != arg_3, "smashed argument");
- assert(c_rarg0 != arg_1, "smashed argument");
- assert(c_rarg0 != arg_2, "smashed argument");
- assert(c_rarg0 != arg_3, "smashed argument");
- assert(c_rarg1 != arg_2, "smashed argument");
- assert(c_rarg1 != arg_3, "smashed argument");
- assert(c_rarg2 != arg_1, "smashed argument");
- assert(c_rarg2 != arg_3, "smashed argument");
- assert(c_rarg3 != arg_1, "smashed argument");
- assert(c_rarg3 != arg_2, "smashed argument");
-
- Label C, E;
- Assembler::call(C, relocInfo::none);
- jmp(E);
-
- bind(C);
- // c_rarg0 is reserved for thread
- if (c_rarg1 != arg_1) {
- movq(c_rarg1, arg_1);
- }
- if (c_rarg2 != arg_2) {
- movq(c_rarg2, arg_2);
- }
- if (c_rarg3 != arg_3) {
- movq(c_rarg3, arg_3);
- }
- call_VM_helper(oop_result, entry_point, 3, check_exceptions);
- ret(0);
-
- bind(E);
-}
-
-void MacroAssembler::call_VM(Register oop_result,
- Register last_java_sp,
- address entry_point,
- int num_args,
- bool check_exceptions) {
- call_VM_base(oop_result, noreg, last_java_sp, entry_point, num_args,
- check_exceptions);
-}
-
-void MacroAssembler::call_VM(Register oop_result,
- Register last_java_sp,
- address entry_point,
- Register arg_1,
- bool check_exceptions) {
- assert(c_rarg0 != arg_1, "smashed argument");
- assert(c_rarg1 != last_java_sp, "smashed argument");
- // c_rarg0 is reserved for thread
- if (c_rarg1 != arg_1) {
- movq(c_rarg1, arg_1);
- }
- call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
-}
-
-void MacroAssembler::call_VM(Register oop_result,
- Register last_java_sp,
- address entry_point,
- Register arg_1,
- Register arg_2,
- bool check_exceptions) {
- assert(c_rarg0 != arg_1, "smashed argument");
- assert(c_rarg0 != arg_2, "smashed argument");
- assert(c_rarg1 != arg_2, "smashed argument");
- assert(c_rarg1 != last_java_sp, "smashed argument");
- assert(c_rarg2 != arg_1, "smashed argument");
- assert(c_rarg2 != last_java_sp, "smashed argument");
- // c_rarg0 is reserved for thread
- if (c_rarg1 != arg_1) {
- movq(c_rarg1, arg_1);
- }
- if (c_rarg2 != arg_2) {
- movq(c_rarg2, arg_2);
- }
- call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
-}
-
-
-void MacroAssembler::call_VM(Register oop_result,
- Register last_java_sp,
- address entry_point,
- Register arg_1,
- Register arg_2,
- Register arg_3,
- bool check_exceptions) {
- assert(c_rarg0 != arg_1, "smashed argument");
- assert(c_rarg0 != arg_2, "smashed argument");
- assert(c_rarg0 != arg_3, "smashed argument");
- assert(c_rarg1 != arg_2, "smashed argument");
- assert(c_rarg1 != arg_3, "smashed argument");
- assert(c_rarg1 != last_java_sp, "smashed argument");
- assert(c_rarg2 != arg_1, "smashed argument");
- assert(c_rarg2 != arg_3, "smashed argument");
- assert(c_rarg2 != last_java_sp, "smashed argument");
- assert(c_rarg3 != arg_1, "smashed argument");
- assert(c_rarg3 != arg_2, "smashed argument");
- assert(c_rarg3 != last_java_sp, "smashed argument");
- // c_rarg0 is reserved for thread
- if (c_rarg1 != arg_1) {
- movq(c_rarg1, arg_1);
- }
- if (c_rarg2 != arg_2) {
- movq(c_rarg2, arg_2);
- }
- if (c_rarg3 != arg_3) {
- movq(c_rarg2, arg_3);
- }
- call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
-}
-
-void MacroAssembler::call_VM_leaf(address entry_point, int num_args) {
- call_VM_leaf_base(entry_point, num_args);
-}
-
-void MacroAssembler::call_VM_leaf(address entry_point, Register arg_1) {
- if (c_rarg0 != arg_1) {
- movq(c_rarg0, arg_1);
- }
- call_VM_leaf(entry_point, 1);
-}
-
-void MacroAssembler::call_VM_leaf(address entry_point,
- Register arg_1,
- Register arg_2) {
- assert(c_rarg0 != arg_2, "smashed argument");
- assert(c_rarg1 != arg_1, "smashed argument");
- if (c_rarg0 != arg_1) {
- movq(c_rarg0, arg_1);
- }
- if (c_rarg1 != arg_2) {
- movq(c_rarg1, arg_2);
- }
- call_VM_leaf(entry_point, 2);
-}
-
-void MacroAssembler::call_VM_leaf(address entry_point,
- Register arg_1,
- Register arg_2,
- Register arg_3) {
- assert(c_rarg0 != arg_2, "smashed argument");
- assert(c_rarg0 != arg_3, "smashed argument");
- assert(c_rarg1 != arg_1, "smashed argument");
- assert(c_rarg1 != arg_3, "smashed argument");
- assert(c_rarg2 != arg_1, "smashed argument");
- assert(c_rarg2 != arg_2, "smashed argument");
- if (c_rarg0 != arg_1) {
- movq(c_rarg0, arg_1);
- }
- if (c_rarg1 != arg_2) {
- movq(c_rarg1, arg_2);
- }
- if (c_rarg2 != arg_3) {
- movq(c_rarg2, arg_3);
- }
- call_VM_leaf(entry_point, 3);
-}
-
-
-// Calls to C land
-//
-// When entering C land, the rbp & rsp of the last Java frame have to
-// be recorded in the (thread-local) JavaThread object. When leaving C
-// land, the last Java fp has to be reset to 0. This is required to
-// allow proper stack traversal.
-void MacroAssembler::store_check(Register obj) {
- // Does a store check for the oop in register obj. The content of
- // register obj is destroyed afterwards.
- store_check_part_1(obj);
- store_check_part_2(obj);
-}
-
-void MacroAssembler::store_check(Register obj, Address dst) {
- store_check(obj);
-}
-
-// split the store check operation so that other instructions can be
-// scheduled inbetween
-void MacroAssembler::store_check_part_1(Register obj) {
- BarrierSet* bs = Universe::heap()->barrier_set();
- assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
- shrq(obj, CardTableModRefBS::card_shift);
-}
-
-void MacroAssembler::store_check_part_2(Register obj) {
- BarrierSet* bs = Universe::heap()->barrier_set();
- assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
- CardTableModRefBS* ct = (CardTableModRefBS*)bs;
- assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
-
- // The calculation for byte_map_base is as follows:
- // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift);
- // So this essentially converts an address to a displacement and
- // it will never need to be relocated. On 64bit however the value may be too
- // large for a 32bit displacement
-
- intptr_t disp = (intptr_t) ct->byte_map_base;
- if (is_simm32(disp)) {
- Address cardtable(noreg, obj, Address::times_1, disp);
- movb(cardtable, 0);
+void MacroAssembler::movptr(Register dst, AddressLiteral src) {
+ if (src.is_lval()) {
+ mov_literal32(dst, (intptr_t)src.target(), src.rspec());
} else {
- // By doing it as an ExternalAddress disp could be converted to a rip-relative
- // displacement and done in a single instruction given favorable mapping and
- // a smarter version of as_Address. Worst case it is two instructions which
- // is no worse off then loading disp into a register and doing as a simple
- // Address() as above.
- // We can't do as ExternalAddress as the only style since if disp == 0 we'll
- // assert since NULL isn't acceptable in a reloci (see 6644928). In any case
- // in some cases we'll get a single instruction version.
-
- ExternalAddress cardtable((address)disp);
- Address index(noreg, obj, Address::times_1);
- movb(as_Address(ArrayAddress(cardtable, index)), 0);
+ movl(dst, as_Address(src));
}
-
}
-void MacroAssembler::c2bool(Register x) {
- // implements x == 0 ? 0 : 1
- // note: must only look at least-significant byte of x
- // since C-style booleans are stored in one byte
- // only! (was bug)
- andl(x, 0xFF);
- setb(Assembler::notZero, x);
+void MacroAssembler::movptr(ArrayAddress dst, Register src) {
+ movl(as_Address(dst), src);
}
-int MacroAssembler::corrected_idivl(Register reg) {
- // Full implementation of Java idiv and irem; checks for special
- // case as described in JVM spec., p.243 & p.271. The function
- // returns the (pc) offset of the idivl instruction - may be needed
- // for implicit exceptions.
- //
- // normal case special case
- //
- // input : eax: dividend min_int
- // reg: divisor (may not be eax/edx) -1
- //
- // output: eax: quotient (= eax idiv reg) min_int
- // edx: remainder (= eax irem reg) 0
- assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
- const int min_int = 0x80000000;
- Label normal_case, special_case;
-
- // check for special case
- cmpl(rax, min_int);
- jcc(Assembler::notEqual, normal_case);
- xorl(rdx, rdx); // prepare edx for possible special case (where
- // remainder = 0)
- cmpl(reg, -1);
- jcc(Assembler::equal, special_case);
-
- // handle normal case
- bind(normal_case);
- cdql();
- int idivl_offset = offset();
- idivl(reg);
-
- // normal and special case exit
- bind(special_case);
-
- return idivl_offset;
+void MacroAssembler::movptr(Register dst, ArrayAddress src) {
+ movl(dst, as_Address(src));
}
-int MacroAssembler::corrected_idivq(Register reg) {
- // Full implementation of Java ldiv and lrem; checks for special
- // case as described in JVM spec., p.243 & p.271. The function
- // returns the (pc) offset of the idivl instruction - may be needed
- // for implicit exceptions.
- //
- // normal case special case
- //
- // input : rax: dividend min_long
- // reg: divisor (may not be eax/edx) -1
- //
- // output: rax: quotient (= rax idiv reg) min_long
- // rdx: remainder (= rax irem reg) 0
- assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
- static const int64_t min_long = 0x8000000000000000;
- Label normal_case, special_case;
-
- // check for special case
- cmp64(rax, ExternalAddress((address) &min_long));
- jcc(Assembler::notEqual, normal_case);
- xorl(rdx, rdx); // prepare rdx for possible special case (where
- // remainder = 0)
- cmpq(reg, -1);
- jcc(Assembler::equal, special_case);
-
- // handle normal case
- bind(normal_case);
- cdqq();
- int idivq_offset = offset();
- idivq(reg);
-
- // normal and special case exit
- bind(special_case);
-
- return idivq_offset;
+// src should NEVER be a real pointer. Use AddressLiteral for true pointers
+void MacroAssembler::movptr(Address dst, intptr_t src) {
+ movl(dst, src);
}
-void MacroAssembler::push_IU_state() {
- pushfq(); // Push flags first because pushaq kills them
- subq(rsp, 8); // Make sure rsp stays 16-byte aligned
- pushaq();
+
+void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
+ movsd(dst, as_Address(src));
}
-void MacroAssembler::pop_IU_state() {
- popaq();
- addq(rsp, 8);
- popfq();
+void MacroAssembler::pop_callee_saved_registers() {
+ pop(rcx);
+ pop(rdx);
+ pop(rdi);
+ pop(rsi);
}
-void MacroAssembler::push_FPU_state() {
- subq(rsp, FPUStateSizeInWords * wordSize);
- fxsave(Address(rsp, 0));
+void MacroAssembler::pop_fTOS() {
+ fld_d(Address(rsp, 0));
+ addl(rsp, 2 * wordSize);
}
-void MacroAssembler::pop_FPU_state() {
- fxrstor(Address(rsp, 0));
- addq(rsp, FPUStateSizeInWords * wordSize);
+void MacroAssembler::push_callee_saved_registers() {
+ push(rsi);
+ push(rdi);
+ push(rdx);
+ push(rcx);
}
-// Save Integer and Float state
-// Warning: Stack must be 16 byte aligned
-void MacroAssembler::push_CPU_state() {
- push_IU_state();
- push_FPU_state();
+void MacroAssembler::push_fTOS() {
+ subl(rsp, 2 * wordSize);
+ fstp_d(Address(rsp, 0));
}
-void MacroAssembler::pop_CPU_state() {
- pop_FPU_state();
- pop_IU_state();
+
+void MacroAssembler::pushoop(jobject obj) {
+ push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
}
-void MacroAssembler::sign_extend_short(Register reg) {
- movswl(reg, reg);
-}
-void MacroAssembler::sign_extend_byte(Register reg) {
- movsbl(reg, reg);
-}
-
-void MacroAssembler::division_with_shift(Register reg, int shift_value) {
- assert (shift_value > 0, "illegal shift value");
- Label _is_positive;
- testl (reg, reg);
- jcc (Assembler::positive, _is_positive);
- int offset = (1 << shift_value) - 1 ;
-
- if (offset == 1) {
- incrementl(reg);
+void MacroAssembler::pushptr(AddressLiteral src) {
+ if (src.is_lval()) {
+ push_literal32((int32_t)src.target(), src.rspec());
} else {
- addl(reg, offset);
+ pushl(as_Address(src));
}
-
- bind (_is_positive);
- sarl(reg, shift_value);
}
-void MacroAssembler::round_to_l(Register reg, int modulus) {
- addl(reg, modulus - 1);
- andl(reg, -modulus);
+void MacroAssembler::set_word_if_not_zero(Register dst) {
+ xorl(dst, dst);
+ set_byte_if_not_zero(dst);
}
-void MacroAssembler::round_to_q(Register reg, int modulus) {
- addq(reg, modulus - 1);
- andq(reg, -modulus);
+static void pass_arg0(MacroAssembler* masm, Register arg) {
+ masm->push(arg);
}
-void MacroAssembler::verify_oop(Register reg, const char* s) {
- if (!VerifyOops) {
- return;
- }
-
- // Pass register number to verify_oop_subroutine
- char* b = new char[strlen(s) + 50];
- sprintf(b, "verify_oop: %s: %s", reg->name(), s);
-
- pushq(rax); // save rax, restored by receiver
-
- // pass args on stack, only touch rax
- pushq(reg);
- // avoid using pushptr, as it modifies scratch registers
- // and our contract is not to modify anything
- ExternalAddress buffer((address)b);
- movptr(rax, buffer.addr());
- pushq(rax);
-
- // call indirectly to solve generation ordering problem
- movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
- call(rax); // no alignment requirement
- // everything popped by receiver
+static void pass_arg1(MacroAssembler* masm, Register arg) {
+ masm->push(arg);
}
-void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
- if (!VerifyOops) return;
- // Pass register number to verify_oop_subroutine
- char* b = new char[strlen(s) + 50];
- sprintf(b, "verify_oop_addr: %s", s);
- pushq(rax); // save rax
- movq(addr, rax);
- pushq(rax); // pass register argument
-
-
- // avoid using pushptr, as it modifies scratch registers
- // and our contract is not to modify anything
- ExternalAddress buffer((address)b);
- movptr(rax, buffer.addr());
- pushq(rax);
-
- // call indirectly to solve generation ordering problem
- movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
- call(rax); // no alignment requirement
- // everything popped by receiver
+static void pass_arg2(MacroAssembler* masm, Register arg) {
+ masm->push(arg);
}
-
-void MacroAssembler::stop(const char* msg) {
- address rip = pc();
- pushaq(); // get regs on stack
- lea(c_rarg0, ExternalAddress((address) msg));
- lea(c_rarg1, InternalAddress(rip));
- movq(c_rarg2, rsp); // pass pointer to regs array
- andq(rsp, -16); // align stack as required by ABI
- call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug)));
- hlt();
-}
-
-void MacroAssembler::warn(const char* msg) {
- pushq(r12);
- movq(r12, rsp);
- andq(rsp, -16); // align stack as required by push_CPU_state and call
-
- push_CPU_state(); // keeps alignment at 16 bytes
- lea(c_rarg0, ExternalAddress((address) msg));
- call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0);
- pop_CPU_state();
-
- movq(rsp, r12);
- popq(r12);
+static void pass_arg3(MacroAssembler* masm, Register arg) {
+ masm->push(arg);
}
#ifndef PRODUCT
extern "C" void findpc(intptr_t x);
#endif
-void MacroAssembler::debug(char* msg, int64_t pc, int64_t regs[]) {
+void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
// In order to get locks to work, we need to fake a in_VM state
- if (ShowMessageBoxOnError ) {
+ JavaThread* thread = JavaThread::current();
+ JavaThreadState saved_state = thread->thread_state();
+ thread->set_thread_state(_thread_in_vm);
+ if (ShowMessageBoxOnError) {
JavaThread* thread = JavaThread::current();
JavaThreadState saved_state = thread->thread_state();
thread->set_thread_state(_thread_in_vm);
-#ifndef PRODUCT
if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
ttyLocker ttyl;
BytecodeCounter::print();
}
-#endif
// To see where a verify_oop failed, get $ebx+40/X for this frame.
- // XXX correct this offset for amd64
// This is the value of eip which points to where verify_oop will return.
if (os::message_box(msg, "Execution stopped, print registers?")) {
ttyLocker ttyl;
- tty->print_cr("rip = 0x%016lx", pc);
+ tty->print_cr("eip = 0x%08x", eip);
#ifndef PRODUCT
tty->cr();
- findpc(pc);
+ findpc(eip);
tty->cr();
#endif
- tty->print_cr("rax = 0x%016lx", regs[15]);
- tty->print_cr("rbx = 0x%016lx", regs[12]);
- tty->print_cr("rcx = 0x%016lx", regs[14]);
- tty->print_cr("rdx = 0x%016lx", regs[13]);
- tty->print_cr("rdi = 0x%016lx", regs[8]);
- tty->print_cr("rsi = 0x%016lx", regs[9]);
- tty->print_cr("rbp = 0x%016lx", regs[10]);
- tty->print_cr("rsp = 0x%016lx", regs[11]);
- tty->print_cr("r8 = 0x%016lx", regs[7]);
- tty->print_cr("r9 = 0x%016lx", regs[6]);
- tty->print_cr("r10 = 0x%016lx", regs[5]);
- tty->print_cr("r11 = 0x%016lx", regs[4]);
- tty->print_cr("r12 = 0x%016lx", regs[3]);
- tty->print_cr("r13 = 0x%016lx", regs[2]);
- tty->print_cr("r14 = 0x%016lx", regs[1]);
- tty->print_cr("r15 = 0x%016lx", regs[0]);
+ tty->print_cr("rax, = 0x%08x", rax);
+ tty->print_cr("rbx, = 0x%08x", rbx);
+ tty->print_cr("rcx = 0x%08x", rcx);
+ tty->print_cr("rdx = 0x%08x", rdx);
+ tty->print_cr("rdi = 0x%08x", rdi);
+ tty->print_cr("rsi = 0x%08x", rsi);
+ tty->print_cr("rbp, = 0x%08x", rbp);
+ tty->print_cr("rsp = 0x%08x", rsp);
BREAKPOINT;
}
- ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
} else {
ttyLocker ttyl;
- ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
- msg);
+ ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
+ assert(false, "DEBUG MESSAGE");
}
+ ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
}
-void MacroAssembler::os_breakpoint() {
- // instead of directly emitting a breakpoint, call os:breakpoint for
- // better debugability
- // This shouldn't need alignment, it's an empty function
- call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
+void MacroAssembler::stop(const char* msg) {
+ ExternalAddress message((address)msg);
+ // push address of message
+ pushptr(message.addr());
+ { Label L; call(L, relocInfo::none); bind(L); } // push eip
+ pusha(); // push registers
+ call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
+ hlt();
}
-// Write serialization page so VM thread can do a pseudo remote membar.
-// We use the current thread pointer to calculate a thread specific
-// offset to write to within the page. This minimizes bus traffic
-// due to cache line collision.
-void MacroAssembler::serialize_memory(Register thread,
- Register tmp) {
+void MacroAssembler::warn(const char* msg) {
+ push_CPU_state();
- movl(tmp, thread);
- shrl(tmp, os::get_serialize_page_shift_count());
- andl(tmp, (os::vm_page_size() - sizeof(int)));
+ ExternalAddress message((address) msg);
+ // push address of message
+ pushptr(message.addr());
- Address index(noreg, tmp, Address::times_1);
- ExternalAddress page(os::get_memory_serialize_page());
-
- movptr(ArrayAddress(page, index), tmp);
+ call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
+ addl(rsp, wordSize); // discard argument
+ pop_CPU_state();
}
-void MacroAssembler::verify_tlab() {
-#ifdef ASSERT
- if (UseTLAB) {
- Label next, ok;
- Register t1 = rsi;
+#else // _LP64
- pushq(t1);
+// 64 bit versions
- movq(t1, Address(r15_thread, in_bytes(JavaThread::tlab_top_offset())));
- cmpq(t1, Address(r15_thread, in_bytes(JavaThread::tlab_start_offset())));
- jcc(Assembler::aboveEqual, next);
- stop("assert(top >= start)");
- should_not_reach_here();
+Address MacroAssembler::as_Address(AddressLiteral adr) {
+ // amd64 always does this as a pc-rel
+ // we can be absolute or disp based on the instruction type
+ // jmp/call are displacements others are absolute
+ assert(!adr.is_lval(), "must be rval");
+ assert(reachable(adr), "must be");
+ return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
- bind(next);
- movq(t1, Address(r15_thread, in_bytes(JavaThread::tlab_end_offset())));
- cmpq(t1, Address(r15_thread, in_bytes(JavaThread::tlab_top_offset())));
- jcc(Assembler::aboveEqual, ok);
- stop("assert(top <= end)");
- should_not_reach_here();
-
- bind(ok);
-
- popq(t1);
- }
-#endif
}
-// Defines obj, preserves var_size_in_bytes
-void MacroAssembler::eden_allocate(Register obj,
- Register var_size_in_bytes,
- int con_size_in_bytes,
- Register t1,
- Label& slow_case) {
- assert(obj == rax, "obj must be in rax for cmpxchg");
- assert_different_registers(obj, var_size_in_bytes, t1);
- Register end = t1;
- Label retry;
- bind(retry);
- ExternalAddress heap_top((address) Universe::heap()->top_addr());
- movptr(obj, heap_top);
- if (var_size_in_bytes == noreg) {
- leaq(end, Address(obj, con_size_in_bytes));
- } else {
- leaq(end, Address(obj, var_size_in_bytes, Address::times_1));
- }
- // if end < obj then we wrapped around => object too long => slow case
- cmpq(end, obj);
- jcc(Assembler::below, slow_case);
- cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr()));
-
- jcc(Assembler::above, slow_case);
- // Compare obj with the top addr, and if still equal, store the new
- // top addr in end at the address of the top addr pointer. Sets ZF
- // if was equal, and clears it otherwise. Use lock prefix for
- // atomicity on MPs.
- if (os::is_MP()) {
- lock();
- }
- cmpxchgptr(end, heap_top);
- // if someone beat us on the allocation, try again, otherwise continue
- jcc(Assembler::notEqual, retry);
+Address MacroAssembler::as_Address(ArrayAddress adr) {
+ AddressLiteral base = adr.base();
+ lea(rscratch1, base);
+ Address index = adr.index();
+ assert(index._disp == 0, "must not have disp"); // maybe it can?
+ Address array(rscratch1, index._index, index._scale, index._disp);
+ return array;
}
-// Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
-void MacroAssembler::tlab_allocate(Register obj,
- Register var_size_in_bytes,
- int con_size_in_bytes,
- Register t1,
- Register t2,
- Label& slow_case) {
- assert_different_registers(obj, t1, t2);
- assert_different_registers(obj, var_size_in_bytes, t1);
- Register end = t2;
-
- verify_tlab();
-
- movq(obj, Address(r15_thread, JavaThread::tlab_top_offset()));
- if (var_size_in_bytes == noreg) {
- leaq(end, Address(obj, con_size_in_bytes));
- } else {
- leaq(end, Address(obj, var_size_in_bytes, Address::times_1));
- }
- cmpq(end, Address(r15_thread, JavaThread::tlab_end_offset()));
- jcc(Assembler::above, slow_case);
-
- // update the tlab top pointer
- movq(Address(r15_thread, JavaThread::tlab_top_offset()), end);
-
- // recover var_size_in_bytes if necessary
- if (var_size_in_bytes == end) {
- subq(var_size_in_bytes, obj);
- }
- verify_tlab();
-}
-
-// Preserves rbx and rdx.
-void MacroAssembler::tlab_refill(Label& retry,
- Label& try_eden,
- Label& slow_case) {
- Register top = rax;
- Register t1 = rcx;
- Register t2 = rsi;
- Register t3 = r10;
- Register thread_reg = r15_thread;
- assert_different_registers(top, thread_reg, t1, t2, t3,
- /* preserve: */ rbx, rdx);
- Label do_refill, discard_tlab;
-
- if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
- // No allocation in the shared eden.
- jmp(slow_case);
- }
-
- movq(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
- movq(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
-
- // calculate amount of free space
- subq(t1, top);
- shrq(t1, LogHeapWordSize);
-
- // Retain tlab and allocate object in shared space if
- // the amount free in the tlab is too large to discard.
- cmpq(t1, Address(thread_reg, // size_t
- in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
- jcc(Assembler::lessEqual, discard_tlab);
-
- // Retain
- mov64(t2, ThreadLocalAllocBuffer::refill_waste_limit_increment());
- addq(Address(thread_reg, // size_t
- in_bytes(JavaThread::tlab_refill_waste_limit_offset())),
- t2);
- if (TLABStats) {
- // increment number of slow_allocations
- addl(Address(thread_reg, // unsigned int
- in_bytes(JavaThread::tlab_slow_allocations_offset())),
- 1);
- }
- jmp(try_eden);
-
- bind(discard_tlab);
- if (TLABStats) {
- // increment number of refills
- addl(Address(thread_reg, // unsigned int
- in_bytes(JavaThread::tlab_number_of_refills_offset())),
- 1);
- // accumulate wastage -- t1 is amount free in tlab
- addl(Address(thread_reg, // unsigned int
- in_bytes(JavaThread::tlab_fast_refill_waste_offset())),
- t1);
- }
-
- // if tlab is currently allocated (top or end != null) then
- // fill [top, end + alignment_reserve) with array object
- testq(top, top);
- jcc(Assembler::zero, do_refill);
-
- // set up the mark word
- mov64(t3, (int64_t) markOopDesc::prototype()->copy_set_hash(0x2));
- movq(Address(top, oopDesc::mark_offset_in_bytes()), t3);
- // set the length to the remaining space
- subq(t1, typeArrayOopDesc::header_size(T_INT));
- addq(t1, (int)ThreadLocalAllocBuffer::alignment_reserve());
- shlq(t1, log2_intptr(HeapWordSize / sizeof(jint)));
- movq(Address(top, arrayOopDesc::length_offset_in_bytes()), t1);
- // set klass to intArrayKlass
- movptr(t1, ExternalAddress((address) Universe::intArrayKlassObj_addr()));
- // store klass last. concurrent gcs assumes klass length is valid if
- // klass field is not null.
- store_klass(top, t1);
-
- // refill the tlab with an eden allocation
- bind(do_refill);
- movq(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
- shlq(t1, LogHeapWordSize);
- // add object_size ??
- eden_allocate(top, t1, 0, t2, slow_case);
-
- // Check that t1 was preserved in eden_allocate.
-#ifdef ASSERT
- if (UseTLAB) {
- Label ok;
- Register tsize = rsi;
- assert_different_registers(tsize, thread_reg, t1);
- pushq(tsize);
- movq(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
- shlq(tsize, LogHeapWordSize);
- cmpq(t1, tsize);
- jcc(Assembler::equal, ok);
- stop("assert(t1 != tlab size)");
- should_not_reach_here();
-
- bind(ok);
- popq(tsize);
- }
-#endif
- movq(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top);
- movq(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top);
- addq(top, t1);
- subq(top, (int)ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
- movq(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top);
- verify_tlab();
- jmp(retry);
-}
-
-
-int MacroAssembler::biased_locking_enter(Register lock_reg, Register obj_reg, Register swap_reg, Register tmp_reg,
+int MacroAssembler::biased_locking_enter(Register lock_reg,
+ Register obj_reg,
+ Register swap_reg,
+ Register tmp_reg,
bool swap_reg_contains_mark,
- Label& done, Label* slow_case,
+ Label& done,
+ Label* slow_case,
BiasedLockingCounters* counters) {
assert(UseBiasedLocking, "why call this otherwise?");
assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
@@ -5129,6 +4958,426 @@ int MacroAssembler::biased_locking_enter(Register lock_reg, Register obj_reg, Re
return null_check_offset;
}
+void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
+ Label L, E;
+
+#ifdef _WIN64
+ // Windows always allocates space for it's register args
+ assert(num_args <= 4, "only register arguments supported");
+ subq(rsp, frame::arg_reg_save_area_bytes);
+#endif
+
+ // Align stack if necessary
+ testl(rsp, 15);
+ jcc(Assembler::zero, L);
+
+ subq(rsp, 8);
+ {
+ call(RuntimeAddress(entry_point));
+ }
+ addq(rsp, 8);
+ jmp(E);
+
+ bind(L);
+ {
+ call(RuntimeAddress(entry_point));
+ }
+
+ bind(E);
+
+#ifdef _WIN64
+ // restore stack pointer
+ addq(rsp, frame::arg_reg_save_area_bytes);
+#endif
+
+}
+
+void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
+ assert(!src2.is_lval(), "should use cmpptr");
+
+ if (reachable(src2)) {
+ cmpq(src1, as_Address(src2));
+ } else {
+ lea(rscratch1, src2);
+ Assembler::cmpq(src1, Address(rscratch1, 0));
+ }
+}
+
+int MacroAssembler::corrected_idivq(Register reg) {
+ // Full implementation of Java ldiv and lrem; checks for special
+ // case as described in JVM spec., p.243 & p.271. The function
+ // returns the (pc) offset of the idivl instruction - may be needed
+ // for implicit exceptions.
+ //
+ // normal case special case
+ //
+ // input : rax: dividend min_long
+ // reg: divisor (may not be eax/edx) -1
+ //
+ // output: rax: quotient (= rax idiv reg) min_long
+ // rdx: remainder (= rax irem reg) 0
+ assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
+ static const int64_t min_long = 0x8000000000000000;
+ Label normal_case, special_case;
+
+ // check for special case
+ cmp64(rax, ExternalAddress((address) &min_long));
+ jcc(Assembler::notEqual, normal_case);
+ xorl(rdx, rdx); // prepare rdx for possible special case (where
+ // remainder = 0)
+ cmpq(reg, -1);
+ jcc(Assembler::equal, special_case);
+
+ // handle normal case
+ bind(normal_case);
+ cdqq();
+ int idivq_offset = offset();
+ idivq(reg);
+
+ // normal and special case exit
+ bind(special_case);
+
+ return idivq_offset;
+}
+
+void MacroAssembler::decrementq(Register reg, int value) {
+ if (value == min_jint) { subq(reg, value); return; }
+ if (value < 0) { incrementq(reg, -value); return; }
+ if (value == 0) { ; return; }
+ if (value == 1 && UseIncDec) { decq(reg) ; return; }
+ /* else */ { subq(reg, value) ; return; }
+}
+
+void MacroAssembler::decrementq(Address dst, int value) {
+ if (value == min_jint) { subq(dst, value); return; }
+ if (value < 0) { incrementq(dst, -value); return; }
+ if (value == 0) { ; return; }
+ if (value == 1 && UseIncDec) { decq(dst) ; return; }
+ /* else */ { subq(dst, value) ; return; }
+}
+
+void MacroAssembler::fat_nop() {
+ // A 5 byte nop that is safe for patching (see patch_verified_entry)
+ // Recommened sequence from 'Software Optimization Guide for the AMD
+ // Hammer Processor'
+ emit_byte(0x66);
+ emit_byte(0x66);
+ emit_byte(0x90);
+ emit_byte(0x66);
+ emit_byte(0x90);
+}
+
+void MacroAssembler::incrementq(Register reg, int value) {
+ if (value == min_jint) { addq(reg, value); return; }
+ if (value < 0) { decrementq(reg, -value); return; }
+ if (value == 0) { ; return; }
+ if (value == 1 && UseIncDec) { incq(reg) ; return; }
+ /* else */ { addq(reg, value) ; return; }
+}
+
+void MacroAssembler::incrementq(Address dst, int value) {
+ if (value == min_jint) { addq(dst, value); return; }
+ if (value < 0) { decrementq(dst, -value); return; }
+ if (value == 0) { ; return; }
+ if (value == 1 && UseIncDec) { incq(dst) ; return; }
+ /* else */ { addq(dst, value) ; return; }
+}
+
+// 32bit can do a case table jump in one instruction but we no longer allow the base
+// to be installed in the Address class
+void MacroAssembler::jump(ArrayAddress entry) {
+ lea(rscratch1, entry.base());
+ Address dispatch = entry.index();
+ assert(dispatch._base == noreg, "must be");
+ dispatch._base = rscratch1;
+ jmp(dispatch);
+}
+
+void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
+ ShouldNotReachHere(); // 64bit doesn't use two regs
+ cmpq(x_lo, y_lo);
+}
+
+void MacroAssembler::lea(Register dst, AddressLiteral src) {
+ mov_literal64(dst, (intptr_t)src.target(), src.rspec());
+}
+
+void MacroAssembler::lea(Address dst, AddressLiteral adr) {
+ mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
+ movptr(dst, rscratch1);
+}
+
+void MacroAssembler::leave() {
+ // %%% is this really better? Why not on 32bit too?
+ emit_byte(0xC9); // LEAVE
+}
+
+void MacroAssembler::lneg(Register hi, Register lo) {
+ ShouldNotReachHere(); // 64bit doesn't use two regs
+ negq(lo);
+}
+
+void MacroAssembler::movoop(Register dst, jobject obj) {
+ mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
+}
+
+void MacroAssembler::movoop(Address dst, jobject obj) {
+ mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
+ movq(dst, rscratch1);
+}
+
+void MacroAssembler::movptr(Register dst, AddressLiteral src) {
+ if (src.is_lval()) {
+ mov_literal64(dst, (intptr_t)src.target(), src.rspec());
+ } else {
+ if (reachable(src)) {
+ movq(dst, as_Address(src));
+ } else {
+ lea(rscratch1, src);
+ movq(dst, Address(rscratch1,0));
+ }
+ }
+}
+
+void MacroAssembler::movptr(ArrayAddress dst, Register src) {
+ movq(as_Address(dst), src);
+}
+
+void MacroAssembler::movptr(Register dst, ArrayAddress src) {
+ movq(dst, as_Address(src));
+}
+
+// src should NEVER be a real pointer. Use AddressLiteral for true pointers
+void MacroAssembler::movptr(Address dst, intptr_t src) {
+ mov64(rscratch1, src);
+ movq(dst, rscratch1);
+}
+
+// These are mostly for initializing NULL
+void MacroAssembler::movptr(Address dst, int32_t src) {
+ movslq(dst, src);
+}
+
+void MacroAssembler::movptr(Register dst, int32_t src) {
+ mov64(dst, (intptr_t)src);
+}
+
+void MacroAssembler::pushoop(jobject obj) {
+ movoop(rscratch1, obj);
+ push(rscratch1);
+}
+
+void MacroAssembler::pushptr(AddressLiteral src) {
+ lea(rscratch1, src);
+ if (src.is_lval()) {
+ push(rscratch1);
+ } else {
+ pushq(Address(rscratch1, 0));
+ }
+}
+
+void MacroAssembler::reset_last_Java_frame(bool clear_fp,
+ bool clear_pc) {
+ // we must set sp to zero to clear frame
+ movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), (int32_t)NULL_WORD);
+ // must clear fp, so that compiled frames are not confused; it is
+ // possible that we need it only for debugging
+ if (clear_fp) {
+ movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), (int32_t)NULL_WORD);
+ }
+
+ if (clear_pc) {
+ movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), (int32_t)NULL_WORD);
+ }
+}
+
+void MacroAssembler::set_last_Java_frame(Register last_java_sp,
+ Register last_java_fp,
+ address last_java_pc) {
+ // determine last_java_sp register
+ if (!last_java_sp->is_valid()) {
+ last_java_sp = rsp;
+ }
+
+ // last_java_fp is optional
+ if (last_java_fp->is_valid()) {
+ movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
+ last_java_fp);
+ }
+
+ // last_java_pc is optional
+ if (last_java_pc != NULL) {
+ Address java_pc(r15_thread,
+ JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
+ lea(rscratch1, InternalAddress(last_java_pc));
+ movptr(java_pc, rscratch1);
+ }
+
+ movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
+}
+
+static void pass_arg0(MacroAssembler* masm, Register arg) {
+ if (c_rarg0 != arg ) {
+ masm->mov(c_rarg0, arg);
+ }
+}
+
+static void pass_arg1(MacroAssembler* masm, Register arg) {
+ if (c_rarg1 != arg ) {
+ masm->mov(c_rarg1, arg);
+ }
+}
+
+static void pass_arg2(MacroAssembler* masm, Register arg) {
+ if (c_rarg2 != arg ) {
+ masm->mov(c_rarg2, arg);
+ }
+}
+
+static void pass_arg3(MacroAssembler* masm, Register arg) {
+ if (c_rarg3 != arg ) {
+ masm->mov(c_rarg3, arg);
+ }
+}
+
+void MacroAssembler::stop(const char* msg) {
+ address rip = pc();
+ pusha(); // get regs on stack
+ lea(c_rarg0, ExternalAddress((address) msg));
+ lea(c_rarg1, InternalAddress(rip));
+ movq(c_rarg2, rsp); // pass pointer to regs array
+ andq(rsp, -16); // align stack as required by ABI
+ call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
+ hlt();
+}
+
+void MacroAssembler::warn(const char* msg) {
+ push(r12);
+ movq(r12, rsp);
+ andq(rsp, -16); // align stack as required by push_CPU_state and call
+
+ push_CPU_state(); // keeps alignment at 16 bytes
+ lea(c_rarg0, ExternalAddress((address) msg));
+ call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0);
+ pop_CPU_state();
+
+ movq(rsp, r12);
+ pop(r12);
+}
+
+#ifndef PRODUCT
+extern "C" void findpc(intptr_t x);
+#endif
+
+void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
+ // In order to get locks to work, we need to fake a in_VM state
+ if (ShowMessageBoxOnError ) {
+ JavaThread* thread = JavaThread::current();
+ JavaThreadState saved_state = thread->thread_state();
+ thread->set_thread_state(_thread_in_vm);
+#ifndef PRODUCT
+ if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
+ ttyLocker ttyl;
+ BytecodeCounter::print();
+ }
+#endif
+ // To see where a verify_oop failed, get $ebx+40/X for this frame.
+ // XXX correct this offset for amd64
+ // This is the value of eip which points to where verify_oop will return.
+ if (os::message_box(msg, "Execution stopped, print registers?")) {
+ ttyLocker ttyl;
+ tty->print_cr("rip = 0x%016lx", pc);
+#ifndef PRODUCT
+ tty->cr();
+ findpc(pc);
+ tty->cr();
+#endif
+ tty->print_cr("rax = 0x%016lx", regs[15]);
+ tty->print_cr("rbx = 0x%016lx", regs[12]);
+ tty->print_cr("rcx = 0x%016lx", regs[14]);
+ tty->print_cr("rdx = 0x%016lx", regs[13]);
+ tty->print_cr("rdi = 0x%016lx", regs[8]);
+ tty->print_cr("rsi = 0x%016lx", regs[9]);
+ tty->print_cr("rbp = 0x%016lx", regs[10]);
+ tty->print_cr("rsp = 0x%016lx", regs[11]);
+ tty->print_cr("r8 = 0x%016lx", regs[7]);
+ tty->print_cr("r9 = 0x%016lx", regs[6]);
+ tty->print_cr("r10 = 0x%016lx", regs[5]);
+ tty->print_cr("r11 = 0x%016lx", regs[4]);
+ tty->print_cr("r12 = 0x%016lx", regs[3]);
+ tty->print_cr("r13 = 0x%016lx", regs[2]);
+ tty->print_cr("r14 = 0x%016lx", regs[1]);
+ tty->print_cr("r15 = 0x%016lx", regs[0]);
+ BREAKPOINT;
+ }
+ ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
+ } else {
+ ttyLocker ttyl;
+ ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
+ msg);
+ }
+}
+
+#endif // _LP64
+
+// Now versions that are common to 32/64 bit
+
+void MacroAssembler::addptr(Register dst, int32_t imm32) {
+ LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
+}
+
+void MacroAssembler::addptr(Register dst, Register src) {
+ LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
+}
+
+void MacroAssembler::addptr(Address dst, Register src) {
+ LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
+}
+
+void MacroAssembler::align(int modulus) {
+ if (offset() % modulus != 0) {
+ nop(modulus - (offset() % modulus));
+ }
+}
+
+void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
+ andpd(dst, as_Address(src));
+}
+
+void MacroAssembler::andptr(Register dst, int32_t imm32) {
+ LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
+}
+
+void MacroAssembler::atomic_incl(AddressLiteral counter_addr) {
+ pushf();
+ if (os::is_MP())
+ lock();
+ incrementl(counter_addr);
+ popf();
+}
+
+// Writes to stack successive pages until offset reached to check for
+// stack overflow + shadow pages. This clobbers tmp.
+void MacroAssembler::bang_stack_size(Register size, Register tmp) {
+ movptr(tmp, rsp);
+ // Bang stack for total size given plus shadow page size.
+ // Bang one page at a time because large size can bang beyond yellow and
+ // red zones.
+ Label loop;
+ bind(loop);
+ movl(Address(tmp, (-os::vm_page_size())), size );
+ subptr(tmp, os::vm_page_size());
+ subl(size, os::vm_page_size());
+ jcc(Assembler::greater, loop);
+
+ // Bang down shadow pages too.
+ // The -1 because we already subtracted 1 page.
+ for (int i = 0; i< StackShadowPages-1; i++) {
+ // this could be any sized move but this is can be a debugging crumb
+ // so the bigger the better.
+ movptr(Address(tmp, (-i*os::vm_page_size())), size );
+ }
+}
void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
assert(UseBiasedLocking, "why call this otherwise?");
@@ -5139,41 +5388,1943 @@ void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, La
// a higher level. Second, if the bias was revoked while we held the
// lock, the object could not be rebiased toward another thread, so
// the bias bit would be clear.
- movq(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
- andq(temp_reg, markOopDesc::biased_lock_mask_in_place);
- cmpq(temp_reg, markOopDesc::biased_lock_pattern);
+ movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
+ andptr(temp_reg, markOopDesc::biased_lock_mask_in_place);
+ cmpptr(temp_reg, markOopDesc::biased_lock_pattern);
jcc(Assembler::equal, done);
}
+void MacroAssembler::c2bool(Register x) {
+ // implements x == 0 ? 0 : 1
+ // note: must only look at least-significant byte of x
+ // since C-style booleans are stored in one byte
+ // only! (was bug)
+ andl(x, 0xFF);
+ setb(Assembler::notZero, x);
+}
+
+// Wouldn't need if AddressLiteral version had new name
+void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
+ Assembler::call(L, rtype);
+}
+
+void MacroAssembler::call(Register entry) {
+ Assembler::call(entry);
+}
+
+void MacroAssembler::call(AddressLiteral entry) {
+ if (reachable(entry)) {
+ Assembler::call_literal(entry.target(), entry.rspec());
+ } else {
+ lea(rscratch1, entry);
+ Assembler::call(rscratch1);
+ }
+}
+
+// Implementation of call_VM versions
+
+void MacroAssembler::call_VM(Register oop_result,
+ address entry_point,
+ bool check_exceptions) {
+ Label C, E;
+ call(C, relocInfo::none);
+ jmp(E);
+
+ bind(C);
+ call_VM_helper(oop_result, entry_point, 0, check_exceptions);
+ ret(0);
+
+ bind(E);
+}
+
+void MacroAssembler::call_VM(Register oop_result,
+ address entry_point,
+ Register arg_1,
+ bool check_exceptions) {
+ Label C, E;
+ call(C, relocInfo::none);
+ jmp(E);
+
+ bind(C);
+ pass_arg1(this, arg_1);
+ call_VM_helper(oop_result, entry_point, 1, check_exceptions);
+ ret(0);
+
+ bind(E);
+}
+
+void MacroAssembler::call_VM(Register oop_result,
+ address entry_point,
+ Register arg_1,
+ Register arg_2,
+ bool check_exceptions) {
+ Label C, E;
+ call(C, relocInfo::none);
+ jmp(E);
+
+ bind(C);
+
+ LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
+
+ pass_arg2(this, arg_2);
+ pass_arg1(this, arg_1);
+ call_VM_helper(oop_result, entry_point, 2, check_exceptions);
+ ret(0);
+
+ bind(E);
+}
+
+void MacroAssembler::call_VM(Register oop_result,
+ address entry_point,
+ Register arg_1,
+ Register arg_2,
+ Register arg_3,
+ bool check_exceptions) {
+ Label C, E;
+ call(C, relocInfo::none);
+ jmp(E);
+
+ bind(C);
+
+ LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
+ LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
+ pass_arg3(this, arg_3);
+
+ LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
+ pass_arg2(this, arg_2);
+
+ pass_arg1(this, arg_1);
+ call_VM_helper(oop_result, entry_point, 3, check_exceptions);
+ ret(0);
+
+ bind(E);
+}
+
+void MacroAssembler::call_VM(Register oop_result,
+ Register last_java_sp,
+ address entry_point,
+ int number_of_arguments,
+ bool check_exceptions) {
+ Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
+ call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
+}
+
+void MacroAssembler::call_VM(Register oop_result,
+ Register last_java_sp,
+ address entry_point,
+ Register arg_1,
+ bool check_exceptions) {
+ pass_arg1(this, arg_1);
+ call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
+}
+
+void MacroAssembler::call_VM(Register oop_result,
+ Register last_java_sp,
+ address entry_point,
+ Register arg_1,
+ Register arg_2,
+ bool check_exceptions) {
+
+ LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
+ pass_arg2(this, arg_2);
+ pass_arg1(this, arg_1);
+ call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
+}
+
+void MacroAssembler::call_VM(Register oop_result,
+ Register last_java_sp,
+ address entry_point,
+ Register arg_1,
+ Register arg_2,
+ Register arg_3,
+ bool check_exceptions) {
+ LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
+ LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
+ pass_arg3(this, arg_3);
+ LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
+ pass_arg2(this, arg_2);
+ pass_arg1(this, arg_1);
+ call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
+}
+
+void MacroAssembler::call_VM_base(Register oop_result,
+ Register java_thread,
+ Register last_java_sp,
+ address entry_point,
+ int number_of_arguments,
+ bool check_exceptions) {
+ // determine java_thread register
+ if (!java_thread->is_valid()) {
+#ifdef _LP64
+ java_thread = r15_thread;
+#else
+ java_thread = rdi;
+ get_thread(java_thread);
+#endif // LP64
+ }
+ // determine last_java_sp register
+ if (!last_java_sp->is_valid()) {
+ last_java_sp = rsp;
+ }
+ // debugging support
+ assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
+ LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
+ assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
+ assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
+
+ // push java thread (becomes first argument of C function)
+
+ NOT_LP64(push(java_thread); number_of_arguments++);
+ LP64_ONLY(mov(c_rarg0, r15_thread));
+
+ // set last Java frame before call
+ assert(last_java_sp != rbp, "can't use ebp/rbp");
+
+ // Only interpreter should have to set fp
+ set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
+
+ // do the call, remove parameters
+ MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
+
+ // restore the thread (cannot use the pushed argument since arguments
+ // may be overwritten by C code generated by an optimizing compiler);
+ // however can use the register value directly if it is callee saved.
+ if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
+ // rdi & rsi (also r15) are callee saved -> nothing to do
+#ifdef ASSERT
+ guarantee(java_thread != rax, "change this code");
+ push(rax);
+ { Label L;
+ get_thread(rax);
+ cmpptr(java_thread, rax);
+ jcc(Assembler::equal, L);
+ stop("MacroAssembler::call_VM_base: rdi not callee saved?");
+ bind(L);
+ }
+ pop(rax);
+#endif
+ } else {
+ get_thread(java_thread);
+ }
+ // reset last Java frame
+ // Only interpreter should have to clear fp
+ reset_last_Java_frame(java_thread, true, false);
+
+#ifndef CC_INTERP
+ // C++ interp handles this in the interpreter
+ check_and_handle_popframe(java_thread);
+ check_and_handle_earlyret(java_thread);
+#endif /* CC_INTERP */
+
+ if (check_exceptions) {
+ // check for pending exceptions (java_thread is set upon return)
+ cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
+#ifndef _LP64
+ jump_cc(Assembler::notEqual,
+ RuntimeAddress(StubRoutines::forward_exception_entry()));
+#else
+ // This used to conditionally jump to forward_exception however it is
+ // possible if we relocate that the branch will not reach. So we must jump
+ // around so we can always reach
+
+ Label ok;
+ jcc(Assembler::equal, ok);
+ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
+ bind(ok);
+#endif // LP64
+ }
+
+ // get oop result if there is one and reset the value in the thread
+ if (oop_result->is_valid()) {
+ movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
+ movptr(Address(java_thread, JavaThread::vm_result_offset()), (int32_t)NULL_WORD);
+ verify_oop(oop_result, "broken oop in call_VM_base");
+ }
+}
+
+void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
+
+ // Calculate the value for last_Java_sp
+ // somewhat subtle. call_VM does an intermediate call
+ // which places a return address on the stack just under the
+ // stack pointer as the user finsihed with it. This allows
+ // use to retrieve last_Java_pc from last_Java_sp[-1].
+ // On 32bit we then have to push additional args on the stack to accomplish
+ // the actual requested call. On 64bit call_VM only can use register args
+ // so the only extra space is the return address that call_VM created.
+ // This hopefully explains the calculations here.
+
+#ifdef _LP64
+ // We've pushed one address, correct last_Java_sp
+ lea(rax, Address(rsp, wordSize));
+#else
+ lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
+#endif // LP64
+
+ call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
+
+}
+
+void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
+ call_VM_leaf_base(entry_point, number_of_arguments);
+}
+
+void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
+ pass_arg0(this, arg_0);
+ call_VM_leaf(entry_point, 1);
+}
+
+void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
+
+ LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
+ pass_arg1(this, arg_1);
+ pass_arg0(this, arg_0);
+ call_VM_leaf(entry_point, 2);
+}
+
+void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
+ LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
+ LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
+ pass_arg2(this, arg_2);
+ LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
+ pass_arg1(this, arg_1);
+ pass_arg0(this, arg_0);
+ call_VM_leaf(entry_point, 3);
+}
+
+void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
+}
+
+void MacroAssembler::check_and_handle_popframe(Register java_thread) {
+}
+
+void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
+ if (reachable(src1)) {
+ cmpl(as_Address(src1), imm);
+ } else {
+ lea(rscratch1, src1);
+ cmpl(Address(rscratch1, 0), imm);
+ }
+}
+
+void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
+ assert(!src2.is_lval(), "use cmpptr");
+ if (reachable(src2)) {
+ cmpl(src1, as_Address(src2));
+ } else {
+ lea(rscratch1, src2);
+ cmpl(src1, Address(rscratch1, 0));
+ }
+}
+
+void MacroAssembler::cmp32(Register src1, int32_t imm) {
+ Assembler::cmpl(src1, imm);
+}
+
+void MacroAssembler::cmp32(Register src1, Address src2) {
+ Assembler::cmpl(src1, src2);
+}
+
+void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
+ ucomisd(opr1, opr2);
+
+ Label L;
+ if (unordered_is_less) {
+ movl(dst, -1);
+ jcc(Assembler::parity, L);
+ jcc(Assembler::below , L);
+ movl(dst, 0);
+ jcc(Assembler::equal , L);
+ increment(dst);
+ } else { // unordered is greater
+ movl(dst, 1);
+ jcc(Assembler::parity, L);
+ jcc(Assembler::above , L);
+ movl(dst, 0);
+ jcc(Assembler::equal , L);
+ decrementl(dst);
+ }
+ bind(L);
+}
+
+void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
+ ucomiss(opr1, opr2);
+
+ Label L;
+ if (unordered_is_less) {
+ movl(dst, -1);
+ jcc(Assembler::parity, L);
+ jcc(Assembler::below , L);
+ movl(dst, 0);
+ jcc(Assembler::equal , L);
+ increment(dst);
+ } else { // unordered is greater
+ movl(dst, 1);
+ jcc(Assembler::parity, L);
+ jcc(Assembler::above , L);
+ movl(dst, 0);
+ jcc(Assembler::equal , L);
+ decrementl(dst);
+ }
+ bind(L);
+}
+
+
+void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
+ if (reachable(src1)) {
+ cmpb(as_Address(src1), imm);
+ } else {
+ lea(rscratch1, src1);
+ cmpb(Address(rscratch1, 0), imm);
+ }
+}
+
+void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
+#ifdef _LP64
+ if (src2.is_lval()) {
+ movptr(rscratch1, src2);
+ Assembler::cmpq(src1, rscratch1);
+ } else if (reachable(src2)) {
+ cmpq(src1, as_Address(src2));
+ } else {
+ lea(rscratch1, src2);
+ Assembler::cmpq(src1, Address(rscratch1, 0));
+ }
+#else
+ if (src2.is_lval()) {
+ cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
+ } else {
+ cmpl(src1, as_Address(src2));
+ }
+#endif // _LP64
+}
+
+void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
+ assert(src2.is_lval(), "not a mem-mem compare");
+#ifdef _LP64
+ // moves src2's literal address
+ movptr(rscratch1, src2);
+ Assembler::cmpq(src1, rscratch1);
+#else
+ cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
+#endif // _LP64
+}
+
+void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
+ if (reachable(adr)) {
+ if (os::is_MP())
+ lock();
+ cmpxchgptr(reg, as_Address(adr));
+ } else {
+ lea(rscratch1, adr);
+ if (os::is_MP())
+ lock();
+ cmpxchgptr(reg, Address(rscratch1, 0));
+ }
+}
+
+void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
+ LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
+}
+
+void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
+ comisd(dst, as_Address(src));
+}
+
+void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
+ comiss(dst, as_Address(src));
+}
+
+
+void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
+ Condition negated_cond = negate_condition(cond);
+ Label L;
+ jcc(negated_cond, L);
+ atomic_incl(counter_addr);
+ bind(L);
+}
+
+int MacroAssembler::corrected_idivl(Register reg) {
+ // Full implementation of Java idiv and irem; checks for
+ // special case as described in JVM spec., p.243 & p.271.
+ // The function returns the (pc) offset of the idivl
+ // instruction - may be needed for implicit exceptions.
+ //
+ // normal case special case
+ //
+ // input : rax,: dividend min_int
+ // reg: divisor (may not be rax,/rdx) -1
+ //
+ // output: rax,: quotient (= rax, idiv reg) min_int
+ // rdx: remainder (= rax, irem reg) 0
+ assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
+ const int min_int = 0x80000000;
+ Label normal_case, special_case;
+
+ // check for special case
+ cmpl(rax, min_int);
+ jcc(Assembler::notEqual, normal_case);
+ xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
+ cmpl(reg, -1);
+ jcc(Assembler::equal, special_case);
+
+ // handle normal case
+ bind(normal_case);
+ cdql();
+ int idivl_offset = offset();
+ idivl(reg);
+
+ // normal and special case exit
+ bind(special_case);
+
+ return idivl_offset;
+}
+
+
+
+void MacroAssembler::decrementl(Register reg, int value) {
+ if (value == min_jint) {subl(reg, value) ; return; }
+ if (value < 0) { incrementl(reg, -value); return; }
+ if (value == 0) { ; return; }
+ if (value == 1 && UseIncDec) { decl(reg) ; return; }
+ /* else */ { subl(reg, value) ; return; }
+}
+
+void MacroAssembler::decrementl(Address dst, int value) {
+ if (value == min_jint) {subl(dst, value) ; return; }
+ if (value < 0) { incrementl(dst, -value); return; }
+ if (value == 0) { ; return; }
+ if (value == 1 && UseIncDec) { decl(dst) ; return; }
+ /* else */ { subl(dst, value) ; return; }
+}
+
+void MacroAssembler::division_with_shift (Register reg, int shift_value) {
+ assert (shift_value > 0, "illegal shift value");
+ Label _is_positive;
+ testl (reg, reg);
+ jcc (Assembler::positive, _is_positive);
+ int offset = (1 << shift_value) - 1 ;
+
+ if (offset == 1) {
+ incrementl(reg);
+ } else {
+ addl(reg, offset);
+ }
+
+ bind (_is_positive);
+ sarl(reg, shift_value);
+}
+
+// !defined(COMPILER2) is because of stupid core builds
+#if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2)
+void MacroAssembler::empty_FPU_stack() {
+ if (VM_Version::supports_mmx()) {
+ emms();
+ } else {
+ for (int i = 8; i-- > 0; ) ffree(i);
+ }
+}
+#endif // !LP64 || C1 || !C2
+
+
+// Defines obj, preserves var_size_in_bytes
+void MacroAssembler::eden_allocate(Register obj,
+ Register var_size_in_bytes,
+ int con_size_in_bytes,
+ Register t1,
+ Label& slow_case) {
+ assert(obj == rax, "obj must be in rax, for cmpxchg");
+ assert_different_registers(obj, var_size_in_bytes, t1);
+ Register end = t1;
+ Label retry;
+ bind(retry);
+ ExternalAddress heap_top((address) Universe::heap()->top_addr());
+ movptr(obj, heap_top);
+ if (var_size_in_bytes == noreg) {
+ lea(end, Address(obj, con_size_in_bytes));
+ } else {
+ lea(end, Address(obj, var_size_in_bytes, Address::times_1));
+ }
+ // if end < obj then we wrapped around => object too long => slow case
+ cmpptr(end, obj);
+ jcc(Assembler::below, slow_case);
+ cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr()));
+ jcc(Assembler::above, slow_case);
+ // Compare obj with the top addr, and if still equal, store the new top addr in
+ // end at the address of the top addr pointer. Sets ZF if was equal, and clears
+ // it otherwise. Use lock prefix for atomicity on MPs.
+ locked_cmpxchgptr(end, heap_top);
+ jcc(Assembler::notEqual, retry);
+}
+
+void MacroAssembler::enter() {
+ push(rbp);
+ mov(rbp, rsp);
+}
+
+void MacroAssembler::fcmp(Register tmp) {
+ fcmp(tmp, 1, true, true);
+}
+
+void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
+ assert(!pop_right || pop_left, "usage error");
+ if (VM_Version::supports_cmov()) {
+ assert(tmp == noreg, "unneeded temp");
+ if (pop_left) {
+ fucomip(index);
+ } else {
+ fucomi(index);
+ }
+ if (pop_right) {
+ fpop();
+ }
+ } else {
+ assert(tmp != noreg, "need temp");
+ if (pop_left) {
+ if (pop_right) {
+ fcompp();
+ } else {
+ fcomp(index);
+ }
+ } else {
+ fcom(index);
+ }
+ // convert FPU condition into eflags condition via rax,
+ save_rax(tmp);
+ fwait(); fnstsw_ax();
+ sahf();
+ restore_rax(tmp);
+ }
+ // condition codes set as follows:
+ //
+ // CF (corresponds to C0) if x < y
+ // PF (corresponds to C2) if unordered
+ // ZF (corresponds to C3) if x = y
+}
+
+void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
+ fcmp2int(dst, unordered_is_less, 1, true, true);
+}
+
+void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
+ fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
+ Label L;
+ if (unordered_is_less) {
+ movl(dst, -1);
+ jcc(Assembler::parity, L);
+ jcc(Assembler::below , L);
+ movl(dst, 0);
+ jcc(Assembler::equal , L);
+ increment(dst);
+ } else { // unordered is greater
+ movl(dst, 1);
+ jcc(Assembler::parity, L);
+ jcc(Assembler::above , L);
+ movl(dst, 0);
+ jcc(Assembler::equal , L);
+ decrementl(dst);
+ }
+ bind(L);
+}
+
+void MacroAssembler::fld_d(AddressLiteral src) {
+ fld_d(as_Address(src));
+}
+
+void MacroAssembler::fld_s(AddressLiteral src) {
+ fld_s(as_Address(src));
+}
+
+void MacroAssembler::fld_x(AddressLiteral src) {
+ Assembler::fld_x(as_Address(src));
+}
+
+void MacroAssembler::fldcw(AddressLiteral src) {
+ Assembler::fldcw(as_Address(src));
+}
+
+void MacroAssembler::fpop() {
+ ffree();
+ fincstp();
+}
+
+void MacroAssembler::fremr(Register tmp) {
+ save_rax(tmp);
+ { Label L;
+ bind(L);
+ fprem();
+ fwait(); fnstsw_ax();
+#ifdef _LP64
+ testl(rax, 0x400);
+ jcc(Assembler::notEqual, L);
+#else
+ sahf();
+ jcc(Assembler::parity, L);
+#endif // _LP64
+ }
+ restore_rax(tmp);
+ // Result is in ST0.
+ // Note: fxch & fpop to get rid of ST1
+ // (otherwise FPU stack could overflow eventually)
+ fxch(1);
+ fpop();
+}
+
+
+void MacroAssembler::incrementl(AddressLiteral dst) {
+ if (reachable(dst)) {
+ incrementl(as_Address(dst));
+ } else {
+ lea(rscratch1, dst);
+ incrementl(Address(rscratch1, 0));
+ }
+}
+
+void MacroAssembler::incrementl(ArrayAddress dst) {
+ incrementl(as_Address(dst));
+}
+
+void MacroAssembler::incrementl(Register reg, int value) {
+ if (value == min_jint) {addl(reg, value) ; return; }
+ if (value < 0) { decrementl(reg, -value); return; }
+ if (value == 0) { ; return; }
+ if (value == 1 && UseIncDec) { incl(reg) ; return; }
+ /* else */ { addl(reg, value) ; return; }
+}
+
+void MacroAssembler::incrementl(Address dst, int value) {
+ if (value == min_jint) {addl(dst, value) ; return; }
+ if (value < 0) { decrementl(dst, -value); return; }
+ if (value == 0) { ; return; }
+ if (value == 1 && UseIncDec) { incl(dst) ; return; }
+ /* else */ { addl(dst, value) ; return; }
+}
+
+void MacroAssembler::jump(AddressLiteral dst) {
+ if (reachable(dst)) {
+ jmp_literal(dst.target(), dst.rspec());
+ } else {
+ lea(rscratch1, dst);
+ jmp(rscratch1);
+ }
+}
+
+void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
+ if (reachable(dst)) {
+ InstructionMark im(this);
+ relocate(dst.reloc());
+ const int short_size = 2;
+ const int long_size = 6;
+ int offs = (intptr_t)dst.target() - ((intptr_t)_code_pos);
+ if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
+ // 0111 tttn #8-bit disp
+ emit_byte(0x70 | cc);
+ emit_byte((offs - short_size) & 0xFF);
+ } else {
+ // 0000 1111 1000 tttn #32-bit disp
+ emit_byte(0x0F);
+ emit_byte(0x80 | cc);
+ emit_long(offs - long_size);
+ }
+ } else {
+#ifdef ASSERT
+ warning("reversing conditional branch");
+#endif /* ASSERT */
+ Label skip;
+ jccb(reverse[cc], skip);
+ lea(rscratch1, dst);
+ Assembler::jmp(rscratch1);
+ bind(skip);
+ }
+}
+
+void MacroAssembler::ldmxcsr(AddressLiteral src) {
+ if (reachable(src)) {
+ Assembler::ldmxcsr(as_Address(src));
+ } else {
+ lea(rscratch1, src);
+ Assembler::ldmxcsr(Address(rscratch1, 0));
+ }
+}
+
+int MacroAssembler::load_signed_byte(Register dst, Address src) {
+ int off;
+ if (LP64_ONLY(true ||) VM_Version::is_P6()) {
+ off = offset();
+ movsbl(dst, src); // movsxb
+ } else {
+ off = load_unsigned_byte(dst, src);
+ shll(dst, 24);
+ sarl(dst, 24);
+ }
+ return off;
+}
+
+// word => int32 which seems bad for 64bit
+int MacroAssembler::load_signed_word(Register dst, Address src) {
+ int off;
+ if (LP64_ONLY(true ||) VM_Version::is_P6()) {
+ // This is dubious to me since it seems safe to do a signed 16 => 64 bit
+ // version but this is what 64bit has always done. This seems to imply
+ // that users are only using 32bits worth.
+ off = offset();
+ movswl(dst, src); // movsxw
+ } else {
+ off = load_unsigned_word(dst, src);
+ shll(dst, 16);
+ sarl(dst, 16);
+ }
+ return off;
+}
+
+int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
+ // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
+ // and "3.9 Partial Register Penalties", p. 22).
+ int off;
+ if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
+ off = offset();
+ movzbl(dst, src); // movzxb
+ } else {
+ xorl(dst, dst);
+ off = offset();
+ movb(dst, src);
+ }
+ return off;
+}
+
+int MacroAssembler::load_unsigned_word(Register dst, Address src) {
+ // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
+ // and "3.9 Partial Register Penalties", p. 22).
+ int off;
+ if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
+ off = offset();
+ movzwl(dst, src); // movzxw
+ } else {
+ xorl(dst, dst);
+ off = offset();
+ movw(dst, src);
+ }
+ return off;
+}
+
+void MacroAssembler::mov32(AddressLiteral dst, Register src) {
+ if (reachable(dst)) {
+ movl(as_Address(dst), src);
+ } else {
+ lea(rscratch1, dst);
+ movl(Address(rscratch1, 0), src);
+ }
+}
+
+void MacroAssembler::mov32(Register dst, AddressLiteral src) {
+ if (reachable(src)) {
+ movl(dst, as_Address(src));
+ } else {
+ lea(rscratch1, src);
+ movl(dst, Address(rscratch1, 0));
+ }
+}
+
+// C++ bool manipulation
+
+void MacroAssembler::movbool(Register dst, Address src) {
+ if(sizeof(bool) == 1)
+ movb(dst, src);
+ else if(sizeof(bool) == 2)
+ movw(dst, src);
+ else if(sizeof(bool) == 4)
+ movl(dst, src);
+ else
+ // unsupported
+ ShouldNotReachHere();
+}
+
+void MacroAssembler::movbool(Address dst, bool boolconst) {
+ if(sizeof(bool) == 1)
+ movb(dst, (int) boolconst);
+ else if(sizeof(bool) == 2)
+ movw(dst, (int) boolconst);
+ else if(sizeof(bool) == 4)
+ movl(dst, (int) boolconst);
+ else
+ // unsupported
+ ShouldNotReachHere();
+}
+
+void MacroAssembler::movbool(Address dst, Register src) {
+ if(sizeof(bool) == 1)
+ movb(dst, src);
+ else if(sizeof(bool) == 2)
+ movw(dst, src);
+ else if(sizeof(bool) == 4)
+ movl(dst, src);
+ else
+ // unsupported
+ ShouldNotReachHere();
+}
+
+void MacroAssembler::movbyte(ArrayAddress dst, int src) {
+ movb(as_Address(dst), src);
+}
+
+void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
+ if (reachable(src)) {
+ if (UseXmmLoadAndClearUpper) {
+ movsd (dst, as_Address(src));
+ } else {
+ movlpd(dst, as_Address(src));
+ }
+ } else {
+ lea(rscratch1, src);
+ if (UseXmmLoadAndClearUpper) {
+ movsd (dst, Address(rscratch1, 0));
+ } else {
+ movlpd(dst, Address(rscratch1, 0));
+ }
+ }
+}
+
+void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
+ if (reachable(src)) {
+ movss(dst, as_Address(src));
+ } else {
+ lea(rscratch1, src);
+ movss(dst, Address(rscratch1, 0));
+ }
+}
+
+void MacroAssembler::movptr(Register dst, Register src) {
+ LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
+}
+
+void MacroAssembler::movptr(Register dst, Address src) {
+ LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
+}
+
+// src should NEVER be a real pointer. Use AddressLiteral for true pointers
+void MacroAssembler::movptr(Register dst, intptr_t src) {
+ LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
+}
+
+void MacroAssembler::movptr(Address dst, Register src) {
+ LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
+}
+
+void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
+ if (reachable(src)) {
+ movss(dst, as_Address(src));
+ } else {
+ lea(rscratch1, src);
+ movss(dst, Address(rscratch1, 0));
+ }
+}
+
+void MacroAssembler::null_check(Register reg, int offset) {
+ if (needs_explicit_null_check(offset)) {
+ // provoke OS NULL exception if reg = NULL by
+ // accessing M[reg] w/o changing any (non-CC) registers
+ // NOTE: cmpl is plenty here to provoke a segv
+ cmpptr(rax, Address(reg, 0));
+ // Note: should probably use testl(rax, Address(reg, 0));
+ // may be shorter code (however, this version of
+ // testl needs to be implemented first)
+ } else {
+ // nothing to do, (later) access of M[reg + offset]
+ // will provoke OS NULL exception if reg = NULL
+ }
+}
+
+void MacroAssembler::os_breakpoint() {
+ // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
+ // (e.g., MSVC can't call ps() otherwise)
+ call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
+}
+
+void MacroAssembler::pop_CPU_state() {
+ pop_FPU_state();
+ pop_IU_state();
+}
+
+void MacroAssembler::pop_FPU_state() {
+ NOT_LP64(frstor(Address(rsp, 0));)
+ LP64_ONLY(fxrstor(Address(rsp, 0));)
+ addptr(rsp, FPUStateSizeInWords * wordSize);
+}
+
+void MacroAssembler::pop_IU_state() {
+ popa();
+ LP64_ONLY(addq(rsp, 8));
+ popf();
+}
+
+// Save Integer and Float state
+// Warning: Stack must be 16 byte aligned (64bit)
+void MacroAssembler::push_CPU_state() {
+ push_IU_state();
+ push_FPU_state();
+}
+
+void MacroAssembler::push_FPU_state() {
+ subptr(rsp, FPUStateSizeInWords * wordSize);
+#ifndef _LP64
+ fnsave(Address(rsp, 0));
+ fwait();
+#else
+ fxsave(Address(rsp, 0));
+#endif // LP64
+}
+
+void MacroAssembler::push_IU_state() {
+ // Push flags first because pusha kills them
+ pushf();
+ // Make sure rsp stays 16-byte aligned
+ LP64_ONLY(subq(rsp, 8));
+ pusha();
+}
+
+void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) {
+ // determine java_thread register
+ if (!java_thread->is_valid()) {
+ java_thread = rdi;
+ get_thread(java_thread);
+ }
+ // we must set sp to zero to clear frame
+ movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), (int32_t)NULL_WORD);
+ if (clear_fp) {
+ movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), (int32_t)NULL_WORD);
+ }
+
+ if (clear_pc)
+ movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), (int32_t)NULL_WORD);
+
+}
+
+void MacroAssembler::restore_rax(Register tmp) {
+ if (tmp == noreg) pop(rax);
+ else if (tmp != rax) mov(rax, tmp);
+}
+
+void MacroAssembler::round_to(Register reg, int modulus) {
+ addptr(reg, modulus - 1);
+ andptr(reg, -modulus);
+}
+
+void MacroAssembler::save_rax(Register tmp) {
+ if (tmp == noreg) push(rax);
+ else if (tmp != rax) mov(tmp, rax);
+}
+
+// Write serialization page so VM thread can do a pseudo remote membar.
+// We use the current thread pointer to calculate a thread specific
+// offset to write to within the page. This minimizes bus traffic
+// due to cache line collision.
+void MacroAssembler::serialize_memory(Register thread, Register tmp) {
+ movl(tmp, thread);
+ shrl(tmp, os::get_serialize_page_shift_count());
+ andl(tmp, (os::vm_page_size() - sizeof(int)));
+
+ Address index(noreg, tmp, Address::times_1);
+ ExternalAddress page(os::get_memory_serialize_page());
+
+ movptr(ArrayAddress(page, index), tmp);
+}
+
+// Calls to C land
+//
+// When entering C land, the rbp, & rsp of the last Java frame have to be recorded
+// in the (thread-local) JavaThread object. When leaving C land, the last Java fp
+// has to be reset to 0. This is required to allow proper stack traversal.
+void MacroAssembler::set_last_Java_frame(Register java_thread,
+ Register last_java_sp,
+ Register last_java_fp,
+ address last_java_pc) {
+ // determine java_thread register
+ if (!java_thread->is_valid()) {
+ java_thread = rdi;
+ get_thread(java_thread);
+ }
+ // determine last_java_sp register
+ if (!last_java_sp->is_valid()) {
+ last_java_sp = rsp;
+ }
+
+ // last_java_fp is optional
+
+ if (last_java_fp->is_valid()) {
+ movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
+ }
+
+ // last_java_pc is optional
+
+ if (last_java_pc != NULL) {
+ lea(Address(java_thread,
+ JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
+ InternalAddress(last_java_pc));
+
+ }
+ movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
+}
+
+void MacroAssembler::shlptr(Register dst, int imm8) {
+ LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
+}
+
+void MacroAssembler::shrptr(Register dst, int imm8) {
+ LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
+}
+
+void MacroAssembler::sign_extend_byte(Register reg) {
+ if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
+ movsbl(reg, reg); // movsxb
+ } else {
+ shll(reg, 24);
+ sarl(reg, 24);
+ }
+}
+
+void MacroAssembler::sign_extend_short(Register reg) {
+ if (LP64_ONLY(true ||) VM_Version::is_P6()) {
+ movswl(reg, reg); // movsxw
+ } else {
+ shll(reg, 16);
+ sarl(reg, 16);
+ }
+}
+
+void MacroAssembler::store_check(Register obj) {
+ // Does a store check for the oop in register obj. The content of
+ // register obj is destroyed afterwards.
+ store_check_part_1(obj);
+ store_check_part_2(obj);
+}
+
+void MacroAssembler::store_check(Register obj, Address dst) {
+ store_check(obj);
+}
+
+
+// split the store check operation so that other instructions can be scheduled inbetween
+void MacroAssembler::store_check_part_1(Register obj) {
+ BarrierSet* bs = Universe::heap()->barrier_set();
+ assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
+ shrptr(obj, CardTableModRefBS::card_shift);
+}
+
+void MacroAssembler::store_check_part_2(Register obj) {
+ BarrierSet* bs = Universe::heap()->barrier_set();
+ assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
+ CardTableModRefBS* ct = (CardTableModRefBS*)bs;
+ assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
+
+ // The calculation for byte_map_base is as follows:
+ // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift);
+ // So this essentially converts an address to a displacement and
+ // it will never need to be relocated. On 64bit however the value may be too
+ // large for a 32bit displacement
+
+ intptr_t disp = (intptr_t) ct->byte_map_base;
+ if (is_simm32(disp)) {
+ Address cardtable(noreg, obj, Address::times_1, disp);
+ movb(cardtable, 0);
+ } else {
+ // By doing it as an ExternalAddress disp could be converted to a rip-relative
+ // displacement and done in a single instruction given favorable mapping and
+ // a smarter version of as_Address. Worst case it is two instructions which
+ // is no worse off then loading disp into a register and doing as a simple
+ // Address() as above.
+ // We can't do as ExternalAddress as the only style since if disp == 0 we'll
+ // assert since NULL isn't acceptable in a reloci (see 6644928). In any case
+ // in some cases we'll get a single instruction version.
+
+ ExternalAddress cardtable((address)disp);
+ Address index(noreg, obj, Address::times_1);
+ movb(as_Address(ArrayAddress(cardtable, index)), 0);
+ }
+}
+
+void MacroAssembler::subptr(Register dst, int32_t imm32) {
+ LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
+}
+
+void MacroAssembler::subptr(Register dst, Register src) {
+ LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
+}
+
+void MacroAssembler::test32(Register src1, AddressLiteral src2) {
+ // src2 must be rval
+
+ if (reachable(src2)) {
+ testl(src1, as_Address(src2));
+ } else {
+ lea(rscratch1, src2);
+ testl(src1, Address(rscratch1, 0));
+ }
+}
+
+// C++ bool manipulation
+void MacroAssembler::testbool(Register dst) {
+ if(sizeof(bool) == 1)
+ testb(dst, 0xff);
+ else if(sizeof(bool) == 2) {
+ // testw implementation needed for two byte bools
+ ShouldNotReachHere();
+ } else if(sizeof(bool) == 4)
+ testl(dst, dst);
+ else
+ // unsupported
+ ShouldNotReachHere();
+}
+
+void MacroAssembler::testptr(Register dst, Register src) {
+ LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
+}
+
+// Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
+void MacroAssembler::tlab_allocate(Register obj,
+ Register var_size_in_bytes,
+ int con_size_in_bytes,
+ Register t1,
+ Register t2,
+ Label& slow_case) {
+ assert_different_registers(obj, t1, t2);
+ assert_different_registers(obj, var_size_in_bytes, t1);
+ Register end = t2;
+ Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread);
+
+ verify_tlab();
+
+ NOT_LP64(get_thread(thread));
+
+ movptr(obj, Address(thread, JavaThread::tlab_top_offset()));
+ if (var_size_in_bytes == noreg) {
+ lea(end, Address(obj, con_size_in_bytes));
+ } else {
+ lea(end, Address(obj, var_size_in_bytes, Address::times_1));
+ }
+ cmpptr(end, Address(thread, JavaThread::tlab_end_offset()));
+ jcc(Assembler::above, slow_case);
+
+ // update the tlab top pointer
+ movptr(Address(thread, JavaThread::tlab_top_offset()), end);
+
+ // recover var_size_in_bytes if necessary
+ if (var_size_in_bytes == end) {
+ subptr(var_size_in_bytes, obj);
+ }
+ verify_tlab();
+}
+
+// Preserves rbx, and rdx.
+void MacroAssembler::tlab_refill(Label& retry,
+ Label& try_eden,
+ Label& slow_case) {
+ Register top = rax;
+ Register t1 = rcx;
+ Register t2 = rsi;
+ Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread);
+ assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx);
+ Label do_refill, discard_tlab;
+
+ if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
+ // No allocation in the shared eden.
+ jmp(slow_case);
+ }
+
+ NOT_LP64(get_thread(thread_reg));
+
+ movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
+ movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
+
+ // calculate amount of free space
+ subptr(t1, top);
+ shrptr(t1, LogHeapWordSize);
+
+ // Retain tlab and allocate object in shared space if
+ // the amount free in the tlab is too large to discard.
+ cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
+ jcc(Assembler::lessEqual, discard_tlab);
+
+ // Retain
+ // %%% yuck as movptr...
+ movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment());
+ addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2);
+ if (TLABStats) {
+ // increment number of slow_allocations
+ addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1);
+ }
+ jmp(try_eden);
+
+ bind(discard_tlab);
+ if (TLABStats) {
+ // increment number of refills
+ addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1);
+ // accumulate wastage -- t1 is amount free in tlab
+ addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1);
+ }
+
+ // if tlab is currently allocated (top or end != null) then
+ // fill [top, end + alignment_reserve) with array object
+ testptr (top, top);
+ jcc(Assembler::zero, do_refill);
+
+ // set up the mark word
+ movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2));
+ // set the length to the remaining space
+ subptr(t1, typeArrayOopDesc::header_size(T_INT));
+ addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve());
+ shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint)));
+ movptr(Address(top, arrayOopDesc::length_offset_in_bytes()), t1);
+ // set klass to intArrayKlass
+ // dubious reloc why not an oop reloc?
+ movptr(t1, ExternalAddress((address) Universe::intArrayKlassObj_addr()));
+ // store klass last. concurrent gcs assumes klass length is valid if
+ // klass field is not null.
+ store_klass(top, t1);
+
+ // refill the tlab with an eden allocation
+ bind(do_refill);
+ movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
+ shlptr(t1, LogHeapWordSize);
+ // add object_size ??
+ eden_allocate(top, t1, 0, t2, slow_case);
+
+ // Check that t1 was preserved in eden_allocate.
+#ifdef ASSERT
+ if (UseTLAB) {
+ Label ok;
+ Register tsize = rsi;
+ assert_different_registers(tsize, thread_reg, t1);
+ push(tsize);
+ movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
+ shlptr(tsize, LogHeapWordSize);
+ cmpptr(t1, tsize);
+ jcc(Assembler::equal, ok);
+ stop("assert(t1 != tlab size)");
+ should_not_reach_here();
+
+ bind(ok);
+ pop(tsize);
+ }
+#endif
+ movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top);
+ movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top);
+ addptr(top, t1);
+ subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
+ movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top);
+ verify_tlab();
+ jmp(retry);
+}
+
+static const double pi_4 = 0.7853981633974483;
+
+void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) {
+ // A hand-coded argument reduction for values in fabs(pi/4, pi/2)
+ // was attempted in this code; unfortunately it appears that the
+ // switch to 80-bit precision and back causes this to be
+ // unprofitable compared with simply performing a runtime call if
+ // the argument is out of the (-pi/4, pi/4) range.
+
+ Register tmp = noreg;
+ if (!VM_Version::supports_cmov()) {
+ // fcmp needs a temporary so preserve rbx,
+ tmp = rbx;
+ push(tmp);
+ }
+
+ Label slow_case, done;
+
+ // x ?<= pi/4
+ fld_d(ExternalAddress((address)&pi_4));
+ fld_s(1); // Stack: X PI/4 X
+ fabs(); // Stack: |X| PI/4 X
+ fcmp(tmp);
+ jcc(Assembler::above, slow_case);
+
+ // fastest case: -pi/4 <= x <= pi/4
+ switch(trig) {
+ case 's':
+ fsin();
+ break;
+ case 'c':
+ fcos();
+ break;
+ case 't':
+ ftan();
+ break;
+ default:
+ assert(false, "bad intrinsic");
+ break;
+ }
+ jmp(done);
+
+ // slow case: runtime call
+ bind(slow_case);
+ // Preserve registers across runtime call
+ pusha();
+ int incoming_argument_and_return_value_offset = -1;
+ if (num_fpu_regs_in_use > 1) {
+ // Must preserve all other FPU regs (could alternatively convert
+ // SharedRuntime::dsin and dcos into assembly routines known not to trash
+ // FPU state, but can not trust C compiler)
+ NEEDS_CLEANUP;
+ // NOTE that in this case we also push the incoming argument to
+ // the stack and restore it later; we also use this stack slot to
+ // hold the return value from dsin or dcos.
+ for (int i = 0; i < num_fpu_regs_in_use; i++) {
+ subptr(rsp, sizeof(jdouble));
+ fstp_d(Address(rsp, 0));
+ }
+ incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1);
+ fld_d(Address(rsp, incoming_argument_and_return_value_offset));
+ }
+ subptr(rsp, sizeof(jdouble));
+ fstp_d(Address(rsp, 0));
+#ifdef _LP64
+ movdbl(xmm0, Address(rsp, 0));
+#endif // _LP64
+
+ // NOTE: we must not use call_VM_leaf here because that requires a
+ // complete interpreter frame in debug mode -- same bug as 4387334
+ // MacroAssembler::call_VM_leaf_base is perfectly safe and will
+ // do proper 64bit abi
+
+ NEEDS_CLEANUP;
+ // Need to add stack banging before this runtime call if it needs to
+ // be taken; however, there is no generic stack banging routine at
+ // the MacroAssembler level
+ switch(trig) {
+ case 's':
+ {
+ MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 0);
+ }
+ break;
+ case 'c':
+ {
+ MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 0);
+ }
+ break;
+ case 't':
+ {
+ MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 0);
+ }
+ break;
+ default:
+ assert(false, "bad intrinsic");
+ break;
+ }
+#ifdef _LP64
+ movsd(Address(rsp, 0), xmm0);
+ fld_d(Address(rsp, 0));
+#endif // _LP64
+ addptr(rsp, sizeof(jdouble));
+ if (num_fpu_regs_in_use > 1) {
+ // Must save return value to stack and then restore entire FPU stack
+ fstp_d(Address(rsp, incoming_argument_and_return_value_offset));
+ for (int i = 0; i < num_fpu_regs_in_use; i++) {
+ fld_d(Address(rsp, 0));
+ addptr(rsp, sizeof(jdouble));
+ }
+ }
+ popa();
+
+ // Come here with result in F-TOS
+ bind(done);
+
+ if (tmp != noreg) {
+ pop(tmp);
+ }
+}
+
+
+void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
+ ucomisd(dst, as_Address(src));
+}
+
+void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
+ ucomiss(dst, as_Address(src));
+}
+
+void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
+ if (reachable(src)) {
+ xorpd(dst, as_Address(src));
+ } else {
+ lea(rscratch1, src);
+ xorpd(dst, Address(rscratch1, 0));
+ }
+}
+
+void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
+ if (reachable(src)) {
+ xorps(dst, as_Address(src));
+ } else {
+ lea(rscratch1, src);
+ xorps(dst, Address(rscratch1, 0));
+ }
+}
+
+void MacroAssembler::verify_oop(Register reg, const char* s) {
+ if (!VerifyOops) return;
+
+ // Pass register number to verify_oop_subroutine
+ char* b = new char[strlen(s) + 50];
+ sprintf(b, "verify_oop: %s: %s", reg->name(), s);
+ push(rax); // save rax,
+ push(reg); // pass register argument
+ ExternalAddress buffer((address) b);
+ // avoid using pushptr, as it modifies scratch registers
+ // and our contract is not to modify anything
+ movptr(rax, buffer.addr());
+ push(rax);
+ // call indirectly to solve generation ordering problem
+ movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
+ call(rax);
+}
+
+
+void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
+ if (!VerifyOops) return;
+
+ // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
+ // Pass register number to verify_oop_subroutine
+ char* b = new char[strlen(s) + 50];
+ sprintf(b, "verify_oop_addr: %s", s);
+
+ push(rax); // save rax,
+ // addr may contain rsp so we will have to adjust it based on the push
+ // we just did
+ // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
+ // stores rax into addr which is backwards of what was intended.
+ if (addr.uses(rsp)) {
+ lea(rax, addr);
+ pushptr(Address(rax, BytesPerWord));
+ } else {
+ pushptr(addr);
+ }
+
+ ExternalAddress buffer((address) b);
+ // pass msg argument
+ // avoid using pushptr, as it modifies scratch registers
+ // and our contract is not to modify anything
+ movptr(rax, buffer.addr());
+ push(rax);
+
+ // call indirectly to solve generation ordering problem
+ movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
+ call(rax);
+ // Caller pops the arguments and restores rax, from the stack
+}
+
+void MacroAssembler::verify_tlab() {
+#ifdef ASSERT
+ if (UseTLAB && VerifyOops) {
+ Label next, ok;
+ Register t1 = rsi;
+ Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
+
+ push(t1);
+ NOT_LP64(push(thread_reg));
+ NOT_LP64(get_thread(thread_reg));
+
+ movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
+ cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
+ jcc(Assembler::aboveEqual, next);
+ stop("assert(top >= start)");
+ should_not_reach_here();
+
+ bind(next);
+ movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
+ cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
+ jcc(Assembler::aboveEqual, ok);
+ stop("assert(top <= end)");
+ should_not_reach_here();
+
+ bind(ok);
+ NOT_LP64(pop(thread_reg));
+ pop(t1);
+ }
+#endif
+}
+
+class ControlWord {
+ public:
+ int32_t _value;
+
+ int rounding_control() const { return (_value >> 10) & 3 ; }
+ int precision_control() const { return (_value >> 8) & 3 ; }
+ bool precision() const { return ((_value >> 5) & 1) != 0; }
+ bool underflow() const { return ((_value >> 4) & 1) != 0; }
+ bool overflow() const { return ((_value >> 3) & 1) != 0; }
+ bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
+ bool denormalized() const { return ((_value >> 1) & 1) != 0; }
+ bool invalid() const { return ((_value >> 0) & 1) != 0; }
+
+ void print() const {
+ // rounding control
+ const char* rc;
+ switch (rounding_control()) {
+ case 0: rc = "round near"; break;
+ case 1: rc = "round down"; break;
+ case 2: rc = "round up "; break;
+ case 3: rc = "chop "; break;
+ };
+ // precision control
+ const char* pc;
+ switch (precision_control()) {
+ case 0: pc = "24 bits "; break;
+ case 1: pc = "reserved"; break;
+ case 2: pc = "53 bits "; break;
+ case 3: pc = "64 bits "; break;
+ };
+ // flags
+ char f[9];
+ f[0] = ' ';
+ f[1] = ' ';
+ f[2] = (precision ()) ? 'P' : 'p';
+ f[3] = (underflow ()) ? 'U' : 'u';
+ f[4] = (overflow ()) ? 'O' : 'o';
+ f[5] = (zero_divide ()) ? 'Z' : 'z';
+ f[6] = (denormalized()) ? 'D' : 'd';
+ f[7] = (invalid ()) ? 'I' : 'i';
+ f[8] = '\x0';
+ // output
+ printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
+ }
+
+};
+
+class StatusWord {
+ public:
+ int32_t _value;
+
+ bool busy() const { return ((_value >> 15) & 1) != 0; }
+ bool C3() const { return ((_value >> 14) & 1) != 0; }
+ bool C2() const { return ((_value >> 10) & 1) != 0; }
+ bool C1() const { return ((_value >> 9) & 1) != 0; }
+ bool C0() const { return ((_value >> 8) & 1) != 0; }
+ int top() const { return (_value >> 11) & 7 ; }
+ bool error_status() const { return ((_value >> 7) & 1) != 0; }
+ bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
+ bool precision() const { return ((_value >> 5) & 1) != 0; }
+ bool underflow() const { return ((_value >> 4) & 1) != 0; }
+ bool overflow() const { return ((_value >> 3) & 1) != 0; }
+ bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
+ bool denormalized() const { return ((_value >> 1) & 1) != 0; }
+ bool invalid() const { return ((_value >> 0) & 1) != 0; }
+
+ void print() const {
+ // condition codes
+ char c[5];
+ c[0] = (C3()) ? '3' : '-';
+ c[1] = (C2()) ? '2' : '-';
+ c[2] = (C1()) ? '1' : '-';
+ c[3] = (C0()) ? '0' : '-';
+ c[4] = '\x0';
+ // flags
+ char f[9];
+ f[0] = (error_status()) ? 'E' : '-';
+ f[1] = (stack_fault ()) ? 'S' : '-';
+ f[2] = (precision ()) ? 'P' : '-';
+ f[3] = (underflow ()) ? 'U' : '-';
+ f[4] = (overflow ()) ? 'O' : '-';
+ f[5] = (zero_divide ()) ? 'Z' : '-';
+ f[6] = (denormalized()) ? 'D' : '-';
+ f[7] = (invalid ()) ? 'I' : '-';
+ f[8] = '\x0';
+ // output
+ printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
+ }
+
+};
+
+class TagWord {
+ public:
+ int32_t _value;
+
+ int tag_at(int i) const { return (_value >> (i*2)) & 3; }
+
+ void print() const {
+ printf("%04x", _value & 0xFFFF);
+ }
+
+};
+
+class FPU_Register {
+ public:
+ int32_t _m0;
+ int32_t _m1;
+ int16_t _ex;
+
+ bool is_indefinite() const {
+ return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
+ }
+
+ void print() const {
+ char sign = (_ex < 0) ? '-' : '+';
+ const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
+ printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
+ };
+
+};
+
+class FPU_State {
+ public:
+ enum {
+ register_size = 10,
+ number_of_registers = 8,
+ register_mask = 7
+ };
+
+ ControlWord _control_word;
+ StatusWord _status_word;
+ TagWord _tag_word;
+ int32_t _error_offset;
+ int32_t _error_selector;
+ int32_t _data_offset;
+ int32_t _data_selector;
+ int8_t _register[register_size * number_of_registers];
+
+ int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
+ FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
+
+ const char* tag_as_string(int tag) const {
+ switch (tag) {
+ case 0: return "valid";
+ case 1: return "zero";
+ case 2: return "special";
+ case 3: return "empty";
+ }
+ ShouldNotReachHere()
+ return NULL;
+ }
+
+ void print() const {
+ // print computation registers
+ { int t = _status_word.top();
+ for (int i = 0; i < number_of_registers; i++) {
+ int j = (i - t) & register_mask;
+ printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
+ st(j)->print();
+ printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
+ }
+ }
+ printf("\n");
+ // print control registers
+ printf("ctrl = "); _control_word.print(); printf("\n");
+ printf("stat = "); _status_word .print(); printf("\n");
+ printf("tags = "); _tag_word .print(); printf("\n");
+ }
+
+};
+
+class Flag_Register {
+ public:
+ int32_t _value;
+
+ bool overflow() const { return ((_value >> 11) & 1) != 0; }
+ bool direction() const { return ((_value >> 10) & 1) != 0; }
+ bool sign() const { return ((_value >> 7) & 1) != 0; }
+ bool zero() const { return ((_value >> 6) & 1) != 0; }
+ bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
+ bool parity() const { return ((_value >> 2) & 1) != 0; }
+ bool carry() const { return ((_value >> 0) & 1) != 0; }
+
+ void print() const {
+ // flags
+ char f[8];
+ f[0] = (overflow ()) ? 'O' : '-';
+ f[1] = (direction ()) ? 'D' : '-';
+ f[2] = (sign ()) ? 'S' : '-';
+ f[3] = (zero ()) ? 'Z' : '-';
+ f[4] = (auxiliary_carry()) ? 'A' : '-';
+ f[5] = (parity ()) ? 'P' : '-';
+ f[6] = (carry ()) ? 'C' : '-';
+ f[7] = '\x0';
+ // output
+ printf("%08x flags = %s", _value, f);
+ }
+
+};
+
+class IU_Register {
+ public:
+ int32_t _value;
+
+ void print() const {
+ printf("%08x %11d", _value, _value);
+ }
+
+};
+
+class IU_State {
+ public:
+ Flag_Register _eflags;
+ IU_Register _rdi;
+ IU_Register _rsi;
+ IU_Register _rbp;
+ IU_Register _rsp;
+ IU_Register _rbx;
+ IU_Register _rdx;
+ IU_Register _rcx;
+ IU_Register _rax;
+
+ void print() const {
+ // computation registers
+ printf("rax, = "); _rax.print(); printf("\n");
+ printf("rbx, = "); _rbx.print(); printf("\n");
+ printf("rcx = "); _rcx.print(); printf("\n");
+ printf("rdx = "); _rdx.print(); printf("\n");
+ printf("rdi = "); _rdi.print(); printf("\n");
+ printf("rsi = "); _rsi.print(); printf("\n");
+ printf("rbp, = "); _rbp.print(); printf("\n");
+ printf("rsp = "); _rsp.print(); printf("\n");
+ printf("\n");
+ // control registers
+ printf("flgs = "); _eflags.print(); printf("\n");
+ }
+};
+
+
+class CPU_State {
+ public:
+ FPU_State _fpu_state;
+ IU_State _iu_state;
+
+ void print() const {
+ printf("--------------------------------------------------\n");
+ _iu_state .print();
+ printf("\n");
+ _fpu_state.print();
+ printf("--------------------------------------------------\n");
+ }
+
+};
+
+
+static void _print_CPU_state(CPU_State* state) {
+ state->print();
+};
+
+
+void MacroAssembler::print_CPU_state() {
+ push_CPU_state();
+ push(rsp); // pass CPU state
+ call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
+ addptr(rsp, wordSize); // discard argument
+ pop_CPU_state();
+}
+
+
+static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
+ static int counter = 0;
+ FPU_State* fs = &state->_fpu_state;
+ counter++;
+ // For leaf calls, only verify that the top few elements remain empty.
+ // We only need 1 empty at the top for C2 code.
+ if( stack_depth < 0 ) {
+ if( fs->tag_for_st(7) != 3 ) {
+ printf("FPR7 not empty\n");
+ state->print();
+ assert(false, "error");
+ return false;
+ }
+ return true; // All other stack states do not matter
+ }
+
+ assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
+ "bad FPU control word");
+
+ // compute stack depth
+ int i = 0;
+ while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
+ int d = i;
+ while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
+ // verify findings
+ if (i != FPU_State::number_of_registers) {
+ // stack not contiguous
+ printf("%s: stack not contiguous at ST%d\n", s, i);
+ state->print();
+ assert(false, "error");
+ return false;
+ }
+ // check if computed stack depth corresponds to expected stack depth
+ if (stack_depth < 0) {
+ // expected stack depth is -stack_depth or less
+ if (d > -stack_depth) {
+ // too many elements on the stack
+ printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
+ state->print();
+ assert(false, "error");
+ return false;
+ }
+ } else {
+ // expected stack depth is stack_depth
+ if (d != stack_depth) {
+ // wrong stack depth
+ printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
+ state->print();
+ assert(false, "error");
+ return false;
+ }
+ }
+ // everything is cool
+ return true;
+}
+
+
+void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
+ if (!VerifyFPU) return;
+ push_CPU_state();
+ push(rsp); // pass CPU state
+ ExternalAddress msg((address) s);
+ // pass message string s
+ pushptr(msg.addr());
+ push(stack_depth); // pass stack depth
+ call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
+ addptr(rsp, 3 * wordSize); // discard arguments
+ // check for error
+ { Label L;
+ testl(rax, rax);
+ jcc(Assembler::notZero, L);
+ int3(); // break if error condition
+ bind(L);
+ }
+ pop_CPU_state();
+}
void MacroAssembler::load_klass(Register dst, Register src) {
+#ifdef _LP64
if (UseCompressedOops) {
movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
decode_heap_oop_not_null(dst);
- } else {
- movq(dst, Address(src, oopDesc::klass_offset_in_bytes()));
- }
+ } else
+#endif
+ movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
}
void MacroAssembler::load_prototype_header(Register dst, Register src) {
+#ifdef _LP64
if (UseCompressedOops) {
movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
movq(dst, Address(r12_heapbase, dst, Address::times_8, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
- } else {
- movq(dst, Address(src, oopDesc::klass_offset_in_bytes()));
- movq(dst, Address(dst, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
- }
+ } else
+#endif
+ {
+ movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
+ movptr(dst, Address(dst, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
+ }
}
void MacroAssembler::store_klass(Register dst, Register src) {
+#ifdef _LP64
if (UseCompressedOops) {
encode_heap_oop_not_null(src);
movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
- } else {
- movq(Address(dst, oopDesc::klass_offset_in_bytes()), src);
- }
+ } else
+#endif
+ movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
}
+#ifdef _LP64
void MacroAssembler::store_klass_gap(Register dst, Register src) {
if (UseCompressedOops) {
// Store to klass gap in destination
@@ -5206,12 +7357,12 @@ void MacroAssembler::encode_heap_oop(Register r) {
#ifdef ASSERT
if (CheckCompressedOops) {
Label ok;
- pushq(rscratch1); // cmpptr trashes rscratch1
+ push(rscratch1); // cmpptr trashes rscratch1
cmpptr(r12_heapbase, ExternalAddress((address)Universe::heap_base_addr()));
jcc(Assembler::equal, ok);
stop("MacroAssembler::encode_heap_oop: heap base corrupted?");
bind(ok);
- popq(rscratch1);
+ pop(rscratch1);
}
#endif
verify_oop(r, "broken oop in encode_heap_oop");
@@ -5261,13 +7412,13 @@ void MacroAssembler::decode_heap_oop(Register r) {
#ifdef ASSERT
if (CheckCompressedOops) {
Label ok;
- pushq(rscratch1);
+ push(rscratch1);
cmpptr(r12_heapbase,
ExternalAddress((address)Universe::heap_base_addr()));
jcc(Assembler::equal, ok);
stop("MacroAssembler::decode_heap_oop: heap base corrupted?");
bind(ok);
- popq(rscratch1);
+ pop(rscratch1);
}
#endif
@@ -5307,14 +7458,15 @@ void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
int oop_index = oop_recorder()->find_index(obj);
RelocationHolder rspec = oop_Relocation::spec(oop_index);
-
- // movl dst,obj
- InstructionMark im(this);
- int encode = prefix_and_encode(dst->encoding());
- emit_byte(0xB8 | encode);
- emit_data(oop_index, rspec, narrow_oop_operand);
+ mov_literal32(dst, oop_index, rspec, narrow_oop_operand);
}
+void MacroAssembler::reinit_heapbase() {
+ if (UseCompressedOops) {
+ movptr(r12_heapbase, ExternalAddress((address)Universe::heap_base_addr()));
+ }
+}
+#endif // _LP64
Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
switch (cond) {
@@ -5339,23 +7491,6 @@ Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond)
ShouldNotReachHere(); return Assembler::overflow;
}
-
-void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
- Condition negated_cond = negate_condition(cond);
- Label L;
- jcc(negated_cond, L);
- atomic_incl(counter_addr);
- bind(L);
-}
-
-void MacroAssembler::atomic_incl(AddressLiteral counter_addr) {
- pushfq();
- if (os::is_MP())
- lock();
- incrementl(counter_addr);
- popfq();
-}
-
SkipIfEqual::SkipIfEqual(
MacroAssembler* masm, const bool* flag_addr, bool value) {
_masm = masm;
@@ -5366,28 +7501,3 @@ SkipIfEqual::SkipIfEqual(
SkipIfEqual::~SkipIfEqual() {
_masm->bind(_label);
}
-
-void MacroAssembler::bang_stack_size(Register size, Register tmp) {
- movq(tmp, rsp);
- // Bang stack for total size given plus shadow page size.
- // Bang one page at a time because large size can bang beyond yellow and
- // red zones.
- Label loop;
- bind(loop);
- movl(Address(tmp, (-os::vm_page_size())), size );
- subq(tmp, os::vm_page_size());
- subl(size, os::vm_page_size());
- jcc(Assembler::greater, loop);
-
- // Bang down shadow pages too.
- // The -1 because we already subtracted 1 page.
- for (int i = 0; i< StackShadowPages-1; i++) {
- movq(Address(tmp, (-i*os::vm_page_size())), size );
- }
-}
-
-void MacroAssembler::reinit_heapbase() {
- if (UseCompressedOops) {
- movptr(r12_heapbase, ExternalAddress((address)Universe::heap_base_addr()));
- }
-}
diff --git a/hotspot/src/cpu/x86/vm/assembler_x86_32.hpp b/hotspot/src/cpu/x86/vm/assembler_x86.hpp
similarity index 63%
rename from hotspot/src/cpu/x86/vm/assembler_x86_32.hpp
rename to hotspot/src/cpu/x86/vm/assembler_x86.hpp
index 9588449955c..d9637ffc9e2 100644
--- a/hotspot/src/cpu/x86/vm/assembler_x86_32.hpp
+++ b/hotspot/src/cpu/x86/vm/assembler_x86.hpp
@@ -58,10 +58,10 @@ REGISTER_DECLARATION(Register, c_rarg1, rdx);
REGISTER_DECLARATION(Register, c_rarg2, r8);
REGISTER_DECLARATION(Register, c_rarg3, r9);
-REGISTER_DECLARATION(FloatRegister, c_farg0, xmm0);
-REGISTER_DECLARATION(FloatRegister, c_farg1, xmm1);
-REGISTER_DECLARATION(FloatRegister, c_farg2, xmm2);
-REGISTER_DECLARATION(FloatRegister, c_farg3, xmm3);
+REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
+REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
+REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
+REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
#else
@@ -72,14 +72,14 @@ REGISTER_DECLARATION(Register, c_rarg3, rcx);
REGISTER_DECLARATION(Register, c_rarg4, r8);
REGISTER_DECLARATION(Register, c_rarg5, r9);
-REGISTER_DECLARATION(FloatRegister, c_farg0, xmm0);
-REGISTER_DECLARATION(FloatRegister, c_farg1, xmm1);
-REGISTER_DECLARATION(FloatRegister, c_farg2, xmm2);
-REGISTER_DECLARATION(FloatRegister, c_farg3, xmm3);
-REGISTER_DECLARATION(FloatRegister, c_farg4, xmm4);
-REGISTER_DECLARATION(FloatRegister, c_farg5, xmm5);
-REGISTER_DECLARATION(FloatRegister, c_farg6, xmm6);
-REGISTER_DECLARATION(FloatRegister, c_farg7, xmm7);
+REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
+REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
+REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
+REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
+REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);
+REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);
+REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);
+REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);
#endif // _WIN64
@@ -112,20 +112,27 @@ REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
#endif /* _WIN64 */
REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
-REGISTER_DECLARATION(FloatRegister, j_farg0, xmm0);
-REGISTER_DECLARATION(FloatRegister, j_farg1, xmm1);
-REGISTER_DECLARATION(FloatRegister, j_farg2, xmm2);
-REGISTER_DECLARATION(FloatRegister, j_farg3, xmm3);
-REGISTER_DECLARATION(FloatRegister, j_farg4, xmm4);
-REGISTER_DECLARATION(FloatRegister, j_farg5, xmm5);
-REGISTER_DECLARATION(FloatRegister, j_farg6, xmm6);
-REGISTER_DECLARATION(FloatRegister, j_farg7, xmm7);
+REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);
+REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);
+REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);
+REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);
+REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
+REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
+REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
+REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
REGISTER_DECLARATION(Register, rscratch1, r10); // volatile
REGISTER_DECLARATION(Register, rscratch2, r11); // volatile
+REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
+#else
+// rscratch1 will apear in 32bit code that is dead but of course must compile
+// Using noreg ensures if the dead code is incorrectly live and executed it
+// will cause an assertion failure
+#define rscratch1 noreg
+
#endif // _LP64
// Address is an abstraction used to represent a memory location
@@ -143,7 +150,8 @@ class Address VALUE_OBJ_CLASS_SPEC {
times_1 = 0,
times_2 = 1,
times_4 = 2,
- times_8 = 3
+ times_8 = 3,
+ times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
};
private:
@@ -153,12 +161,15 @@ class Address VALUE_OBJ_CLASS_SPEC {
int _disp;
RelocationHolder _rspec;
- // Easily misused constructor make them private
-#ifndef _LP64
- Address(address loc, RelocationHolder spec);
-#endif // _LP64
+ // Easily misused constructors make them private
+ // %%% can we make these go away?
+ NOT_LP64(Address(address loc, RelocationHolder spec);)
+ Address(int disp, address loc, relocInfo::relocType rtype);
+ Address(int disp, address loc, RelocationHolder spec);
public:
+
+ int disp() { return _disp; }
// creation
Address()
: _base(noreg),
@@ -358,11 +369,7 @@ class ArrayAddress VALUE_OBJ_CLASS_SPEC {
};
-#ifndef _LP64
-const int FPUStateSizeInWords = 27;
-#else
-const int FPUStateSizeInWords = 512 / wordSize;
-#endif // _LP64
+const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize);
// The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
// level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
@@ -371,62 +378,7 @@ const int FPUStateSizeInWords = 512 / wordSize;
class Assembler : public AbstractAssembler {
friend class AbstractAssembler; // for the non-virtual hack
friend class LIR_Assembler; // as_Address()
-
- protected:
- #ifdef ASSERT
- void check_relocation(RelocationHolder const& rspec, int format);
- #endif
-
- inline void emit_long64(jlong x);
-
- void emit_data(jint data, relocInfo::relocType rtype, int format /* = 0 */);
- void emit_data(jint data, RelocationHolder const& rspec, int format /* = 0 */);
- void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
- void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
-
- // Helper functions for groups of instructions
- void emit_arith_b(int op1, int op2, Register dst, int imm8);
-
- void emit_arith(int op1, int op2, Register dst, int imm32);
- // only x86??
- void emit_arith(int op1, int op2, Register dst, jobject obj);
- void emit_arith(int op1, int op2, Register dst, Register src);
-
- void emit_operand(Register reg,
- Register base, Register index, Address::ScaleFactor scale,
- int disp,
- RelocationHolder const& rspec);
- void emit_operand(Register reg, Address adr);
-
- // Immediate-to-memory forms
- void emit_arith_operand(int op1, Register rm, Address adr, int imm32);
-
- void emit_farith(int b1, int b2, int i);
-
- // macroassembler?? QQQ
- bool reachable(AddressLiteral adr) { return true; }
-
- // These are all easily abused and hence protected
-
- // Make these disappear in 64bit mode since they would never be correct
-#ifndef _LP64
- void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec);
- void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec);
-
- void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec);
- void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec);
-
- void push_literal32(int32_t imm32, RelocationHolder const& rspec);
-#endif // _LP64
-
- // These are unique in that we are ensured by the caller that the 32bit
- // relative in these instructions will always be able to reach the potentially
- // 64bit address described by entry. Since they can take a 64bit address they
- // don't have the 32 suffix like the other instructions in this class.
-
- void call_literal(address entry, RelocationHolder const& rspec);
- void jmp_literal(address entry, RelocationHolder const& rspec);
-
+ friend class StubGenerator;
public:
enum Condition { // The x86 condition codes used for conditional jumps/moves.
@@ -484,12 +436,177 @@ class Assembler : public AbstractAssembler {
enum WhichOperand {
// input to locate_operand, and format code for relocations
- imm32_operand = 0, // embedded 32-bit immediate operand
+ imm_operand = 0, // embedded 32-bit|64-bit immediate operand
disp32_operand = 1, // embedded 32-bit displacement or address
call32_operand = 2, // embedded 32-bit self-relative displacement
+#ifndef _LP64
_WhichOperand_limit = 3
+#else
+ narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop
+ _WhichOperand_limit = 4
+#endif
};
+
+
+ // NOTE: The general philopsophy of the declarations here is that 64bit versions
+ // of instructions are freely declared without the need for wrapping them an ifdef.
+ // (Some dangerous instructions are ifdef's out of inappropriate jvm's.)
+ // In the .cpp file the implementations are wrapped so that they are dropped out
+ // of the resulting jvm. This is done mostly to keep the footprint of KERNEL
+ // to the size it was prior to merging up the 32bit and 64bit assemblers.
+ //
+ // This does mean you'll get a linker/runtime error if you use a 64bit only instruction
+ // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
+
+private:
+
+
+ // 64bit prefixes
+ int prefix_and_encode(int reg_enc, bool byteinst = false);
+ int prefixq_and_encode(int reg_enc);
+
+ int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false);
+ int prefixq_and_encode(int dst_enc, int src_enc);
+
+ void prefix(Register reg);
+ void prefix(Address adr);
+ void prefixq(Address adr);
+
+ void prefix(Address adr, Register reg, bool byteinst = false);
+ void prefixq(Address adr, Register reg);
+
+ void prefix(Address adr, XMMRegister reg);
+
+ void prefetch_prefix(Address src);
+
+ // Helper functions for groups of instructions
+ void emit_arith_b(int op1, int op2, Register dst, int imm8);
+
+ void emit_arith(int op1, int op2, Register dst, int32_t imm32);
+ // only 32bit??
+ void emit_arith(int op1, int op2, Register dst, jobject obj);
+ void emit_arith(int op1, int op2, Register dst, Register src);
+
+ void emit_operand(Register reg,
+ Register base, Register index, Address::ScaleFactor scale,
+ int disp,
+ RelocationHolder const& rspec,
+ int rip_relative_correction = 0);
+
+ void emit_operand(Register reg, Address adr, int rip_relative_correction = 0);
+
+ // operands that only take the original 32bit registers
+ void emit_operand32(Register reg, Address adr);
+
+ void emit_operand(XMMRegister reg,
+ Register base, Register index, Address::ScaleFactor scale,
+ int disp,
+ RelocationHolder const& rspec);
+
+ void emit_operand(XMMRegister reg, Address adr);
+
+ void emit_operand(MMXRegister reg, Address adr);
+
+ // workaround gcc (3.2.1-7) bug
+ void emit_operand(Address adr, MMXRegister reg);
+
+
+ // Immediate-to-memory forms
+ void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32);
+
+ void emit_farith(int b1, int b2, int i);
+
+
+ protected:
+ #ifdef ASSERT
+ void check_relocation(RelocationHolder const& rspec, int format);
+ #endif
+
+ inline void emit_long64(jlong x);
+
+ void emit_data(jint data, relocInfo::relocType rtype, int format);
+ void emit_data(jint data, RelocationHolder const& rspec, int format);
+ void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
+ void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
+
+
+ bool reachable(AddressLiteral adr) NOT_LP64({ return true;});
+
+ // These are all easily abused and hence protected
+
+ void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec, int format = 0);
+
+ // 32BIT ONLY SECTION
+#ifndef _LP64
+ // Make these disappear in 64bit mode since they would never be correct
+ void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
+ void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
+
+ void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
+
+ void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
+#else
+ // 64BIT ONLY SECTION
+ void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY
+#endif // _LP64
+
+ // These are unique in that we are ensured by the caller that the 32bit
+ // relative in these instructions will always be able to reach the potentially
+ // 64bit address described by entry. Since they can take a 64bit address they
+ // don't have the 32 suffix like the other instructions in this class.
+
+ void call_literal(address entry, RelocationHolder const& rspec);
+ void jmp_literal(address entry, RelocationHolder const& rspec);
+
+ // Avoid using directly section
+ // Instructions in this section are actually usable by anyone without danger
+ // of failure but have performance issues that are addressed my enhanced
+ // instructions which will do the proper thing base on the particular cpu.
+ // We protect them because we don't trust you...
+
+ // Don't use next inc() and dec() methods directly. INC & DEC instructions
+ // could cause a partial flag stall since they don't set CF flag.
+ // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
+ // which call inc() & dec() or add() & sub() in accordance with
+ // the product flag UseIncDec value.
+
+ void decl(Register dst);
+ void decl(Address dst);
+ void decq(Register dst);
+ void decq(Address dst);
+
+ void incl(Register dst);
+ void incl(Address dst);
+ void incq(Register dst);
+ void incq(Address dst);
+
+ // New cpus require use of movsd and movss to avoid partial register stall
+ // when loading from memory. But for old Opteron use movlpd instead of movsd.
+ // The selection is done in MacroAssembler::movdbl() and movflt().
+
+ // Move Scalar Single-Precision Floating-Point Values
+ void movss(XMMRegister dst, Address src);
+ void movss(XMMRegister dst, XMMRegister src);
+ void movss(Address dst, XMMRegister src);
+
+ // Move Scalar Double-Precision Floating-Point Values
+ void movsd(XMMRegister dst, Address src);
+ void movsd(XMMRegister dst, XMMRegister src);
+ void movsd(Address dst, XMMRegister src);
+ void movlpd(XMMRegister dst, Address src);
+
+ // New cpus require use of movaps and movapd to avoid partial register stall
+ // when moving between registers.
+ void movaps(XMMRegister dst, XMMRegister src);
+ void movapd(XMMRegister dst, XMMRegister src);
+
+ // End avoid using directly
+
+
+ // Instruction prefixes
+ void prefix(Prefix p);
+
public:
// Creation
@@ -499,219 +616,351 @@ class Assembler : public AbstractAssembler {
static address locate_operand(address inst, WhichOperand which);
static address locate_next_instruction(address inst);
- // Stack
- void pushad();
- void popad();
+ // Utilities
- void pushfd();
- void popfd();
+#ifdef _LP64
+ static bool is_simm(int64_t x, int nbits) { return -( CONST64(1) << (nbits-1) ) <= x && x < ( CONST64(1) << (nbits-1) ); }
+ static bool is_simm32(int64_t x) { return x == (int64_t)(int32_t)x; }
+#else
+ static bool is_simm(int32_t x, int nbits) { return -( 1 << (nbits-1) ) <= x && x < ( 1 << (nbits-1) ); }
+ static bool is_simm32(int32_t x) { return true; }
+#endif // LP64
- void pushl(int imm32);
- void pushoop(jobject obj);
+ // Generic instructions
+ // Does 32bit or 64bit as needed for the platform. In some sense these
+ // belong in macro assembler but there is no need for both varieties to exist
- void pushl(Register src);
- void pushl(Address src);
- // void pushl(Label& L, relocInfo::relocType rtype); ? needed?
+ void lea(Register dst, Address src);
- // dummy to prevent NULL being converted to Register
- void pushl(void* dummy);
+ void mov(Register dst, Register src);
- void popl(Register dst);
- void popl(Address dst);
+ void pusha();
+ void popa();
- // Instruction prefixes
- void prefix(Prefix p);
+ void pushf();
+ void popf();
- // Moves
- void movb(Register dst, Address src);
- void movb(Address dst, int imm8);
- void movb(Address dst, Register src);
+ void push(int32_t imm32);
- void movw(Address dst, int imm16);
- void movw(Register dst, Address src);
- void movw(Address dst, Register src);
+ void push(Register src);
- // these are dummies used to catch attempting to convert NULL to Register
- void movl(Register dst, void* junk);
- void movl(Address dst, void* junk);
+ void pop(Register dst);
- void movl(Register dst, int imm32);
- void movl(Address dst, int imm32);
- void movl(Register dst, Register src);
- void movl(Register dst, Address src);
- void movl(Address dst, Register src);
+ // These are dummies to prevent surprise implicit conversions to Register
+ void push(void* v);
+ void pop(void* v);
- void movsxb(Register dst, Address src);
- void movsxb(Register dst, Register src);
- void movsxw(Register dst, Address src);
- void movsxw(Register dst, Register src);
+ // These do register sized moves/scans
+ void rep_mov();
+ void rep_set();
+ void repne_scan();
+#ifdef _LP64
+ void repne_scanl();
+#endif
- void movzxb(Register dst, Address src);
- void movzxb(Register dst, Register src);
+ // Vanilla instructions in lexical order
- void movzxw(Register dst, Address src);
- void movzxw(Register dst, Register src);
-
- // Conditional moves (P6 only)
- void cmovl(Condition cc, Register dst, Register src);
- void cmovl(Condition cc, Register dst, Address src);
-
- // Prefetches (SSE, SSE2, 3DNOW only)
- void prefetcht0(Address src);
- void prefetcht1(Address src);
- void prefetcht2(Address src);
- void prefetchnta(Address src);
- void prefetchw(Address src);
- void prefetchr(Address src);
-
- // Arithmetics
- void adcl(Register dst, int imm32);
+ void adcl(Register dst, int32_t imm32);
void adcl(Register dst, Address src);
void adcl(Register dst, Register src);
- void addl(Address dst, int imm32);
+ void adcq(Register dst, int32_t imm32);
+ void adcq(Register dst, Address src);
+ void adcq(Register dst, Register src);
+
+
+ void addl(Address dst, int32_t imm32);
void addl(Address dst, Register src);
- void addl(Register dst, int imm32);
+ void addl(Register dst, int32_t imm32);
void addl(Register dst, Address src);
void addl(Register dst, Register src);
- void andl(Register dst, int imm32);
- void andl(Register dst, Address src);
- void andl(Register dst, Register src);
+ void addq(Address dst, int32_t imm32);
+ void addq(Address dst, Register src);
+ void addq(Register dst, int32_t imm32);
+ void addq(Register dst, Address src);
+ void addq(Register dst, Register src);
- void cmpb(Address dst, int imm8);
- void cmpw(Address dst, int imm16);
- void cmpl(Address dst, int imm32);
- void cmpl(Register dst, int imm32);
- void cmpl(Register dst, Register src);
- void cmpl(Register dst, Address src);
- // this is a dummy used to catch attempting to convert NULL to Register
- void cmpl(Register dst, void* junk);
-
- protected:
- // Don't use next inc() and dec() methods directly. INC & DEC instructions
- // could cause a partial flag stall since they don't set CF flag.
- // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
- // which call inc() & dec() or add() & sub() in accordance with
- // the product flag UseIncDec value.
-
- void decl(Register dst);
- void decl(Address dst);
-
- void incl(Register dst);
- void incl(Address dst);
-
- public:
- void idivl(Register src);
- void cdql();
-
- void imull(Register dst, Register src);
- void imull(Register dst, Register src, int value);
-
- void leal(Register dst, Address src);
-
- void mull(Address src);
- void mull(Register src);
-
- void negl(Register dst);
-
- void notl(Register dst);
-
- void orl(Address dst, int imm32);
- void orl(Register dst, int imm32);
- void orl(Register dst, Address src);
- void orl(Register dst, Register src);
-
- void rcll(Register dst, int imm8);
-
- void sarl(Register dst, int imm8);
- void sarl(Register dst);
-
- void sbbl(Address dst, int imm32);
- void sbbl(Register dst, int imm32);
- void sbbl(Register dst, Address src);
- void sbbl(Register dst, Register src);
-
- void shldl(Register dst, Register src);
-
- void shll(Register dst, int imm8);
- void shll(Register dst);
-
- void shrdl(Register dst, Register src);
-
- void shrl(Register dst, int imm8);
- void shrl(Register dst);
-
- void subl(Address dst, int imm32);
- void subl(Address dst, Register src);
- void subl(Register dst, int imm32);
- void subl(Register dst, Address src);
- void subl(Register dst, Register src);
-
- void testb(Register dst, int imm8);
- void testl(Register dst, int imm32);
- void testl(Register dst, Address src);
- void testl(Register dst, Register src);
-
- void xaddl(Address dst, Register src);
-
- void xorl(Register dst, int imm32);
- void xorl(Register dst, Address src);
- void xorl(Register dst, Register src);
-
- // Miscellaneous
- void bswap(Register reg);
- void lock();
-
- void xchg (Register reg, Address adr);
- void xchgl(Register dst, Register src);
-
- void cmpxchg (Register reg, Address adr);
- void cmpxchg8 (Address adr);
-
- void nop(int i = 1);
void addr_nop_4();
void addr_nop_5();
void addr_nop_7();
void addr_nop_8();
- void hlt();
- void ret(int imm16);
- void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
- void smovl();
- void rep_movl();
- void rep_set();
- void repne_scan();
- void setb(Condition cc, Register dst);
- void membar(); // Serializing memory-fence
- void cpuid();
- void cld();
- void std();
+ // Add Scalar Double-Precision Floating-Point Values
+ void addsd(XMMRegister dst, Address src);
+ void addsd(XMMRegister dst, XMMRegister src);
- void emit_raw (unsigned char);
+ // Add Scalar Single-Precision Floating-Point Values
+ void addss(XMMRegister dst, Address src);
+ void addss(XMMRegister dst, XMMRegister src);
+
+ void andl(Register dst, int32_t imm32);
+ void andl(Register dst, Address src);
+ void andl(Register dst, Register src);
+
+ void andq(Register dst, int32_t imm32);
+ void andq(Register dst, Address src);
+ void andq(Register dst, Register src);
+
+
+ // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
+ void andpd(XMMRegister dst, Address src);
+ void andpd(XMMRegister dst, XMMRegister src);
+
+ void bswapl(Register reg);
+
+ void bswapq(Register reg);
- // Calls
void call(Label& L, relocInfo::relocType rtype);
void call(Register reg); // push pc; pc <- reg
void call(Address adr); // push pc; pc <- adr
- // Jumps
- void jmp(Address entry); // pc <- entry
- void jmp(Register entry); // pc <- entry
+ void cdql();
- // Label operations & relative jumps (PPUM Appendix D)
- void jmp(Label& L, relocInfo::relocType rtype = relocInfo::none); // unconditional jump to L
+ void cdqq();
- // Force an 8-bit jump offset
- // void jmpb(address entry);
+ void cld() { emit_byte(0xfc); }
+
+ void clflush(Address adr);
+
+ void cmovl(Condition cc, Register dst, Register src);
+ void cmovl(Condition cc, Register dst, Address src);
+
+ void cmovq(Condition cc, Register dst, Register src);
+ void cmovq(Condition cc, Register dst, Address src);
+
+
+ void cmpb(Address dst, int imm8);
+
+ void cmpl(Address dst, int32_t imm32);
+
+ void cmpl(Register dst, int32_t imm32);
+ void cmpl(Register dst, Register src);
+ void cmpl(Register dst, Address src);
+
+ void cmpq(Address dst, int32_t imm32);
+ void cmpq(Address dst, Register src);
+
+ void cmpq(Register dst, int32_t imm32);
+ void cmpq(Register dst, Register src);
+ void cmpq(Register dst, Address src);
+
+ // these are dummies used to catch attempting to convert NULL to Register
+ void cmpl(Register dst, void* junk); // dummy
+ void cmpq(Register dst, void* junk); // dummy
+
+ void cmpw(Address dst, int imm16);
+
+ void cmpxchg8 (Address adr);
+
+ void cmpxchgl(Register reg, Address adr);
+
+ void cmpxchgq(Register reg, Address adr);
+
+ // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
+ void comisd(XMMRegister dst, Address src);
+
+ // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
+ void comiss(XMMRegister dst, Address src);
+
+ // Identify processor type and features
+ void cpuid() {
+ emit_byte(0x0F);
+ emit_byte(0xA2);
+ }
+
+ // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
+ void cvtsd2ss(XMMRegister dst, XMMRegister src);
+
+ // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
+ void cvtsi2sdl(XMMRegister dst, Register src);
+ void cvtsi2sdq(XMMRegister dst, Register src);
+
+ // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
+ void cvtsi2ssl(XMMRegister dst, Register src);
+ void cvtsi2ssq(XMMRegister dst, Register src);
+
+ // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value
+ void cvtdq2pd(XMMRegister dst, XMMRegister src);
+
+ // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value
+ void cvtdq2ps(XMMRegister dst, XMMRegister src);
+
+ // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
+ void cvtss2sd(XMMRegister dst, XMMRegister src);
+
+ // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
+ void cvttsd2sil(Register dst, Address src);
+ void cvttsd2sil(Register dst, XMMRegister src);
+ void cvttsd2siq(Register dst, XMMRegister src);
+
+ // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
+ void cvttss2sil(Register dst, XMMRegister src);
+ void cvttss2siq(Register dst, XMMRegister src);
+
+ // Divide Scalar Double-Precision Floating-Point Values
+ void divsd(XMMRegister dst, Address src);
+ void divsd(XMMRegister dst, XMMRegister src);
+
+ // Divide Scalar Single-Precision Floating-Point Values
+ void divss(XMMRegister dst, Address src);
+ void divss(XMMRegister dst, XMMRegister src);
+
+ void emms();
+
+ void fabs();
+
+ void fadd(int i);
+
+ void fadd_d(Address src);
+ void fadd_s(Address src);
+
+ // "Alternate" versions of x87 instructions place result down in FPU
+ // stack instead of on TOS
+
+ void fadda(int i); // "alternate" fadd
+ void faddp(int i = 1);
+
+ void fchs();
+
+ void fcom(int i);
+
+ void fcomp(int i = 1);
+ void fcomp_d(Address src);
+ void fcomp_s(Address src);
+
+ void fcompp();
+
+ void fcos();
+
+ void fdecstp();
+
+ void fdiv(int i);
+ void fdiv_d(Address src);
+ void fdivr_s(Address src);
+ void fdiva(int i); // "alternate" fdiv
+ void fdivp(int i = 1);
+
+ void fdivr(int i);
+ void fdivr_d(Address src);
+ void fdiv_s(Address src);
+
+ void fdivra(int i); // "alternate" reversed fdiv
+
+ void fdivrp(int i = 1);
+
+ void ffree(int i = 0);
+
+ void fild_d(Address adr);
+ void fild_s(Address adr);
+
+ void fincstp();
+
+ void finit();
+
+ void fist_s (Address adr);
+ void fistp_d(Address adr);
+ void fistp_s(Address adr);
+
+ void fld1();
+
+ void fld_d(Address adr);
+ void fld_s(Address adr);
+ void fld_s(int index);
+ void fld_x(Address adr); // extended-precision (80-bit) format
+
+ void fldcw(Address src);
+
+ void fldenv(Address src);
+
+ void fldlg2();
+
+ void fldln2();
+
+ void fldz();
+
+ void flog();
+ void flog10();
+
+ void fmul(int i);
+
+ void fmul_d(Address src);
+ void fmul_s(Address src);
+
+ void fmula(int i); // "alternate" fmul
+
+ void fmulp(int i = 1);
+
+ void fnsave(Address dst);
+
+ void fnstcw(Address src);
+
+ void fnstsw_ax();
+
+ void fprem();
+ void fprem1();
+
+ void frstor(Address src);
+
+ void fsin();
+
+ void fsqrt();
+
+ void fst_d(Address adr);
+ void fst_s(Address adr);
+
+ void fstp_d(Address adr);
+ void fstp_d(int index);
+ void fstp_s(Address adr);
+ void fstp_x(Address adr); // extended-precision (80-bit) format
+
+ void fsub(int i);
+ void fsub_d(Address src);
+ void fsub_s(Address src);
+
+ void fsuba(int i); // "alternate" fsub
+
+ void fsubp(int i = 1);
+
+ void fsubr(int i);
+ void fsubr_d(Address src);
+ void fsubr_s(Address src);
+
+ void fsubra(int i); // "alternate" reversed fsub
+
+ void fsubrp(int i = 1);
+
+ void ftan();
+
+ void ftst();
+
+ void fucomi(int i = 1);
+ void fucomip(int i = 1);
+
+ void fwait();
+
+ void fxch(int i = 1);
+
+ void fxrstor(Address src);
+
+ void fxsave(Address dst);
+
+ void fyl2x();
+
+ void hlt();
+
+ void idivl(Register src);
+
+ void idivq(Register src);
+
+ void imull(Register dst, Register src);
+ void imull(Register dst, Register src, int value);
+
+ void imulq(Register dst, Register src);
+ void imulq(Register dst, Register src, int value);
- // Unconditional 8-bit offset jump to L.
- // WARNING: be very careful using this for forward jumps. If the label is
- // not bound within an 8-bit offset of this instruction, a run-time error
- // will occur.
- void jmpb(Label& L);
// jcc is the generic conditional branch generator to run-
// time routines, jcc is used for branches to labels. jcc
@@ -737,250 +986,321 @@ class Assembler : public AbstractAssembler {
// will occur.
void jccb(Condition cc, Label& L);
- // Floating-point operations
- void fld1();
- void fldz();
+ void jmp(Address entry); // pc <- entry
- void fld_s(Address adr);
- void fld_s(int index);
- void fld_d(Address adr);
- void fld_x(Address adr); // extended-precision (80-bit) format
+ // Label operations & relative jumps (PPUM Appendix D)
+ void jmp(Label& L, relocInfo::relocType rtype = relocInfo::none); // unconditional jump to L
- void fst_s(Address adr);
- void fst_d(Address adr);
+ void jmp(Register entry); // pc <- entry
- void fstp_s(Address adr);
- void fstp_d(Address adr);
- void fstp_d(int index);
- void fstp_x(Address adr); // extended-precision (80-bit) format
+ // Unconditional 8-bit offset jump to L.
+ // WARNING: be very careful using this for forward jumps. If the label is
+ // not bound within an 8-bit offset of this instruction, a run-time error
+ // will occur.
+ void jmpb(Label& L);
- void fild_s(Address adr);
- void fild_d(Address adr);
+ void ldmxcsr( Address src );
- void fist_s (Address adr);
- void fistp_s(Address adr);
- void fistp_d(Address adr);
+ void leal(Register dst, Address src);
- void fabs();
- void fchs();
+ void leaq(Register dst, Address src);
- void flog();
- void flog10();
+ void lfence() {
+ emit_byte(0x0F);
+ emit_byte(0xAE);
+ emit_byte(0xE8);
+ }
- void fldln2();
- void fyl2x();
- void fldlg2();
+ void lock();
- void fcos();
- void fsin();
- void ftan();
- void fsqrt();
+ enum Membar_mask_bits {
+ StoreStore = 1 << 3,
+ LoadStore = 1 << 2,
+ StoreLoad = 1 << 1,
+ LoadLoad = 1 << 0
+ };
- // "Alternate" versions of instructions place result down in FPU
- // stack instead of on TOS
- void fadd_s(Address src);
- void fadd_d(Address src);
- void fadd(int i);
- void fadda(int i); // "alternate" fadd
+ // Serializes memory.
+ void membar(Membar_mask_bits order_constraint) {
+ // We only have to handle StoreLoad and LoadLoad
+ if (order_constraint & StoreLoad) {
+ // MFENCE subsumes LFENCE
+ mfence();
+ } /* [jk] not needed currently: else if (order_constraint & LoadLoad) {
+ lfence();
+ } */
+ }
- void fsub_s(Address src);
- void fsub_d(Address src);
- void fsubr_s(Address src);
- void fsubr_d(Address src);
+ void mfence();
- void fmul_s(Address src);
- void fmul_d(Address src);
- void fmul(int i);
- void fmula(int i); // "alternate" fmul
+ // Moves
- void fdiv_s(Address src);
- void fdiv_d(Address src);
- void fdivr_s(Address src);
- void fdivr_d(Address src);
+ void mov64(Register dst, int64_t imm64);
- void fsub(int i);
- void fsuba(int i); // "alternate" fsub
- void fsubr(int i);
- void fsubra(int i); // "alternate" reversed fsub
- void fdiv(int i);
- void fdiva(int i); // "alternate" fdiv
- void fdivr(int i);
- void fdivra(int i); // "alternate" reversed fdiv
+ void movb(Address dst, Register src);
+ void movb(Address dst, int imm8);
+ void movb(Register dst, Address src);
- void faddp(int i = 1);
- void fsubp(int i = 1);
- void fsubrp(int i = 1);
- void fmulp(int i = 1);
- void fdivp(int i = 1);
- void fdivrp(int i = 1);
- void fprem();
- void fprem1();
+ void movdl(XMMRegister dst, Register src);
+ void movdl(Register dst, XMMRegister src);
- void fxch(int i = 1);
- void fincstp();
- void fdecstp();
- void ffree(int i = 0);
+ // Move Double Quadword
+ void movdq(XMMRegister dst, Register src);
+ void movdq(Register dst, XMMRegister src);
- void fcomp_s(Address src);
- void fcomp_d(Address src);
- void fcom(int i);
- void fcomp(int i = 1);
- void fcompp();
+ // Move Aligned Double Quadword
+ void movdqa(Address dst, XMMRegister src);
+ void movdqa(XMMRegister dst, Address src);
+ void movdqa(XMMRegister dst, XMMRegister src);
- void fucomi(int i = 1);
- void fucomip(int i = 1);
+ void movl(Register dst, int32_t imm32);
+ void movl(Address dst, int32_t imm32);
+ void movl(Register dst, Register src);
+ void movl(Register dst, Address src);
+ void movl(Address dst, Register src);
- void ftst();
- void fnstsw_ax();
- void fwait();
- void finit();
- void fldcw(Address src);
- void fnstcw(Address src);
+ // These dummies prevent using movl from converting a zero (like NULL) into Register
+ // by giving the compiler two choices it can't resolve
- void fnsave(Address dst);
- void frstor(Address src);
- void fldenv(Address src);
+ void movl(Address dst, void* junk);
+ void movl(Register dst, void* junk);
+
+#ifdef _LP64
+ void movq(Register dst, Register src);
+ void movq(Register dst, Address src);
+ void movq(Address dst, Register src);
+#endif
+
+ void movq(Address dst, MMXRegister src );
+ void movq(MMXRegister dst, Address src );
+
+#ifdef _LP64
+ // These dummies prevent using movq from converting a zero (like NULL) into Register
+ // by giving the compiler two choices it can't resolve
+
+ void movq(Address dst, void* dummy);
+ void movq(Register dst, void* dummy);
+#endif
+
+ // Move Quadword
+ void movq(Address dst, XMMRegister src);
+ void movq(XMMRegister dst, Address src);
+
+ void movsbl(Register dst, Address src);
+ void movsbl(Register dst, Register src);
+
+#ifdef _LP64
+ // Move signed 32bit immediate to 64bit extending sign
+ void movslq(Address dst, int32_t imm64);
+ void movslq(Register dst, int32_t imm64);
+
+ void movslq(Register dst, Address src);
+ void movslq(Register dst, Register src);
+ void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous
+#endif
+
+ void movswl(Register dst, Address src);
+ void movswl(Register dst, Register src);
+
+ void movw(Address dst, int imm16);
+ void movw(Register dst, Address src);
+ void movw(Address dst, Register src);
+
+ void movzbl(Register dst, Address src);
+ void movzbl(Register dst, Register src);
+
+ void movzwl(Register dst, Address src);
+ void movzwl(Register dst, Register src);
+
+ void mull(Address src);
+ void mull(Register src);
+
+ // Multiply Scalar Double-Precision Floating-Point Values
+ void mulsd(XMMRegister dst, Address src);
+ void mulsd(XMMRegister dst, XMMRegister src);
+
+ // Multiply Scalar Single-Precision Floating-Point Values
+ void mulss(XMMRegister dst, Address src);
+ void mulss(XMMRegister dst, XMMRegister src);
+
+ void negl(Register dst);
+
+#ifdef _LP64
+ void negq(Register dst);
+#endif
+
+ void nop(int i = 1);
+
+ void notl(Register dst);
+
+#ifdef _LP64
+ void notq(Register dst);
+#endif
+
+ void orl(Address dst, int32_t imm32);
+ void orl(Register dst, int32_t imm32);
+ void orl(Register dst, Address src);
+ void orl(Register dst, Register src);
+
+ void orq(Address dst, int32_t imm32);
+ void orq(Register dst, int32_t imm32);
+ void orq(Register dst, Address src);
+ void orq(Register dst, Register src);
+
+ void popl(Address dst);
+
+#ifdef _LP64
+ void popq(Address dst);
+#endif
+
+ // Prefetches (SSE, SSE2, 3DNOW only)
+
+ void prefetchnta(Address src);
+ void prefetchr(Address src);
+ void prefetcht0(Address src);
+ void prefetcht1(Address src);
+ void prefetcht2(Address src);
+ void prefetchw(Address src);
+
+ // Shuffle Packed Doublewords
+ void pshufd(XMMRegister dst, XMMRegister src, int mode);
+ void pshufd(XMMRegister dst, Address src, int mode);
+
+ // Shuffle Packed Low Words
+ void pshuflw(XMMRegister dst, XMMRegister src, int mode);
+ void pshuflw(XMMRegister dst, Address src, int mode);
+
+ // Shift Right Logical Quadword Immediate
+ void psrlq(XMMRegister dst, int shift);
+
+ // Interleave Low Bytes
+ void punpcklbw(XMMRegister dst, XMMRegister src);
+
+ void pushl(Address src);
+
+ void pushq(Address src);
+
+ // Xor Packed Byte Integer Values
+ void pxor(XMMRegister dst, Address src);
+ void pxor(XMMRegister dst, XMMRegister src);
+
+ void rcll(Register dst, int imm8);
+
+ void rclq(Register dst, int imm8);
+
+ void ret(int imm16);
void sahf();
- protected:
- void emit_sse_operand(XMMRegister reg, Address adr);
- void emit_sse_operand(Register reg, Address adr);
- void emit_sse_operand(XMMRegister dst, XMMRegister src);
- void emit_sse_operand(XMMRegister dst, Register src);
- void emit_sse_operand(Register dst, XMMRegister src);
+ void sarl(Register dst, int imm8);
+ void sarl(Register dst);
- void emit_operand(MMXRegister reg, Address adr);
+ void sarq(Register dst, int imm8);
+ void sarq(Register dst);
- public:
- // mmx operations
- void movq( MMXRegister dst, Address src );
- void movq( Address dst, MMXRegister src );
- void emms();
+ void sbbl(Address dst, int32_t imm32);
+ void sbbl(Register dst, int32_t imm32);
+ void sbbl(Register dst, Address src);
+ void sbbl(Register dst, Register src);
- // xmm operations
- void addss(XMMRegister dst, Address src); // Add Scalar Single-Precision Floating-Point Values
- void addss(XMMRegister dst, XMMRegister src);
- void addsd(XMMRegister dst, Address src); // Add Scalar Double-Precision Floating-Point Values
- void addsd(XMMRegister dst, XMMRegister src);
+ void sbbq(Address dst, int32_t imm32);
+ void sbbq(Register dst, int32_t imm32);
+ void sbbq(Register dst, Address src);
+ void sbbq(Register dst, Register src);
- void subss(XMMRegister dst, Address src); // Subtract Scalar Single-Precision Floating-Point Values
- void subss(XMMRegister dst, XMMRegister src);
- void subsd(XMMRegister dst, Address src); // Subtract Scalar Double-Precision Floating-Point Values
- void subsd(XMMRegister dst, XMMRegister src);
+ void setb(Condition cc, Register dst);
- void mulss(XMMRegister dst, Address src); // Multiply Scalar Single-Precision Floating-Point Values
- void mulss(XMMRegister dst, XMMRegister src);
- void mulsd(XMMRegister dst, Address src); // Multiply Scalar Double-Precision Floating-Point Values
- void mulsd(XMMRegister dst, XMMRegister src);
+ void shldl(Register dst, Register src);
- void divss(XMMRegister dst, Address src); // Divide Scalar Single-Precision Floating-Point Values
- void divss(XMMRegister dst, XMMRegister src);
- void divsd(XMMRegister dst, Address src); // Divide Scalar Double-Precision Floating-Point Values
- void divsd(XMMRegister dst, XMMRegister src);
+ void shll(Register dst, int imm8);
+ void shll(Register dst);
- void sqrtss(XMMRegister dst, Address src); // Compute Square Root of Scalar Single-Precision Floating-Point Value
- void sqrtss(XMMRegister dst, XMMRegister src);
- void sqrtsd(XMMRegister dst, Address src); // Compute Square Root of Scalar Double-Precision Floating-Point Value
+ void shlq(Register dst, int imm8);
+ void shlq(Register dst);
+
+ void shrdl(Register dst, Register src);
+
+ void shrl(Register dst, int imm8);
+ void shrl(Register dst);
+
+ void shrq(Register dst, int imm8);
+ void shrq(Register dst);
+
+ void smovl(); // QQQ generic?
+
+ // Compute Square Root of Scalar Double-Precision Floating-Point Value
+ void sqrtsd(XMMRegister dst, Address src);
void sqrtsd(XMMRegister dst, XMMRegister src);
- void pxor(XMMRegister dst, Address src); // Xor Packed Byte Integer Values
- void pxor(XMMRegister dst, XMMRegister src); // Xor Packed Byte Integer Values
+ void std() { emit_byte(0xfd); }
- void comiss(XMMRegister dst, Address src); // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
- void comiss(XMMRegister dst, XMMRegister src);
- void comisd(XMMRegister dst, Address src); // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
- void comisd(XMMRegister dst, XMMRegister src);
+ void stmxcsr( Address dst );
- void ucomiss(XMMRegister dst, Address src); // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
- void ucomiss(XMMRegister dst, XMMRegister src);
- void ucomisd(XMMRegister dst, Address src); // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
+ void subl(Address dst, int32_t imm32);
+ void subl(Address dst, Register src);
+ void subl(Register dst, int32_t imm32);
+ void subl(Register dst, Address src);
+ void subl(Register dst, Register src);
+
+ void subq(Address dst, int32_t imm32);
+ void subq(Address dst, Register src);
+ void subq(Register dst, int32_t imm32);
+ void subq(Register dst, Address src);
+ void subq(Register dst, Register src);
+
+
+ // Subtract Scalar Double-Precision Floating-Point Values
+ void subsd(XMMRegister dst, Address src);
+ void subsd(XMMRegister dst, XMMRegister src);
+
+ // Subtract Scalar Single-Precision Floating-Point Values
+ void subss(XMMRegister dst, Address src);
+ void subss(XMMRegister dst, XMMRegister src);
+
+ void testb(Register dst, int imm8);
+
+ void testl(Register dst, int32_t imm32);
+ void testl(Register dst, Register src);
+ void testl(Register dst, Address src);
+
+ void testq(Register dst, int32_t imm32);
+ void testq(Register dst, Register src);
+
+
+ // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
+ void ucomisd(XMMRegister dst, Address src);
void ucomisd(XMMRegister dst, XMMRegister src);
- void cvtss2sd(XMMRegister dst, Address src); // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
- void cvtss2sd(XMMRegister dst, XMMRegister src);
- void cvtsd2ss(XMMRegister dst, Address src); // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
- void cvtsd2ss(XMMRegister dst, XMMRegister src);
- void cvtdq2pd(XMMRegister dst, XMMRegister src);
- void cvtdq2ps(XMMRegister dst, XMMRegister src);
+ // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
+ void ucomiss(XMMRegister dst, Address src);
+ void ucomiss(XMMRegister dst, XMMRegister src);
- void cvtsi2ss(XMMRegister dst, Address src); // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
- void cvtsi2ss(XMMRegister dst, Register src);
- void cvtsi2sd(XMMRegister dst, Address src); // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
- void cvtsi2sd(XMMRegister dst, Register src);
+ void xaddl(Address dst, Register src);
- void cvtss2si(Register dst, Address src); // Convert Scalar Single-Precision Floating-Point Value to Doubleword Integer
- void cvtss2si(Register dst, XMMRegister src);
- void cvtsd2si(Register dst, Address src); // Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer
- void cvtsd2si(Register dst, XMMRegister src);
+ void xaddq(Address dst, Register src);
- void cvttss2si(Register dst, Address src); // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
- void cvttss2si(Register dst, XMMRegister src);
- void cvttsd2si(Register dst, Address src); // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
- void cvttsd2si(Register dst, XMMRegister src);
+ void xchgl(Register reg, Address adr);
+ void xchgl(Register dst, Register src);
- protected: // Avoid using the next instructions directly.
- // New cpus require use of movsd and movss to avoid partial register stall
- // when loading from memory. But for old Opteron use movlpd instead of movsd.
- // The selection is done in MacroAssembler::movdbl() and movflt().
- void movss(XMMRegister dst, Address src); // Move Scalar Single-Precision Floating-Point Values
- void movss(XMMRegister dst, XMMRegister src);
- void movss(Address dst, XMMRegister src);
- void movsd(XMMRegister dst, Address src); // Move Scalar Double-Precision Floating-Point Values
- void movsd(XMMRegister dst, XMMRegister src);
- void movsd(Address dst, XMMRegister src);
- void movlpd(XMMRegister dst, Address src);
- // New cpus require use of movaps and movapd to avoid partial register stall
- // when moving between registers.
- void movaps(XMMRegister dst, XMMRegister src);
- void movapd(XMMRegister dst, XMMRegister src);
- public:
+ void xchgq(Register reg, Address adr);
+ void xchgq(Register dst, Register src);
- void andps(XMMRegister dst, Address src); // Bitwise Logical AND of Packed Single-Precision Floating-Point Values
- void andps(XMMRegister dst, XMMRegister src);
- void andpd(XMMRegister dst, Address src); // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
- void andpd(XMMRegister dst, XMMRegister src);
+ void xorl(Register dst, int32_t imm32);
+ void xorl(Register dst, Address src);
+ void xorl(Register dst, Register src);
- void andnps(XMMRegister dst, Address src); // Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values
- void andnps(XMMRegister dst, XMMRegister src);
- void andnpd(XMMRegister dst, Address src); // Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values
- void andnpd(XMMRegister dst, XMMRegister src);
+ void xorq(Register dst, Address src);
+ void xorq(Register dst, Register src);
- void orps(XMMRegister dst, Address src); // Bitwise Logical OR of Packed Single-Precision Floating-Point Values
- void orps(XMMRegister dst, XMMRegister src);
- void orpd(XMMRegister dst, Address src); // Bitwise Logical OR of Packed Double-Precision Floating-Point Values
- void orpd(XMMRegister dst, XMMRegister src);
-
- void xorps(XMMRegister dst, Address src); // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
- void xorps(XMMRegister dst, XMMRegister src);
- void xorpd(XMMRegister dst, Address src); // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
+ // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
+ void xorpd(XMMRegister dst, Address src);
void xorpd(XMMRegister dst, XMMRegister src);
- void movq(XMMRegister dst, Address src); // Move Quadword
- void movq(XMMRegister dst, XMMRegister src);
- void movq(Address dst, XMMRegister src);
+ // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
+ void xorps(XMMRegister dst, Address src);
+ void xorps(XMMRegister dst, XMMRegister src);
- void movd(XMMRegister dst, Address src); // Move Doubleword
- void movd(XMMRegister dst, Register src);
- void movd(Register dst, XMMRegister src);
- void movd(Address dst, XMMRegister src);
-
- void movdqa(XMMRegister dst, Address src); // Move Aligned Double Quadword
- void movdqa(XMMRegister dst, XMMRegister src);
- void movdqa(Address dst, XMMRegister src);
-
- void pshufd(XMMRegister dst, XMMRegister src, int mode); // Shuffle Packed Doublewords
- void pshufd(XMMRegister dst, Address src, int mode);
- void pshuflw(XMMRegister dst, XMMRegister src, int mode); // Shuffle Packed Low Words
- void pshuflw(XMMRegister dst, Address src, int mode);
-
- void psrlq(XMMRegister dst, int shift); // Shift Right Logical Quadword Immediate
-
- void punpcklbw(XMMRegister dst, XMMRegister src); // Interleave Low Bytes
- void punpcklbw(XMMRegister dst, Address src);
-
- void ldmxcsr( Address src );
- void stmxcsr( Address dst );
+ void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
};
@@ -1077,10 +1397,22 @@ class MacroAssembler: public Assembler {
void extend_sign(Register hi, Register lo);
// Support for inc/dec with optimal instruction selection depending on value
- void increment(Register reg, int value = 1);
- void decrement(Register reg, int value = 1);
- void increment(Address dst, int value = 1);
- void decrement(Address dst, int value = 1);
+
+ void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
+ void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
+
+ void decrementl(Address dst, int value = 1);
+ void decrementl(Register reg, int value = 1);
+
+ void decrementq(Register reg, int value = 1);
+ void decrementq(Address dst, int value = 1);
+
+ void incrementl(Address dst, int value = 1);
+ void incrementl(Register reg, int value = 1);
+
+ void incrementq(Register reg, int value = 1);
+ void incrementq(Address dst, int value = 1);
+
// Support optimal SSE move instructions.
void movflt(XMMRegister dst, XMMRegister src) {
@@ -1104,9 +1436,8 @@ class MacroAssembler: public Assembler {
}
void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
- void increment(AddressLiteral dst);
- void increment(ArrayAddress dst);
-
+ void incrementl(AddressLiteral dst);
+ void incrementl(ArrayAddress dst);
// Alignment
void align(int modulus);
@@ -1128,25 +1459,70 @@ class MacroAssembler: public Assembler {
// They make sure that the stack linkage is setup correctly. call_VM's correspond
// to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
- void call_VM(Register oop_result, address entry_point, bool check_exceptions = true);
- void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true);
- void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
- void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
- void call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
- void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
- void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
- void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
+ void call_VM(Register oop_result,
+ address entry_point,
+ bool check_exceptions = true);
+ void call_VM(Register oop_result,
+ address entry_point,
+ Register arg_1,
+ bool check_exceptions = true);
+ void call_VM(Register oop_result,
+ address entry_point,
+ Register arg_1, Register arg_2,
+ bool check_exceptions = true);
+ void call_VM(Register oop_result,
+ address entry_point,
+ Register arg_1, Register arg_2, Register arg_3,
+ bool check_exceptions = true);
- void call_VM_leaf(address entry_point, int number_of_arguments = 0);
- void call_VM_leaf(address entry_point, Register arg_1);
- void call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
- void call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
+ // Overloadings with last_Java_sp
+ void call_VM(Register oop_result,
+ Register last_java_sp,
+ address entry_point,
+ int number_of_arguments = 0,
+ bool check_exceptions = true);
+ void call_VM(Register oop_result,
+ Register last_java_sp,
+ address entry_point,
+ Register arg_1, bool
+ check_exceptions = true);
+ void call_VM(Register oop_result,
+ Register last_java_sp,
+ address entry_point,
+ Register arg_1, Register arg_2,
+ bool check_exceptions = true);
+ void call_VM(Register oop_result,
+ Register last_java_sp,
+ address entry_point,
+ Register arg_1, Register arg_2, Register arg_3,
+ bool check_exceptions = true);
+
+ void call_VM_leaf(address entry_point,
+ int number_of_arguments = 0);
+ void call_VM_leaf(address entry_point,
+ Register arg_1);
+ void call_VM_leaf(address entry_point,
+ Register arg_1, Register arg_2);
+ void call_VM_leaf(address entry_point,
+ Register arg_1, Register arg_2, Register arg_3);
// last Java Frame (fills frame anchor)
- void set_last_Java_frame(Register thread, Register last_java_sp, Register last_java_fp, address last_java_pc);
+ void set_last_Java_frame(Register thread,
+ Register last_java_sp,
+ Register last_java_fp,
+ address last_java_pc);
+
+ // thread in the default location (r15_thread on 64bit)
+ void set_last_Java_frame(Register last_java_sp,
+ Register last_java_fp,
+ address last_java_pc);
+
void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc);
+ // thread in the default location (r15_thread on 64bit)
+ void reset_last_Java_frame(bool clear_fp, bool clear_pc);
+
// Stores
void store_check(Register obj); // store check for obj - register is destroyed afterwards
void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
@@ -1165,18 +1541,48 @@ class MacroAssembler: public Assembler {
void movbool(Address dst, Register src);
void testbool(Register dst);
- // Int division/reminder for Java
+ // oop manipulations
+ void load_klass(Register dst, Register src);
+ void store_klass(Register dst, Register src);
+
+ void load_prototype_header(Register dst, Register src);
+
+#ifdef _LP64
+ void store_klass_gap(Register dst, Register src);
+
+ void load_heap_oop(Register dst, Address src);
+ void store_heap_oop(Address dst, Register src);
+ void encode_heap_oop(Register r);
+ void decode_heap_oop(Register r);
+ void encode_heap_oop_not_null(Register r);
+ void decode_heap_oop_not_null(Register r);
+ void encode_heap_oop_not_null(Register dst, Register src);
+ void decode_heap_oop_not_null(Register dst, Register src);
+
+ void set_narrow_oop(Register dst, jobject obj);
+
+ // if heap base register is used - reinit it with the correct value
+ void reinit_heapbase();
+#endif // _LP64
+
+ // Int division/remainder for Java
// (as idivl, but checks for special case as described in JVM spec.)
// returns idivl instruction offset for implicit exception handling
int corrected_idivl(Register reg);
+ // Long division/remainder for Java
+ // (as idivq, but checks for special case as described in JVM spec.)
+ // returns idivq instruction offset for implicit exception handling
+ int corrected_idivq(Register reg);
+
void int3();
+ // Long operation macros for a 32bit cpu
// Long negation for Java
void lneg(Register hi, Register lo);
// Long multiplication for Java
- // (destroys contents of rax, rbx, rcx and rdx)
+ // (destroys contents of eax, ebx, ecx and edx)
void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
// Long shifts for Java
@@ -1188,6 +1594,16 @@ class MacroAssembler: public Assembler {
// (semantics as described in JVM spec.)
void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
+
+ // misc
+
+ // Sign extension
+ void sign_extend_short(Register reg);
+ void sign_extend_byte(Register reg);
+
+ // Division by power of 2, rounding towards 0
+ void division_with_shift(Register reg, int shift_value);
+
// Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
//
// CF (corresponds to C0) if x < y
@@ -1255,13 +1671,6 @@ class MacroAssembler: public Assembler {
void push_CPU_state();
void pop_CPU_state();
- // Sign extension
- void sign_extend_short(Register reg);
- void sign_extend_byte(Register reg);
-
- // Division by power of 2, rounding towards 0
- void division_with_shift(Register reg, int shift_value);
-
// Round up to a power of two
void round_to(Register reg, int modulus);
@@ -1291,17 +1700,31 @@ class MacroAssembler: public Assembler {
void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
// Debugging
- void verify_oop(Register reg, const char* s = "broken oop"); // only if +VerifyOops
+
+ // only if +VerifyOops
+ void verify_oop(Register reg, const char* s = "broken oop");
void verify_oop_addr(Address addr, const char * s = "broken oop addr");
- void verify_FPU(int stack_depth, const char* s = "illegal FPU state"); // only if +VerifyFPU
- void stop(const char* msg); // prints msg, dumps registers and stops execution
- void warn(const char* msg); // prints msg and continues
- static void debug(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
+ // only if +VerifyFPU
+ void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
+
+ // prints msg, dumps registers and stops execution
+ void stop(const char* msg);
+
+ // prints msg and continues
+ void warn(const char* msg);
+
+ static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
+ static void debug64(char* msg, int64_t pc, int64_t regs[]);
+
void os_breakpoint();
+
void untested() { stop("untested"); }
+
void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, sizeof(b), "unimplemented: %s", what); stop(b); }
+
void should_not_reach_here() { stop("should not reach here"); }
+
void print_CPU_state();
// Stack overflow checking
@@ -1348,9 +1771,20 @@ class MacroAssembler: public Assembler {
// Arithmetics
- void cmp8(AddressLiteral src1, int8_t imm);
- // QQQ renamed to drag out the casting of address to int32_t/intptr_t
+ void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
+ void addptr(Address dst, Register src);
+
+ void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
+ void addptr(Register dst, int32_t src);
+ void addptr(Register dst, Register src);
+
+ void andptr(Register dst, int32_t src);
+ void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
+
+ void cmp8(AddressLiteral src1, int imm);
+
+ // renamed to drag out the casting of address to int32_t/intptr_t
void cmp32(Register src1, int32_t imm);
void cmp32(AddressLiteral src1, int32_t imm);
@@ -1359,16 +1793,63 @@ class MacroAssembler: public Assembler {
void cmp32(Register src1, Address src2);
+#ifndef _LP64
+ void cmpoop(Address dst, jobject obj);
+ void cmpoop(Register dst, jobject obj);
+#endif // _LP64
+
// NOTE src2 must be the lval. This is NOT an mem-mem compare
void cmpptr(Address src1, AddressLiteral src2);
void cmpptr(Register src1, AddressLiteral src2);
- void cmpoop(Address dst, jobject obj);
- void cmpoop(Register dst, jobject obj);
+ void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
+ void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
+ // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
+
+ void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
+ void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
+
+ // cmp64 to avoild hiding cmpq
+ void cmp64(Register src1, AddressLiteral src);
+
+ void cmpxchgptr(Register reg, Address adr);
+
+ void locked_cmpxchgptr(Register reg, AddressLiteral adr);
+
+
+ void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
+
+
+ void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
+
+ void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
+
+ void shlptr(Register dst, int32_t shift);
+ void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
+
+ void shrptr(Register dst, int32_t shift);
+ void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
+
+ void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
+ void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
+
+ void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
+
+ void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
+ void subptr(Register dst, int32_t src);
+ void subptr(Register dst, Register src);
+
+
+ void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
+ void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
+
+ void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
+ void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
+
+ void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
- void cmpxchgptr(Register reg, AddressLiteral adr);
// Helper functions for statistics gathering.
// Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
@@ -1378,8 +1859,21 @@ class MacroAssembler: public Assembler {
void lea(Register dst, AddressLiteral adr);
void lea(Address dst, AddressLiteral adr);
+ void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
- void test32(Register dst, AddressLiteral src);
+ void leal32(Register dst, Address src) { leal(dst, src); }
+
+ void test32(Register src1, AddressLiteral src2);
+
+ void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
+ void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
+ void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
+
+ void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
+ void testptr(Register src1, Register src2);
+
+ void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
+ void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
// Calls
@@ -1431,11 +1925,19 @@ class MacroAssembler: public Assembler {
void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
void ldmxcsr(AddressLiteral src);
+private:
+ // these are private because users should be doing movflt/movdbl
+
void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
void movss(XMMRegister dst, AddressLiteral src);
+ void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
+ void movlpd(XMMRegister dst, AddressLiteral src);
+
+public:
+
void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
@@ -1461,6 +1963,11 @@ class MacroAssembler: public Assembler {
// Data
+ void cmov(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); }
+
+ void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); }
+ void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); }
+
void movoop(Register dst, jobject obj);
void movoop(Address dst, jobject obj);
@@ -1468,17 +1975,48 @@ class MacroAssembler: public Assembler {
// can this do an lea?
void movptr(Register dst, ArrayAddress src);
+ void movptr(Register dst, Address src);
+
void movptr(Register dst, AddressLiteral src);
+ void movptr(Register dst, intptr_t src);
+ void movptr(Register dst, Register src);
+ void movptr(Address dst, intptr_t src);
+
+ void movptr(Address dst, Register src);
+
+#ifdef _LP64
+ // Generally the next two are only used for moving NULL
+ // Although there are situations in initializing the mark word where
+ // they could be used. They are dangerous.
+
+ // They only exist on LP64 so that int32_t and intptr_t are not the same
+ // and we have ambiguous declarations.
+
+ void movptr(Address dst, int32_t imm32);
+ void movptr(Register dst, int32_t imm32);
+#endif // _LP64
+
// to avoid hiding movl
void mov32(AddressLiteral dst, Register src);
void mov32(Register dst, AddressLiteral src);
+
// to avoid hiding movb
void movbyte(ArrayAddress dst, int src);
// Can push value or effective address
void pushptr(AddressLiteral src);
+ void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
+ void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
+
+ void pushoop(jobject obj);
+
+ // sign extend as need a l to ptr sized element
+ void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
+ void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
+
+
#undef VIRTUAL
};
diff --git a/hotspot/src/cpu/x86/vm/assembler_x86_64.inline.hpp b/hotspot/src/cpu/x86/vm/assembler_x86.inline.hpp
similarity index 74%
rename from hotspot/src/cpu/x86/vm/assembler_x86_64.inline.hpp
rename to hotspot/src/cpu/x86/vm/assembler_x86.inline.hpp
index 3a705ea3ea1..27c2b6addc0 100644
--- a/hotspot/src/cpu/x86/vm/assembler_x86_64.inline.hpp
+++ b/hotspot/src/cpu/x86/vm/assembler_x86.inline.hpp
@@ -1,5 +1,5 @@
/*
- * Copyright 2003-2005 Sun Microsystems, Inc. All Rights Reserved.
+ * Copyright 1997-2005 Sun Microsystems, Inc. All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -22,12 +22,6 @@
*
*/
-inline void Assembler::emit_long64(jlong x) {
- *(jlong*) _code_pos = x;
- _code_pos += sizeof(jlong);
- code_section()->set_end(_code_pos);
-}
-
inline void MacroAssembler::pd_patch_instruction(address branch, address target) {
unsigned char op = branch[0];
assert(op == 0xE8 /* call */ ||
@@ -69,18 +63,25 @@ inline void MacroAssembler::pd_print_patched_instruction(address branch) {
}
#endif // ndef PRODUCT
-inline void MacroAssembler::movptr(Address dst, intptr_t src) {
-#ifdef _LP64
- Assembler::mov64(dst, src);
-#else
- Assembler::movl(dst, src);
-#endif // _LP64
-}
+#ifndef _LP64
+inline int Assembler::prefix_and_encode(int reg_enc, bool byteinst) { return reg_enc; }
+inline int Assembler::prefixq_and_encode(int reg_enc) { return reg_enc; }
-inline void MacroAssembler::movptr(Register dst, intptr_t src) {
-#ifdef _LP64
- Assembler::mov64(dst, src);
+inline int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) { return dst_enc << 3 | src_enc; }
+inline int Assembler::prefixq_and_encode(int dst_enc, int src_enc) { return dst_enc << 3 | src_enc; }
+
+inline void Assembler::prefix(Register reg) {}
+inline void Assembler::prefix(Address adr) {}
+inline void Assembler::prefixq(Address adr) {}
+
+inline void Assembler::prefix(Address adr, Register reg, bool byteinst) {}
+inline void Assembler::prefixq(Address adr, Register reg) {}
+
+inline void Assembler::prefix(Address adr, XMMRegister reg) {}
#else
- Assembler::movl(dst, src);
-#endif // _LP64
+inline void Assembler::emit_long64(jlong x) {
+ *(jlong*) _code_pos = x;
+ _code_pos += sizeof(jlong);
+ code_section()->set_end(_code_pos);
}
+#endif // _LP64
diff --git a/hotspot/src/cpu/x86/vm/assembler_x86_32.cpp b/hotspot/src/cpu/x86/vm/assembler_x86_32.cpp
deleted file mode 100644
index 91c2e9ab193..00000000000
--- a/hotspot/src/cpu/x86/vm/assembler_x86_32.cpp
+++ /dev/null
@@ -1,5001 +0,0 @@
-/*
- * Copyright 1997-2008 Sun Microsystems, Inc. All Rights Reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
- * CA 95054 USA or visit www.sun.com if you need additional information or
- * have any questions.
- *
- */
-
-#include "incls/_precompiled.incl"
-#include "incls/_assembler_x86_32.cpp.incl"
-
-// Implementation of AddressLiteral
-
-AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
- _is_lval = false;
- _target = target;
- switch (rtype) {
- case relocInfo::oop_type:
- // Oops are a special case. Normally they would be their own section
- // but in cases like icBuffer they are literals in the code stream that
- // we don't have a section for. We use none so that we get a literal address
- // which is always patchable.
- break;
- case relocInfo::external_word_type:
- _rspec = external_word_Relocation::spec(target);
- break;
- case relocInfo::internal_word_type:
- _rspec = internal_word_Relocation::spec(target);
- break;
- case relocInfo::opt_virtual_call_type:
- _rspec = opt_virtual_call_Relocation::spec();
- break;
- case relocInfo::static_call_type:
- _rspec = static_call_Relocation::spec();
- break;
- case relocInfo::runtime_call_type:
- _rspec = runtime_call_Relocation::spec();
- break;
- case relocInfo::poll_type:
- case relocInfo::poll_return_type:
- _rspec = Relocation::spec_simple(rtype);
- break;
- case relocInfo::none:
- break;
- default:
- ShouldNotReachHere();
- break;
- }
-}
-
-// Implementation of Address
-
-Address Address::make_array(ArrayAddress adr) {
-#ifdef _LP64
- // Not implementable on 64bit machines
- // Should have been handled higher up the call chain.
- ShouldNotReachHere();
-#else
- AddressLiteral base = adr.base();
- Address index = adr.index();
- assert(index._disp == 0, "must not have disp"); // maybe it can?
- Address array(index._base, index._index, index._scale, (intptr_t) base.target());
- array._rspec = base._rspec;
- return array;
-#endif // _LP64
-}
-
-#ifndef _LP64
-
-// exceedingly dangerous constructor
-Address::Address(address loc, RelocationHolder spec) {
- _base = noreg;
- _index = noreg;
- _scale = no_scale;
- _disp = (intptr_t) loc;
- _rspec = spec;
-}
-#endif // _LP64
-
-// Convert the raw encoding form into the form expected by the constructor for
-// Address. An index of 4 (rsp) corresponds to having no index, so convert
-// that to noreg for the Address constructor.
-Address Address::make_raw(int base, int index, int scale, int disp) {
- bool valid_index = index != rsp->encoding();
- if (valid_index) {
- Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
- return madr;
- } else {
- Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
- return madr;
- }
-}
-
-// Implementation of Assembler
-
-int AbstractAssembler::code_fill_byte() {
- return (u_char)'\xF4'; // hlt
-}
-
-// make this go away someday
-void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
- if (rtype == relocInfo::none)
- emit_long(data);
- else emit_data(data, Relocation::spec_simple(rtype), format);
-}
-
-
-void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
- assert(imm32_operand == 0, "default format must be imm32 in this file");
- assert(inst_mark() != NULL, "must be inside InstructionMark");
- if (rspec.type() != relocInfo::none) {
- #ifdef ASSERT
- check_relocation(rspec, format);
- #endif
- // Do not use AbstractAssembler::relocate, which is not intended for
- // embedded words. Instead, relocate to the enclosing instruction.
-
- // hack. call32 is too wide for mask so use disp32
- if (format == call32_operand)
- code_section()->relocate(inst_mark(), rspec, disp32_operand);
- else
- code_section()->relocate(inst_mark(), rspec, format);
- }
- emit_long(data);
-}
-
-
-void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
- assert(dst->has_byte_register(), "must have byte register");
- assert(isByte(op1) && isByte(op2), "wrong opcode");
- assert(isByte(imm8), "not a byte");
- assert((op1 & 0x01) == 0, "should be 8bit operation");
- emit_byte(op1);
- emit_byte(op2 | dst->encoding());
- emit_byte(imm8);
-}
-
-
-void Assembler::emit_arith(int op1, int op2, Register dst, int imm32) {
- assert(isByte(op1) && isByte(op2), "wrong opcode");
- assert((op1 & 0x01) == 1, "should be 32bit operation");
- assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
- if (is8bit(imm32)) {
- emit_byte(op1 | 0x02); // set sign bit
- emit_byte(op2 | dst->encoding());
- emit_byte(imm32 & 0xFF);
- } else {
- emit_byte(op1);
- emit_byte(op2 | dst->encoding());
- emit_long(imm32);
- }
-}
-
-// immediate-to-memory forms
-void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int imm32) {
- assert((op1 & 0x01) == 1, "should be 32bit operation");
- assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
- if (is8bit(imm32)) {
- emit_byte(op1 | 0x02); // set sign bit
- emit_operand(rm,adr);
- emit_byte(imm32 & 0xFF);
- } else {
- emit_byte(op1);
- emit_operand(rm,adr);
- emit_long(imm32);
- }
-}
-
-void Assembler::emit_arith(int op1, int op2, Register dst, jobject obj) {
- assert(isByte(op1) && isByte(op2), "wrong opcode");
- assert((op1 & 0x01) == 1, "should be 32bit operation");
- assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
- InstructionMark im(this);
- emit_byte(op1);
- emit_byte(op2 | dst->encoding());
- emit_data((int)obj, relocInfo::oop_type, 0);
-}
-
-
-void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
- assert(isByte(op1) && isByte(op2), "wrong opcode");
- emit_byte(op1);
- emit_byte(op2 | dst->encoding() << 3 | src->encoding());
-}
-
-
-void Assembler::emit_operand(Register reg,
- Register base,
- Register index,
- Address::ScaleFactor scale,
- int disp,
- RelocationHolder const& rspec) {
-
- relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
- if (base->is_valid()) {
- if (index->is_valid()) {
- assert(scale != Address::no_scale, "inconsistent address");
- // [base + index*scale + disp]
- if (disp == 0 && rtype == relocInfo::none && base != rbp) {
- // [base + index*scale]
- // [00 reg 100][ss index base]
- assert(index != rsp, "illegal addressing mode");
- emit_byte(0x04 | reg->encoding() << 3);
- emit_byte(scale << 6 | index->encoding() << 3 | base->encoding());
- } else if (is8bit(disp) && rtype == relocInfo::none) {
- // [base + index*scale + imm8]
- // [01 reg 100][ss index base] imm8
- assert(index != rsp, "illegal addressing mode");
- emit_byte(0x44 | reg->encoding() << 3);
- emit_byte(scale << 6 | index->encoding() << 3 | base->encoding());
- emit_byte(disp & 0xFF);
- } else {
- // [base + index*scale + imm32]
- // [10 reg 100][ss index base] imm32
- assert(index != rsp, "illegal addressing mode");
- emit_byte(0x84 | reg->encoding() << 3);
- emit_byte(scale << 6 | index->encoding() << 3 | base->encoding());
- emit_data(disp, rspec, disp32_operand);
- }
- } else if (base == rsp) {
- // [esp + disp]
- if (disp == 0 && rtype == relocInfo::none) {
- // [esp]
- // [00 reg 100][00 100 100]
- emit_byte(0x04 | reg->encoding() << 3);
- emit_byte(0x24);
- } else if (is8bit(disp) && rtype == relocInfo::none) {
- // [esp + imm8]
- // [01 reg 100][00 100 100] imm8
- emit_byte(0x44 | reg->encoding() << 3);
- emit_byte(0x24);
- emit_byte(disp & 0xFF);
- } else {
- // [esp + imm32]
- // [10 reg 100][00 100 100] imm32
- emit_byte(0x84 | reg->encoding() << 3);
- emit_byte(0x24);
- emit_data(disp, rspec, disp32_operand);
- }
- } else {
- // [base + disp]
- assert(base != rsp, "illegal addressing mode");
- if (disp == 0 && rtype == relocInfo::none && base != rbp) {
- // [base]
- // [00 reg base]
- assert(base != rbp, "illegal addressing mode");
- emit_byte(0x00 | reg->encoding() << 3 | base->encoding());
- } else if (is8bit(disp) && rtype == relocInfo::none) {
- // [base + imm8]
- // [01 reg base] imm8
- emit_byte(0x40 | reg->encoding() << 3 | base->encoding());
- emit_byte(disp & 0xFF);
- } else {
- // [base + imm32]
- // [10 reg base] imm32
- emit_byte(0x80 | reg->encoding() << 3 | base->encoding());
- emit_data(disp, rspec, disp32_operand);
- }
- }
- } else {
- if (index->is_valid()) {
- assert(scale != Address::no_scale, "inconsistent address");
- // [index*scale + disp]
- // [00 reg 100][ss index 101] imm32
- assert(index != rsp, "illegal addressing mode");
- emit_byte(0x04 | reg->encoding() << 3);
- emit_byte(scale << 6 | index->encoding() << 3 | 0x05);
- emit_data(disp, rspec, disp32_operand);
- } else {
- // [disp]
- // [00 reg 101] imm32
- emit_byte(0x05 | reg->encoding() << 3);
- emit_data(disp, rspec, disp32_operand);
- }
- }
-}
-
-// Secret local extension to Assembler::WhichOperand:
-#define end_pc_operand (_WhichOperand_limit)
-
-address Assembler::locate_operand(address inst, WhichOperand which) {
- // Decode the given instruction, and return the address of
- // an embedded 32-bit operand word.
-
- // If "which" is disp32_operand, selects the displacement portion
- // of an effective address specifier.
- // If "which" is imm32_operand, selects the trailing immediate constant.
- // If "which" is call32_operand, selects the displacement of a call or jump.
- // Caller is responsible for ensuring that there is such an operand,
- // and that it is 32 bits wide.
-
- // If "which" is end_pc_operand, find the end of the instruction.
-
- address ip = inst;
-
- debug_only(bool has_imm32 = false);
- int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
-
- again_after_prefix:
- switch (0xFF & *ip++) {
-
- // These convenience macros generate groups of "case" labels for the switch.
- #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
- #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
- case (x)+4: case (x)+5: case (x)+6: case (x)+7
- #define REP16(x) REP8((x)+0): \
- case REP8((x)+8)
-
- case CS_segment:
- case SS_segment:
- case DS_segment:
- case ES_segment:
- case FS_segment:
- case GS_segment:
- assert(ip == inst+1, "only one prefix allowed");
- goto again_after_prefix;
-
- case 0xFF: // pushl a; decl a; incl a; call a; jmp a
- case 0x88: // movb a, r
- case 0x89: // movl a, r
- case 0x8A: // movb r, a
- case 0x8B: // movl r, a
- case 0x8F: // popl a
- break;
-
- case 0x68: // pushl #32(oop?)
- if (which == end_pc_operand) return ip + 4;
- assert(which == imm32_operand, "pushl has no disp32");
- return ip; // not produced by emit_operand
-
- case 0x66: // movw ... (size prefix)
- switch (0xFF & *ip++) {
- case 0x8B: // movw r, a
- case 0x89: // movw a, r
- break;
- case 0xC7: // movw a, #16
- tail_size = 2; // the imm16
- break;
- case 0x0F: // several SSE/SSE2 variants
- ip--; // reparse the 0x0F
- goto again_after_prefix;
- default:
- ShouldNotReachHere();
- }
- break;
-
- case REP8(0xB8): // movl r, #32(oop?)
- if (which == end_pc_operand) return ip + 4;
- assert(which == imm32_operand || which == disp32_operand, "");
- return ip;
-
- case 0x69: // imul r, a, #32
- case 0xC7: // movl a, #32(oop?)
- tail_size = 4;
- debug_only(has_imm32 = true); // has both kinds of operands!
- break;
-
- case 0x0F: // movx..., etc.
- switch (0xFF & *ip++) {
- case 0x12: // movlps
- case 0x28: // movaps
- case 0x2E: // ucomiss
- case 0x2F: // comiss
- case 0x54: // andps
- case 0x55: // andnps
- case 0x56: // orps
- case 0x57: // xorps
- case 0x6E: // movd
- case 0x7E: // movd
- case 0xAE: // ldmxcsr a
- // amd side says it these have both operands but that doesn't
- // appear to be true.
- // debug_only(has_imm32 = true); // has both kinds of operands!
- break;
-
- case 0xAD: // shrd r, a, %cl
- case 0xAF: // imul r, a
- case 0xBE: // movsxb r, a
- case 0xBF: // movsxw r, a
- case 0xB6: // movzxb r, a
- case 0xB7: // movzxw r, a
- case REP16(0x40): // cmovl cc, r, a
- case 0xB0: // cmpxchgb
- case 0xB1: // cmpxchg
- case 0xC1: // xaddl
- case 0xC7: // cmpxchg8
- case REP16(0x90): // setcc a
- // fall out of the switch to decode the address
- break;
- case 0xAC: // shrd r, a, #8
- tail_size = 1; // the imm8
- break;
- case REP16(0x80): // jcc rdisp32
- if (which == end_pc_operand) return ip + 4;
- assert(which == call32_operand, "jcc has no disp32 or imm32");
- return ip;
- default:
- ShouldNotReachHere();
- }
- break;
-
- case 0x81: // addl a, #32; addl r, #32
- // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
- // in the case of cmpl, the imm32 might be an oop
- tail_size = 4;
- debug_only(has_imm32 = true); // has both kinds of operands!
- break;
-
- case 0x85: // test r/m, r
- break;
-
- case 0x83: // addl a, #8; addl r, #8
- // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
- tail_size = 1;
- break;
-
- case 0x9B:
- switch (0xFF & *ip++) {
- case 0xD9: // fnstcw a
- break;
- default:
- ShouldNotReachHere();
- }
- break;
-
- case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
- case REP4(0x10): // adc...
- case REP4(0x20): // and...
- case REP4(0x30): // xor...
- case REP4(0x08): // or...
- case REP4(0x18): // sbb...
- case REP4(0x28): // sub...
- case REP4(0x38): // cmp...
- case 0xF7: // mull a
- case 0x8D: // leal r, a
- case 0x87: // xchg r, a
- break;
-
- case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
- case 0xC6: // movb a, #8
- case 0x80: // cmpb a, #8
- case 0x6B: // imul r, a, #8
- tail_size = 1; // the imm8
- break;
-
- case 0xE8: // call rdisp32
- case 0xE9: // jmp rdisp32
- if (which == end_pc_operand) return ip + 4;
- assert(which == call32_operand, "call has no disp32 or imm32");
- return ip;
-
- case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
- case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
- case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
- case 0xDD: // fld_d a; fst_d a; fstp_d a
- case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
- case 0xDF: // fild_d a; fistp_d a
- case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
- case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
- case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
- break;
-
- case 0xF3: // For SSE
- case 0xF2: // For SSE2
- ip++; ip++;
- break;
-
- default:
- ShouldNotReachHere();
-
- #undef REP8
- #undef REP16
- }
-
- assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
- assert(which != imm32_operand || has_imm32, "instruction has no imm32 field");
-
- // parse the output of emit_operand
- int op2 = 0xFF & *ip++;
- int base = op2 & 0x07;
- int op3 = -1;
- const int b100 = 4;
- const int b101 = 5;
- if (base == b100 && (op2 >> 6) != 3) {
- op3 = 0xFF & *ip++;
- base = op3 & 0x07; // refetch the base
- }
- // now ip points at the disp (if any)
-
- switch (op2 >> 6) {
- case 0:
- // [00 reg 100][ss index base]
- // [00 reg 100][00 100 rsp]
- // [00 reg base]
- // [00 reg 100][ss index 101][disp32]
- // [00 reg 101] [disp32]
-
- if (base == b101) {
- if (which == disp32_operand)
- return ip; // caller wants the disp32
- ip += 4; // skip the disp32
- }
- break;
-
- case 1:
- // [01 reg 100][ss index base][disp8]
- // [01 reg 100][00 100 rsp][disp8]
- // [01 reg base] [disp8]
- ip += 1; // skip the disp8
- break;
-
- case 2:
- // [10 reg 100][ss index base][disp32]
- // [10 reg 100][00 100 rsp][disp32]
- // [10 reg base] [disp32]
- if (which == disp32_operand)
- return ip; // caller wants the disp32
- ip += 4; // skip the disp32
- break;
-
- case 3:
- // [11 reg base] (not a memory addressing mode)
- break;
- }
-
- if (which == end_pc_operand) {
- return ip + tail_size;
- }
-
- assert(which == imm32_operand, "instruction has only an imm32 field");
- return ip;
-}
-
-address Assembler::locate_next_instruction(address inst) {
- // Secretly share code with locate_operand:
- return locate_operand(inst, end_pc_operand);
-}
-
-
-#ifdef ASSERT
-void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
- address inst = inst_mark();
- assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
- address opnd;
-
- Relocation* r = rspec.reloc();
- if (r->type() == relocInfo::none) {
- return;
- } else if (r->is_call() || format == call32_operand) {
- // assert(format == imm32_operand, "cannot specify a nonzero format");
- opnd = locate_operand(inst, call32_operand);
- } else if (r->is_data()) {
- assert(format == imm32_operand || format == disp32_operand, "format ok");
- opnd = locate_operand(inst, (WhichOperand)format);
- } else {
- assert(format == imm32_operand, "cannot specify a format");
- return;
- }
- assert(opnd == pc(), "must put operand where relocs can find it");
-}
-#endif
-
-
-
-void Assembler::emit_operand(Register reg, Address adr) {
- emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
-}
-
-
-void Assembler::emit_farith(int b1, int b2, int i) {
- assert(isByte(b1) && isByte(b2), "wrong opcode");
- assert(0 <= i && i < 8, "illegal stack offset");
- emit_byte(b1);
- emit_byte(b2 + i);
-}
-
-
-void Assembler::pushad() {
- emit_byte(0x60);
-}
-
-void Assembler::popad() {
- emit_byte(0x61);
-}
-
-void Assembler::pushfd() {
- emit_byte(0x9C);
-}
-
-void Assembler::popfd() {
- emit_byte(0x9D);
-}
-
-void Assembler::pushl(int imm32) {
- emit_byte(0x68);
- emit_long(imm32);
-}
-
-#ifndef _LP64
-void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
- InstructionMark im(this);
- emit_byte(0x68);
- emit_data(imm32, rspec, 0);
-}
-#endif // _LP64
-
-void Assembler::pushl(Register src) {
- emit_byte(0x50 | src->encoding());
-}
-
-
-void Assembler::pushl(Address src) {
- InstructionMark im(this);
- emit_byte(0xFF);
- emit_operand(rsi, src);
-}
-
-void Assembler::popl(Register dst) {
- emit_byte(0x58 | dst->encoding());
-}
-
-
-void Assembler::popl(Address dst) {
- InstructionMark im(this);
- emit_byte(0x8F);
- emit_operand(rax, dst);
-}
-
-
-void Assembler::prefix(Prefix p) {
- a_byte(p);
-}
-
-
-void Assembler::movb(Register dst, Address src) {
- assert(dst->has_byte_register(), "must have byte register");
- InstructionMark im(this);
- emit_byte(0x8A);
- emit_operand(dst, src);
-}
-
-
-void Assembler::movb(Address dst, int imm8) {
- InstructionMark im(this);
- emit_byte(0xC6);
- emit_operand(rax, dst);
- emit_byte(imm8);
-}
-
-
-void Assembler::movb(Address dst, Register src) {
- assert(src->has_byte_register(), "must have byte register");
- InstructionMark im(this);
- emit_byte(0x88);
- emit_operand(src, dst);
-}
-
-
-void Assembler::movw(Address dst, int imm16) {
- InstructionMark im(this);
-
- emit_byte(0x66); // switch to 16-bit mode
- emit_byte(0xC7);
- emit_operand(rax, dst);
- emit_word(imm16);
-}
-
-
-void Assembler::movw(Register dst, Address src) {
- InstructionMark im(this);
- emit_byte(0x66);
- emit_byte(0x8B);
- emit_operand(dst, src);
-}
-
-
-void Assembler::movw(Address dst, Register src) {
- InstructionMark im(this);
- emit_byte(0x66);
- emit_byte(0x89);
- emit_operand(src, dst);
-}
-
-
-void Assembler::movl(Register dst, int imm32) {
- emit_byte(0xB8 | dst->encoding());
- emit_long(imm32);
-}
-
-#ifndef _LP64
-void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
-
- InstructionMark im(this);
- emit_byte(0xB8 | dst->encoding());
- emit_data((int)imm32, rspec, 0);
-}
-#endif // _LP64
-
-void Assembler::movl(Register dst, Register src) {
- emit_byte(0x8B);
- emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding());
-}
-
-
-void Assembler::movl(Register dst, Address src) {
- InstructionMark im(this);
- emit_byte(0x8B);
- emit_operand(dst, src);
-}
-
-
-void Assembler::movl(Address dst, int imm32) {
- InstructionMark im(this);
- emit_byte(0xC7);
- emit_operand(rax, dst);
- emit_long(imm32);
-}
-
-#ifndef _LP64
-void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
- InstructionMark im(this);
- emit_byte(0xC7);
- emit_operand(rax, dst);
- emit_data((int)imm32, rspec, 0);
-}
-#endif // _LP64
-
-void Assembler::movl(Address dst, Register src) {
- InstructionMark im(this);
- emit_byte(0x89);
- emit_operand(src, dst);
-}
-
-void Assembler::movsxb(Register dst, Address src) {
- InstructionMark im(this);
- emit_byte(0x0F);
- emit_byte(0xBE);
- emit_operand(dst, src);
-}
-
-void Assembler::movsxb(Register dst, Register src) {
- assert(src->has_byte_register(), "must have byte register");
- emit_byte(0x0F);
- emit_byte(0xBE);
- emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding());
-}
-
-
-void Assembler::movsxw(Register dst, Address src) {
- InstructionMark im(this);
- emit_byte(0x0F);
- emit_byte(0xBF);
- emit_operand(dst, src);
-}
-
-
-void Assembler::movsxw(Register dst, Register src) {
- emit_byte(0x0F);
- emit_byte(0xBF);
- emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding());
-}
-
-
-void Assembler::movzxb(Register dst, Address src) {
- InstructionMark im(this);
- emit_byte(0x0F);
- emit_byte(0xB6);
- emit_operand(dst, src);
-}
-
-
-void Assembler::movzxb(Register dst, Register src) {
- assert(src->has_byte_register(), "must have byte register");
- emit_byte(0x0F);
- emit_byte(0xB6);
- emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding());
-}
-
-
-void Assembler::movzxw(Register dst, Address src) {
- InstructionMark im(this);
- emit_byte(0x0F);
- emit_byte(0xB7);
- emit_operand(dst, src);
-}
-
-
-void Assembler::movzxw(Register dst, Register src) {
- emit_byte(0x0F);
- emit_byte(0xB7);
- emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding());
-}
-
-
-void Assembler::cmovl(Condition cc, Register dst, Register src) {
- guarantee(VM_Version::supports_cmov(), "illegal instruction");
- emit_byte(0x0F);
- emit_byte(0x40 | cc);
- emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding());
-}
-
-
-void Assembler::cmovl(Condition cc, Register dst, Address src) {
- guarantee(VM_Version::supports_cmov(), "illegal instruction");
- // The code below seems to be wrong - however the manual is inconclusive
- // do not use for now (remember to enable all callers when fixing this)
- Unimplemented();
- // wrong bytes?
- InstructionMark im(this);
- emit_byte(0x0F);
- emit_byte(0x40 | cc);
- emit_operand(dst, src);
-}
-
-
-void Assembler::prefetcht0(Address src) {
- assert(VM_Version::supports_sse(), "must support");
- InstructionMark im(this);
- emit_byte(0x0F);
- emit_byte(0x18);
- emit_operand(rcx, src); // 1, src
-}
-
-
-void Assembler::prefetcht1(Address src) {
- assert(VM_Version::supports_sse(), "must support");
- InstructionMark im(this);
- emit_byte(0x0F);
- emit_byte(0x18);
- emit_operand(rdx, src); // 2, src
-}
-
-
-void Assembler::prefetcht2(Address src) {
- assert(VM_Version::supports_sse(), "must support");
- InstructionMark im(this);
- emit_byte(0x0F);
- emit_byte(0x18);
- emit_operand(rbx, src); // 3, src
-}
-
-
-void Assembler::prefetchnta(Address src) {
- assert(VM_Version::supports_sse2(), "must support");
- InstructionMark im(this);
- emit_byte(0x0F);
- emit_byte(0x18);
- emit_operand(rax, src); // 0, src
-}
-
-
-void Assembler::prefetchw(Address src) {
- assert(VM_Version::supports_3dnow(), "must support");
- InstructionMark im(this);
- emit_byte(0x0F);
- emit_byte(0x0D);
- emit_operand(rcx, src); // 1, src
-}
-
-
-void Assembler::prefetchr(Address src) {
- assert(VM_Version::supports_3dnow(), "must support");
- InstructionMark im(this);
- emit_byte(0x0F);
- emit_byte(0x0D);
- emit_operand(rax, src); // 0, src
-}
-
-
-void Assembler::adcl(Register dst, int imm32) {
- emit_arith(0x81, 0xD0, dst, imm32);
-}
-
-
-void Assembler::adcl(Register dst, Address src) {
- InstructionMark im(this);
- emit_byte(0x13);
- emit_operand(dst, src);
-}
-
-
-void Assembler::adcl(Register dst, Register src) {
- emit_arith(0x13, 0xC0, dst, src);
-}
-
-
-void Assembler::addl(Address dst, int imm32) {
- InstructionMark im(this);
- emit_arith_operand(0x81,rax,dst,imm32);
-}
-
-
-void Assembler::addl(Address dst, Register src) {
- InstructionMark im(this);
- emit_byte(0x01);
- emit_operand(src, dst);
-}
-
-
-void Assembler::addl(Register dst, int imm32) {
- emit_arith(0x81, 0xC0, dst, imm32);
-}
-
-
-void Assembler::addl(Register dst, Address src) {
- InstructionMark im(this);
- emit_byte(0x03);
- emit_operand(dst, src);
-}
-
-
-void Assembler::addl(Register dst, Register src) {
- emit_arith(0x03, 0xC0, dst, src);
-}
-
-
-void Assembler::andl(Register dst, int imm32) {
- emit_arith(0x81, 0xE0, dst, imm32);
-}
-
-
-void Assembler::andl(Register dst, Address src) {
- InstructionMark im(this);
- emit_byte(0x23);
- emit_operand(dst, src);
-}
-
-
-void Assembler::andl(Register dst, Register src) {
- emit_arith(0x23, 0xC0, dst, src);
-}
-
-
-void Assembler::cmpb(Address dst, int imm8) {
- InstructionMark im(this);
- emit_byte(0x80);
- emit_operand(rdi, dst);
- emit_byte(imm8);
-}
-
-void Assembler::cmpw(Address dst, int imm16) {
- InstructionMark im(this);
- emit_byte(0x66);
- emit_byte(0x81);
- emit_operand(rdi, dst);
- emit_word(imm16);
-}
-
-void Assembler::cmpl(Address dst, int imm32) {
- InstructionMark im(this);
- emit_byte(0x81);
- emit_operand(rdi, dst);
- emit_long(imm32);
-}
-
-#ifndef _LP64
-void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
- InstructionMark im(this);
- emit_byte(0x81);
- emit_byte(0xF8 | src1->encoding());
- emit_data(imm32, rspec, 0);
-}
-
-void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
- InstructionMark im(this);
- emit_byte(0x81);
- emit_operand(rdi, src1);
- emit_data(imm32, rspec, 0);
-}
-#endif // _LP64
-
-
-void Assembler::cmpl(Register dst, int imm32) {
- emit_arith(0x81, 0xF8, dst, imm32);
-}
-
-
-void Assembler::cmpl(Register dst, Register src) {
- emit_arith(0x3B, 0xC0, dst, src);
-}
-
-
-void Assembler::cmpl(Register dst, Address src) {
- InstructionMark im(this);
- emit_byte(0x3B);
- emit_operand(dst, src);
-}
-
-
-void Assembler::decl(Register dst) {
- // Don't use it directly. Use MacroAssembler::decrement() instead.
- emit_byte(0x48 | dst->encoding());
-}
-
-
-void Assembler::decl(Address dst) {
- // Don't use it directly. Use MacroAssembler::decrement() instead.
- InstructionMark im(this);
- emit_byte(0xFF);
- emit_operand(rcx, dst);
-}
-
-
-void Assembler::idivl(Register src) {
- emit_byte(0xF7);
- emit_byte(0xF8 | src->encoding());
-}
-
-
-void Assembler::cdql() {
- emit_byte(0x99);
-}
-
-
-void Assembler::imull(Register dst, Register src) {
- emit_byte(0x0F);
- emit_byte(0xAF);
- emit_byte(0xC0 | dst->encoding() << 3 | src->encoding());
-}
-
-
-void Assembler::imull(Register dst, Register src, int value) {
- if (is8bit(value)) {
- emit_byte(0x6B);
- emit_byte(0xC0 | dst->encoding() << 3 | src->encoding());
- emit_byte(value);
- } else {
- emit_byte(0x69);
- emit_byte(0xC0 | dst->encoding() << 3 | src->encoding());
- emit_long(value);
- }
-}
-
-
-void Assembler::incl(Register dst) {
- // Don't use it directly. Use MacroAssembler::increment() instead.
- emit_byte(0x40 | dst->encoding());
-}
-
-
-void Assembler::incl(Address dst) {
- // Don't use it directly. Use MacroAssembler::increment() instead.
- InstructionMark im(this);
- emit_byte(0xFF);
- emit_operand(rax, dst);
-}
-
-
-void Assembler::leal(Register dst, Address src) {
- InstructionMark im(this);
- emit_byte(0x8D);
- emit_operand(dst, src);
-}
-
-void Assembler::mull(Address src) {
- InstructionMark im(this);
- emit_byte(0xF7);
- emit_operand(rsp, src);
-}
-
-
-void Assembler::mull(Register src) {
- emit_byte(0xF7);
- emit_byte(0xE0 | src->encoding());
-}
-
-
-void Assembler::negl(Register dst) {
- emit_byte(0xF7);
- emit_byte(0xD8 | dst->encoding());
-}
-
-
-void Assembler::notl(Register dst) {
- emit_byte(0xF7);
- emit_byte(0xD0 | dst->encoding());
-}
-
-
-void Assembler::orl(Address dst, int imm32) {
- InstructionMark im(this);
- emit_byte(0x81);
- emit_operand(rcx, dst);
- emit_long(imm32);
-}
-
-void Assembler::orl(Register dst, int imm32) {
- emit_arith(0x81, 0xC8, dst, imm32);
-}
-
-
-void Assembler::orl(Register dst, Address src) {
- InstructionMark im(this);
- emit_byte(0x0B);
- emit_operand(dst, src);
-}
-
-
-void Assembler::orl(Register dst, Register src) {
- emit_arith(0x0B, 0xC0, dst, src);
-}
-
-
-void Assembler::rcll(Register dst, int imm8) {
- assert(isShiftCount(imm8), "illegal shift count");
- if (imm8 == 1) {
- emit_byte(0xD1);
- emit_byte(0xD0 | dst->encoding());
- } else {
- emit_byte(0xC1);
- emit_byte(0xD0 | dst->encoding());
- emit_byte(imm8);
- }
-}
-
-
-void Assembler::sarl(Register dst, int imm8) {
- assert(isShiftCount(imm8), "illegal shift count");
- if (imm8 == 1) {
- emit_byte(0xD1);
- emit_byte(0xF8 | dst->encoding());
- } else {
- emit_byte(0xC1);
- emit_byte(0xF8 | dst->encoding());
- emit_byte(imm8);
- }
-}
-
-
-void Assembler::sarl(Register dst) {
- emit_byte(0xD3);
- emit_byte(0xF8 | dst->encoding());
-}
-
-
-void Assembler::sbbl(Address dst, int imm32) {
- InstructionMark im(this);
- emit_arith_operand(0x81,rbx,dst,imm32);
-}
-
-
-void Assembler::sbbl(Register dst, int imm32) {
- emit_arith(0x81, 0xD8, dst, imm32);
-}
-
-
-void Assembler::sbbl(Register dst, Address src) {
- InstructionMark im(this);
- emit_byte(0x1B);
- emit_operand(dst, src);
-}
-
-
-void Assembler::sbbl(Register dst, Register src) {
- emit_arith(0x1B, 0xC0, dst, src);
-}
-
-
-void Assembler::shldl(Register dst, Register src) {
- emit_byte(0x0F);
- emit_byte(0xA5);
- emit_byte(0xC0 | src->encoding() << 3 | dst->encoding());
-}
-
-
-void Assembler::shll(Register dst, int imm8) {
- assert(isShiftCount(imm8), "illegal shift count");
- if (imm8 == 1 ) {
- emit_byte(0xD1);
- emit_byte(0xE0 | dst->encoding());
- } else {
- emit_byte(0xC1);
- emit_byte(0xE0 | dst->encoding());
- emit_byte(imm8);
- }
-}
-
-
-void Assembler::shll(Register dst) {
- emit_byte(0xD3);
- emit_byte(0xE0 | dst->encoding());
-}
-
-
-void Assembler::shrdl(Register dst, Register src) {
- emit_byte(0x0F);
- emit_byte(0xAD);
- emit_byte(0xC0 | src->encoding() << 3 | dst->encoding());
-}
-
-
-void Assembler::shrl(Register dst, int imm8) {
- assert(isShiftCount(imm8), "illegal shift count");
- emit_byte(0xC1);
- emit_byte(0xE8 | dst->encoding());
- emit_byte(imm8);
-}
-
-
-void Assembler::shrl(Register dst) {
- emit_byte(0xD3);
- emit_byte(0xE8 | dst->encoding());
-}
-
-
-void Assembler::subl(Address dst, int imm32) {
- if (is8bit(imm32)) {
- InstructionMark im(this);
- emit_byte(0x83);
- emit_operand(rbp, dst);
- emit_byte(imm32 & 0xFF);
- } else {
- InstructionMark im(this);
- emit_byte(0x81);
- emit_operand(rbp, dst);
- emit_long(imm32);
- }
-}
-
-
-void Assembler::subl(Register dst, int imm32) {
- emit_arith(0x81, 0xE8, dst, imm32);
-}
-
-
-void Assembler::subl(Address dst, Register src) {
- InstructionMark im(this);
- emit_byte(0x29);
- emit_operand(src, dst);
-}
-
-
-void Assembler::subl(Register dst, Address src) {
- InstructionMark im(this);
- emit_byte(0x2B);
- emit_operand(dst, src);
-}
-
-
-void Assembler::subl(Register dst, Register src) {
- emit_arith(0x2B, 0xC0, dst, src);
-}
-
-
-void Assembler::testb(Register dst, int imm8) {
- assert(dst->has_byte_register(), "must have byte register");
- emit_arith_b(0xF6, 0xC0, dst, imm8);
-}
-
-
-void Assembler::testl(Register dst, int imm32) {
- // not using emit_arith because test
- // doesn't support sign-extension of
- // 8bit operands
- if (dst->encoding() == 0) {
- emit_byte(0xA9);
- } else {
- emit_byte(0xF7);
- emit_byte(0xC0 | dst->encoding());
- }
- emit_long(imm32);
-}
-
-
-void Assembler::testl(Register dst, Register src) {
- emit_arith(0x85, 0xC0, dst, src);
-}
-
-void Assembler::testl(Register dst, Address src) {
- InstructionMark im(this);
- emit_byte(0x85);
- emit_operand(dst, src);
-}
-
-void Assembler::xaddl(Address dst, Register src) {
- InstructionMark im(this);
- emit_byte(0x0F);
- emit_byte(0xC1);
- emit_operand(src, dst);
-}
-
-void Assembler::xorl(Register dst, int imm32) {
- emit_arith(0x81, 0xF0, dst, imm32);
-}
-
-
-void Assembler::xorl(Register dst, Address src) {
- InstructionMark im(this);
- emit_byte(0x33);
- emit_operand(dst, src);
-}
-
-
-void Assembler::xorl(Register dst, Register src) {
- emit_arith(0x33, 0xC0, dst, src);
-}
-
-
-void Assembler::bswap(Register reg) {
- emit_byte(0x0F);
- emit_byte(0xC8 | reg->encoding());
-}
-
-
-void Assembler::lock() {
- if (Atomics & 1) {
- // Emit either nothing, a NOP, or a NOP: prefix
- emit_byte(0x90) ;
- } else {
- emit_byte(0xF0);
- }
-}
-
-
-void Assembler::xchg(Register reg, Address adr) {
- InstructionMark im(this);
- emit_byte(0x87);
- emit_operand(reg, adr);
-}
-
-
-void Assembler::xchgl(Register dst, Register src) {
- emit_byte(0x87);
- emit_byte(0xc0 | dst->encoding() << 3 | src->encoding());
-}
-
-
-// The 32-bit cmpxchg compares the value at adr with the contents of rax,
-// and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
-// The ZF is set if the compared values were equal, and cleared otherwise.
-void Assembler::cmpxchg(Register reg, Address adr) {
- if (Atomics & 2) {
- // caveat: no instructionmark, so this isn't relocatable.
- // Emit a synthetic, non-atomic, CAS equivalent.
- // Beware. The synthetic form sets all ICCs, not just ZF.
- // cmpxchg r,[m] is equivalent to rax, = CAS (m, rax, r)
- cmpl (rax, adr) ;
- movl (rax, adr) ;
- if (reg != rax) {
- Label L ;
- jcc (Assembler::notEqual, L) ;
- movl (adr, reg) ;
- bind (L) ;
- }
- } else {
- InstructionMark im(this);
- emit_byte(0x0F);
- emit_byte(0xB1);
- emit_operand(reg, adr);
- }
-}
-
-// The 64-bit cmpxchg compares the value at adr with the contents of rdx:rax,
-// and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
-// into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
-void Assembler::cmpxchg8(Address adr) {
- InstructionMark im(this);
- emit_byte(0x0F);
- emit_byte(0xc7);
- emit_operand(rcx, adr);
-}
-
-void Assembler::hlt() {
- emit_byte(0xF4);
-}
-
-
-void Assembler::addr_nop_4() {
- // 4 bytes: NOP DWORD PTR [EAX+0]
- emit_byte(0x0F);
- emit_byte(0x1F);
- emit_byte(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
- emit_byte(0); // 8-bits offset (1 byte)
-}
-
-void Assembler::addr_nop_5() {
- // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
- emit_byte(0x0F);
- emit_byte(0x1F);
- emit_byte(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
- emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
- emit_byte(0); // 8-bits offset (1 byte)
-}
-
-void Assembler::addr_nop_7() {
- // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
- emit_byte(0x0F);
- emit_byte(0x1F);
- emit_byte(0x80); // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
- emit_long(0); // 32-bits offset (4 bytes)
-}
-
-void Assembler::addr_nop_8() {
- // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
- emit_byte(0x0F);
- emit_byte(0x1F);
- emit_byte(0x84); // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
- emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
- emit_long(0); // 32-bits offset (4 bytes)
-}
-
-void Assembler::nop(int i) {
- assert(i > 0, " ");
- if (UseAddressNop && VM_Version::is_intel()) {
- //
- // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
- // 1: 0x90
- // 2: 0x66 0x90
- // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
- // 4: 0x0F 0x1F 0x40 0x00
- // 5: 0x0F 0x1F 0x44 0x00 0x00
- // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
- // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
- // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
- // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
- // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
- // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
-
- // The rest coding is Intel specific - don't use consecutive address nops
-
- // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
- // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
- // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
- // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
-
- while(i >= 15) {
- // For Intel don't generate consecutive addess nops (mix with regular nops)
- i -= 15;
- emit_byte(0x66); // size prefix
- emit_byte(0x66); // size prefix
- emit_byte(0x66); // size prefix
- addr_nop_8();
- emit_byte(0x66); // size prefix
- emit_byte(0x66); // size prefix
- emit_byte(0x66); // size prefix
- emit_byte(0x90); // nop
- }
- switch (i) {
- case 14:
- emit_byte(0x66); // size prefix
- case 13:
- emit_byte(0x66); // size prefix
- case 12:
- addr_nop_8();
- emit_byte(0x66); // size prefix
- emit_byte(0x66); // size prefix
- emit_byte(0x66); // size prefix
- emit_byte(0x90); // nop
- break;
- case 11:
- emit_byte(0x66); // size prefix
- case 10:
- emit_byte(0x66); // size prefix
- case 9:
- emit_byte(0x66); // size prefix
- case 8:
- addr_nop_8();
- break;
- case 7:
- addr_nop_7();
- break;
- case 6:
- emit_byte(0x66); // size prefix
- case 5:
- addr_nop_5();
- break;
- case 4:
- addr_nop_4();
- break;
- case 3:
- // Don't use "0x0F 0x1F 0x00" - need patching safe padding
- emit_byte(0x66); // size prefix
- case 2:
- emit_byte(0x66); // size prefix
- case 1:
- emit_byte(0x90); // nop
- break;
- default:
- assert(i == 0, " ");
- }
- return;
- }
- if (UseAddressNop && VM_Version::is_amd()) {
- //
- // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
- // 1: 0x90
- // 2: 0x66 0x90
- // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
- // 4: 0x0F 0x1F 0x40 0x00
- // 5: 0x0F 0x1F 0x44 0x00 0x00
- // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
- // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
- // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
- // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
- // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
- // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
-
- // The rest coding is AMD specific - use consecutive address nops
-
- // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
- // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
- // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
- // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
- // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
- // Size prefixes (0x66) are added for larger sizes
-
- while(i >= 22) {
- i -= 11;
- emit_byte(0x66); // size prefix
- emit_byte(0x66); // size prefix
- emit_byte(0x66); // size prefix
- addr_nop_8();
- }
- // Generate first nop for size between 21-12
- switch (i) {
- case 21:
- i -= 1;
- emit_byte(0x66); // size prefix
- case 20:
- case 19:
- i -= 1;
- emit_byte(0x66); // size prefix
- case 18:
- case 17:
- i -= 1;
- emit_byte(0x66); // size prefix
- case 16:
- case 15:
- i -= 8;
- addr_nop_8();
- break;
- case 14:
- case 13:
- i -= 7;
- addr_nop_7();
- break;
- case 12:
- i -= 6;
- emit_byte(0x66); // size prefix
- addr_nop_5();
- break;
- default:
- assert(i < 12, " ");
- }
-
- // Generate second nop for size between 11-1
- switch (i) {
- case 11:
- emit_byte(0x66); // size prefix
- case 10:
- emit_byte(0x66); // size prefix
- case 9:
- emit_byte(0x66); // size prefix
- case 8:
- addr_nop_8();
- break;
- case 7:
- addr_nop_7();
- break;
- case 6:
- emit_byte(0x66); // size prefix
- case 5:
- addr_nop_5();
- break;
- case 4:
- addr_nop_4();
- break;
- case 3:
- // Don't use "0x0F 0x1F 0x00" - need patching safe padding
- emit_byte(0x66); // size prefix
- case 2:
- emit_byte(0x66); // size prefix
- case 1:
- emit_byte(0x90); // nop
- break;
- default:
- assert(i == 0, " ");
- }
- return;
- }
-
- // Using nops with size prefixes "0x66 0x90".
- // From AMD Optimization Guide:
- // 1: 0x90
- // 2: 0x66 0x90
- // 3: 0x66 0x66 0x90
- // 4: 0x66 0x66 0x66 0x90
- // 5: 0x66 0x66 0x90 0x66 0x90
- // 6: 0x66 0x66 0x90 0x66 0x66 0x90
- // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
- // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
- // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
- // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
- //
- while(i > 12) {
- i -= 4;
- emit_byte(0x66); // size prefix
- emit_byte(0x66);
- emit_byte(0x66);
- emit_byte(0x90); // nop
- }
- // 1 - 12 nops
- if(i > 8) {
- if(i > 9) {
- i -= 1;
- emit_byte(0x66);
- }
- i -= 3;
- emit_byte(0x66);
- emit_byte(0x66);
- emit_byte(0x90);
- }
- // 1 - 8 nops
- if(i > 4) {
- if(i > 6) {
- i -= 1;
- emit_byte(0x66);
- }
- i -= 3;
- emit_byte(0x66);
- emit_byte(0x66);
- emit_byte(0x90);
- }
- switch (i) {
- case 4:
- emit_byte(0x66);
- case 3:
- emit_byte(0x66);
- case 2:
- emit_byte(0x66);
- case 1:
- emit_byte(0x90);
- break;
- default:
- assert(i == 0, " ");
- }
-}
-
-void Assembler::ret(int imm16) {
- if (imm16 == 0) {
- emit_byte(0xC3);
- } else {
- emit_byte(0xC2);
- emit_word(imm16);
- }
-}
-
-
-void Assembler::set_byte_if_not_zero(Register dst) {
- emit_byte(0x0F);
- emit_byte(0x95);
- emit_byte(0xE0 | dst->encoding());
-}
-
-
-// copies a single word from [esi] to [edi]
-void Assembler::smovl() {
- emit_byte(0xA5);
-}
-
-// copies data from [esi] to [edi] using rcx double words (m32)
-void Assembler::rep_movl() {
- emit_byte(0xF3);
- emit_byte(0xA5);
-}
-
-
-// sets rcx double words (m32) with rax, value at [edi]
-void Assembler::rep_set() {
- emit_byte(0xF3);
- emit_byte(0xAB);
-}
-
-// scans rcx double words (m32) at [edi] for occurance of rax,
-void Assembler::repne_scan() {
- emit_byte(0xF2);
- emit_byte(0xAF);
-}
-
-
-void Assembler::setb(Condition cc, Register dst) {
- assert(0 <= cc && cc < 16, "illegal cc");
- emit_byte(0x0F);
- emit_byte(0x90 | cc);
- emit_byte(0xC0 | dst->encoding());
-}
-
-void Assembler::cld() {
- emit_byte(0xfc);
-}
-
-void Assembler::std() {
- emit_byte(0xfd);
-}
-
-void Assembler::emit_raw (unsigned char b) {
- emit_byte (b) ;
-}
-
-// Serializes memory.
-void Assembler::membar() {
- // Memory barriers are only needed on multiprocessors
- if (os::is_MP()) {
- if( VM_Version::supports_sse2() ) {
- emit_byte( 0x0F ); // MFENCE; faster blows no regs
- emit_byte( 0xAE );
- emit_byte( 0xF0 );
- } else {
- // All usable chips support "locked" instructions which suffice
- // as barriers, and are much faster than the alternative of
- // using cpuid instruction. We use here a locked add [esp],0.
- // This is conveniently otherwise a no-op except for blowing
- // flags (which we save and restore.)
- pushfd(); // Save eflags register
- lock();
- addl(Address(rsp, 0), 0);// Assert the lock# signal here
- popfd(); // Restore eflags register
- }
- }
-}
-
-// Identify processor type and features
-void Assembler::cpuid() {
- // Note: we can't assert VM_Version::supports_cpuid() here
- // because this instruction is used in the processor
- // identification code.
- emit_byte( 0x0F );
- emit_byte( 0xA2 );
-}
-
-void Assembler::call(Label& L, relocInfo::relocType rtype) {
- if (L.is_bound()) {
- const int long_size = 5;
- int offs = target(L) - pc();
- assert(offs <= 0, "assembler error");
- InstructionMark im(this);
- // 1110 1000 #32-bit disp
- emit_byte(0xE8);
- emit_data(offs - long_size, rtype, 0);
- } else {
- InstructionMark im(this);
- // 1110 1000 #32-bit disp
- L.add_patch_at(code(), locator());
- emit_byte(0xE8);
- emit_data(int(0), rtype, 0);
- }
-}
-
-void Assembler::call(Register dst) {
- emit_byte(0xFF);
- emit_byte(0xD0 | dst->encoding());
-}
-
-
-void Assembler::call(Address adr) {
- InstructionMark im(this);
- relocInfo::relocType rtype = adr.reloc();
- if (rtype != relocInfo::runtime_call_type) {
- emit_byte(0xFF);
- emit_operand(rdx, adr);
- } else {
- assert(false, "ack");
- }
-
-}
-
-void Assembler::call_literal(address dest, RelocationHolder const& rspec) {
- InstructionMark im(this);
- emit_byte(0xE8);
- intptr_t disp = dest - (_code_pos + sizeof(int32_t));
- assert(dest != NULL, "must have a target");
- emit_data(disp, rspec, call32_operand);
-
-}
-
-void Assembler::jmp(Register entry) {
- emit_byte(0xFF);
- emit_byte(0xE0 | entry->encoding());
-}
-
-
-void Assembler::jmp(Address adr) {
- InstructionMark im(this);
- emit_byte(0xFF);
- emit_operand(rsp, adr);
-}
-
-void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
- InstructionMark im(this);
- emit_byte(0xE9);
- assert(dest != NULL, "must have a target");
- intptr_t disp = dest - (_code_pos + sizeof(int32_t));
- emit_data(disp, rspec.reloc(), call32_operand);
-}
-
-void Assembler::jmp(Label& L, relocInfo::relocType rtype) {
- if (L.is_bound()) {
- address entry = target(L);
- assert(entry != NULL, "jmp most probably wrong");
- InstructionMark im(this);
- const int short_size = 2;
- const int long_size = 5;
- intptr_t offs = entry - _code_pos;
- if (rtype == relocInfo::none && is8bit(offs - short_size)) {
- emit_byte(0xEB);
- emit_byte((offs - short_size) & 0xFF);
- } else {
- emit_byte(0xE9);
- emit_long(offs - long_size);
- }
- } else {
- // By default, forward jumps are always 32-bit displacements, since
- // we can't yet know where the label will be bound. If you're sure that
- // the forward jump will not run beyond 256 bytes, use jmpb to
- // force an 8-bit displacement.
- InstructionMark im(this);
- relocate(rtype);
- L.add_patch_at(code(), locator());
- emit_byte(0xE9);
- emit_long(0);
- }
-}
-
-void Assembler::jmpb(Label& L) {
- if (L.is_bound()) {
- const int short_size = 2;
- address entry = target(L);
- assert(is8bit((entry - _code_pos) + short_size),
- "Dispacement too large for a short jmp");
- assert(entry != NULL, "jmp most probably wrong");
- intptr_t offs = entry - _code_pos;
- emit_byte(0xEB);
- emit_byte((offs - short_size) & 0xFF);
- } else {
- InstructionMark im(this);
- L.add_patch_at(code(), locator());
- emit_byte(0xEB);
- emit_byte(0);
- }
-}
-
-void Assembler::jcc(Condition cc, Label& L, relocInfo::relocType rtype) {
- InstructionMark im(this);
- relocate(rtype);
- assert((0 <= cc) && (cc < 16), "illegal cc");
- if (L.is_bound()) {
- address dst = target(L);
- assert(dst != NULL, "jcc most probably wrong");
-
- const int short_size = 2;
- const int long_size = 6;
- int offs = (int)dst - ((int)_code_pos);
- if (rtype == relocInfo::none && is8bit(offs - short_size)) {
- // 0111 tttn #8-bit disp
- emit_byte(0x70 | cc);
- emit_byte((offs - short_size) & 0xFF);
- } else {
- // 0000 1111 1000 tttn #32-bit disp
- emit_byte(0x0F);
- emit_byte(0x80 | cc);
- emit_long(offs - long_size);
- }
- } else {
- // Note: could eliminate cond. jumps to this jump if condition
- // is the same however, seems to be rather unlikely case.
- // Note: use jccb() if label to be bound is very close to get
- // an 8-bit displacement
- L.add_patch_at(code(), locator());
- emit_byte(0x0F);
- emit_byte(0x80 | cc);
- emit_long(0);
- }
-}
-
-void Assembler::jccb(Condition cc, Label& L) {
- if (L.is_bound()) {
- const int short_size = 2;
- address entry = target(L);
- assert(is8bit((intptr_t)entry - ((intptr_t)_code_pos + short_size)),
- "Dispacement too large for a short jmp");
- intptr_t offs = (intptr_t)entry - (intptr_t)_code_pos;
- // 0111 tttn #8-bit disp
- emit_byte(0x70 | cc);
- emit_byte((offs - short_size) & 0xFF);
- jcc(cc, L);
- } else {
- InstructionMark im(this);
- L.add_patch_at(code(), locator());
- emit_byte(0x70 | cc);
- emit_byte(0);
- }
-}
-
-// FPU instructions
-
-void Assembler::fld1() {
- emit_byte(0xD9);
- emit_byte(0xE8);
-}
-
-
-void Assembler::fldz() {
- emit_byte(0xD9);
- emit_byte(0xEE);
-}
-
-
-void Assembler::fld_s(Address adr) {
- InstructionMark im(this);
- emit_byte(0xD9);
- emit_operand(rax, adr);
-}
-
-
-void Assembler::fld_s (int index) {
- emit_farith(0xD9, 0xC0, index);
-}
-
-
-void Assembler::fld_d(Address adr) {
- InstructionMark im(this);
- emit_byte(0xDD);
- emit_operand(rax, adr);
-}
-
-
-void Assembler::fld_x(Address adr) {
- InstructionMark im(this);
- emit_byte(0xDB);
- emit_operand(rbp, adr);
-}
-
-
-void Assembler::fst_s(Address adr) {
- InstructionMark im(this);
- emit_byte(0xD9);
- emit_operand(rdx, adr);
-}
-
-
-void Assembler::fst_d(Address adr) {
- InstructionMark im(this);
- emit_byte(0xDD);
- emit_operand(rdx, adr);
-}
-
-
-void Assembler::fstp_s(Address adr) {
- InstructionMark im(this);
- emit_byte(0xD9);
- emit_operand(rbx, adr);
-}
-
-
-void Assembler::fstp_d(Address adr) {
- InstructionMark im(this);
- emit_byte(0xDD);
- emit_operand(rbx, adr);
-}
-
-
-void Assembler::fstp_x(Address adr) {
- InstructionMark im(this);
- emit_byte(0xDB);
- emit_operand(rdi, adr);
-}
-
-
-void Assembler::fstp_d(int index) {
- emit_farith(0xDD, 0xD8, index);
-}
-
-
-void Assembler::fild_s(Address adr) {
- InstructionMark im(this);
- emit_byte(0xDB);
- emit_operand(rax, adr);
-}
-
-
-void Assembler::fild_d(Address adr) {
- InstructionMark im(this);
- emit_byte(0xDF);
- emit_operand(rbp, adr);
-}
-
-
-void Assembler::fistp_s(Address adr) {
- InstructionMark im(this);
- emit_byte(0xDB);
- emit_operand(rbx, adr);
-}
-
-
-void Assembler::fistp_d(Address adr) {
- InstructionMark im(this);
- emit_byte(0xDF);
- emit_operand(rdi, adr);
-}
-
-
-void Assembler::fist_s(Address adr) {
- InstructionMark im(this);
- emit_byte(0xDB);
- emit_operand(rdx, adr);
-}
-
-
-void Assembler::fabs() {
- emit_byte(0xD9);
- emit_byte(0xE1);
-}
-
-
-void Assembler::fldln2() {
- emit_byte(0xD9);
- emit_byte(0xED);
-}
-
-void Assembler::fyl2x() {
- emit_byte(0xD9);
- emit_byte(0xF1);
-}
-
-
-void Assembler::fldlg2() {
- emit_byte(0xD9);
- emit_byte(0xEC);
-}
-
-
-void Assembler::flog() {
- fldln2();
- fxch();
- fyl2x();
-}
-
-
-void Assembler::flog10() {
- fldlg2();
- fxch();
- fyl2x();
-}
-
-
-void Assembler::fsin() {
- emit_byte(0xD9);
- emit_byte(0xFE);
-}
-
-
-void Assembler::fcos() {
- emit_byte(0xD9);
- emit_byte(0xFF);
-}
-
-void Assembler::ftan() {
- emit_byte(0xD9);
- emit_byte(0xF2);
- emit_byte(0xDD);
- emit_byte(0xD8);
-}
-
-void Assembler::fsqrt() {
- emit_byte(0xD9);
- emit_byte(0xFA);
-}
-
-
-void Assembler::fchs() {
- emit_byte(0xD9);
- emit_byte(0xE0);
-}
-
-
-void Assembler::fadd_s(Address src) {
- InstructionMark im(this);
- emit_byte(0xD8);
- emit_operand(rax, src);
-}
-
-
-void Assembler::fadd_d(Address src) {
- InstructionMark im(this);
- emit_byte(0xDC);
- emit_operand(rax, src);
-}
-
-
-void Assembler::fadd(int i) {
- emit_farith(0xD8, 0xC0, i);
-}
-
-
-void Assembler::fadda(int i) {
- emit_farith(0xDC, 0xC0, i);
-}
-
-
-void Assembler::fsub_d(Address src) {
- InstructionMark im(this);
- emit_byte(0xDC);
- emit_operand(rsp, src);
-}
-
-
-void Assembler::fsub_s(Address src) {
- InstructionMark im(this);
- emit_byte(0xD8);
- emit_operand(rsp, src);
-}
-
-
-void Assembler::fsubr_s(Address src) {
- InstructionMark im(this);
- emit_byte(0xD8);
- emit_operand(rbp, src);
-}
-
-
-void Assembler::fsubr_d(Address src) {
- InstructionMark im(this);
- emit_byte(0xDC);
- emit_operand(rbp, src);
-}
-
-
-void Assembler::fmul_s(Address src) {
- InstructionMark im(this);
- emit_byte(0xD8);
- emit_operand(rcx, src);
-}
-
-
-void Assembler::fmul_d(Address src) {
- InstructionMark im(this);
- emit_byte(0xDC);
- emit_operand(rcx, src);
-}
-
-
-void Assembler::fmul(int i) {
- emit_farith(0xD8, 0xC8, i);
-}
-
-
-void Assembler::fmula(int i) {
- emit_farith(0xDC, 0xC8, i);
-}
-
-
-void Assembler::fdiv_s(Address src) {
- InstructionMark im(this);
- emit_byte(0xD8);
- emit_operand(rsi, src);
-}
-
-
-void Assembler::fdiv_d(Address src) {
- InstructionMark im(this);
- emit_byte(0xDC);
- emit_operand(rsi, src);
-}
-
-
-void Assembler::fdivr_s(Address src) {
- InstructionMark im(this);
- emit_byte(0xD8);
- emit_operand(rdi, src);
-}
-
-
-void Assembler::fdivr_d(Address src) {
- InstructionMark im(this);
- emit_byte(0xDC);
- emit_operand(rdi, src);
-}
-
-
-void Assembler::fsub(int i) {
- emit_farith(0xD8, 0xE0, i);
-}
-
-
-void Assembler::fsuba(int i) {
- emit_farith(0xDC, 0xE8, i);
-}
-
-
-void Assembler::fsubr(int i) {
- emit_farith(0xD8, 0xE8, i);
-}
-
-
-void Assembler::fsubra(int i) {
- emit_farith(0xDC, 0xE0, i);
-}
-
-
-void Assembler::fdiv(int i) {
- emit_farith(0xD8, 0xF0, i);
-}
-
-
-void Assembler::fdiva(int i) {
- emit_farith(0xDC, 0xF8, i);
-}
-
-
-void Assembler::fdivr(int i) {
- emit_farith(0xD8, 0xF8, i);
-}
-
-
-void Assembler::fdivra(int i) {
- emit_farith(0xDC, 0xF0, i);
-}
-
-
-// Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
-// is erroneous for some of the floating-point instructions below.
-
-void Assembler::fdivp(int i) {
- emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
-}
-
-
-void Assembler::fdivrp(int i) {
- emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
-}
-
-
-void Assembler::fsubp(int i) {
- emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
-}
-
-
-void Assembler::fsubrp(int i) {
- emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
-}
-
-
-void Assembler::faddp(int i) {
- emit_farith(0xDE, 0xC0, i);
-}
-
-
-void Assembler::fmulp(int i) {
- emit_farith(0xDE, 0xC8, i);
-}
-
-
-void Assembler::fprem() {
- emit_byte(0xD9);
- emit_byte(0xF8);
-}
-
-
-void Assembler::fprem1() {
- emit_byte(0xD9);
- emit_byte(0xF5);
-}
-
-
-void Assembler::fxch(int i) {
- emit_farith(0xD9, 0xC8, i);
-}
-
-
-void Assembler::fincstp() {
- emit_byte(0xD9);
- emit_byte(0xF7);
-}
-
-
-void Assembler::fdecstp() {
- emit_byte(0xD9);
- emit_byte(0xF6);
-}
-
-
-void Assembler::ffree(int i) {
- emit_farith(0xDD, 0xC0, i);
-}
-
-
-void Assembler::fcomp_s(Address src) {
- InstructionMark im(this);
- emit_byte(0xD8);
- emit_operand(rbx, src);
-}
-
-
-void Assembler::fcomp_d(Address src) {
- InstructionMark im(this);
- emit_byte(0xDC);
- emit_operand(rbx, src);
-}
-
-
-void Assembler::fcom(int i) {
- emit_farith(0xD8, 0xD0, i);
-}
-
-
-void Assembler::fcomp(int i) {
- emit_farith(0xD8, 0xD8, i);
-}
-
-
-void Assembler::fcompp() {
- emit_byte(0xDE);
- emit_byte(0xD9);
-}
-
-
-void Assembler::fucomi(int i) {
- // make sure the instruction is supported (introduced for P6, together with cmov)
- guarantee(VM_Version::supports_cmov(), "illegal instruction");
- emit_farith(0xDB, 0xE8, i);
-}
-
-
-void Assembler::fucomip(int i) {
- // make sure the instruction is supported (introduced for P6, together with cmov)
- guarantee(VM_Version::supports_cmov(), "illegal instruction");
- emit_farith(0xDF, 0xE8, i);
-}
-
-
-void Assembler::ftst() {
- emit_byte(0xD9);
- emit_byte(0xE4);
-}
-
-
-void Assembler::fnstsw_ax() {
- emit_byte(0xdF);
- emit_byte(0xE0);
-}
-
-
-void Assembler::fwait() {
- emit_byte(0x9B);
-}
-
-
-void Assembler::finit() {
- emit_byte(0x9B);
- emit_byte(0xDB);
- emit_byte(0xE3);
-}
-
-
-void Assembler::fldcw(Address src) {
- InstructionMark im(this);
- emit_byte(0xd9);
- emit_operand(rbp, src);
-}
-
-
-void Assembler::fnstcw(Address src) {
- InstructionMark im(this);
- emit_byte(0x9B);
- emit_byte(0xD9);
- emit_operand(rdi, src);
-}
-
-void Assembler::fnsave(Address dst) {
- InstructionMark im(this);
- emit_byte(0xDD);
- emit_operand(rsi, dst);
-}
-
-
-void Assembler::frstor(Address src) {
- InstructionMark im(this);
- emit_byte(0xDD);
- emit_operand(rsp, src);
-}
-
-
-void Assembler::fldenv(Address src) {
- InstructionMark im(this);
- emit_byte(0xD9);
- emit_operand(rsp, src);
-}
-
-
-void Assembler::sahf() {
- emit_byte(0x9E);
-}
-
-// MMX operations
-void Assembler::emit_operand(MMXRegister reg, Address adr) {
- emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
-}
-
-void Assembler::movq( MMXRegister dst, Address src ) {
- assert( VM_Version::supports_mmx(), "" );
- emit_byte(0x0F);
- emit_byte(0x6F);
- emit_operand(dst,src);
-}
-
-void Assembler::movq( Address dst, MMXRegister src ) {
- assert( VM_Version::supports_mmx(), "" );
- emit_byte(0x0F);
- emit_byte(0x7F);
- emit_operand(src,dst);
-}
-
-void Assembler::emms() {
- emit_byte(0x0F);
- emit_byte(0x77);
-}
-
-
-
-
-// SSE and SSE2 instructions
-inline void Assembler::emit_sse_operand(XMMRegister reg, Address adr) {
- assert(((Register)reg)->encoding() == reg->encoding(), "otherwise typecast is invalid");
- emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
-}
-inline void Assembler::emit_sse_operand(Register reg, Address adr) {
- emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
-}
-
-inline void Assembler::emit_sse_operand(XMMRegister dst, XMMRegister src) {
- emit_byte(0xC0 | dst->encoding() << 3 | src->encoding());
-}
-inline void Assembler::emit_sse_operand(XMMRegister dst, Register src) {
- emit_byte(0xC0 | dst->encoding() << 3 | src->encoding());
-}
-inline void Assembler::emit_sse_operand(Register dst, XMMRegister src) {
- emit_byte(0xC0 | dst->encoding() << 3 | src->encoding());
-}
-
-
-// Macro for creation of SSE2 instructions
-// The SSE2 instricution set is highly regular, so this macro saves
-// a lot of cut&paste
-// Each macro expansion creates two methods (same name with different
-// parameter list)
-//
-// Macro parameters:
-// * name: name of the created methods
-// * sse_version: either sse or sse2 for the assertion if instruction supported by processor
-// * prefix: first opcode byte of the instruction (or 0 if no prefix byte)
-// * opcode: last opcode byte of the instruction
-// * conversion instruction have parameters of type Register instead of XMMRegister,
-// so this can also configured with macro parameters
-#define emit_sse_instruction(name, sse_version, prefix, opcode, dst_register_type, src_register_type) \
- \
- void Assembler:: name (dst_register_type dst, Address src) { \
- assert(VM_Version::supports_##sse_version(), ""); \
- \
- InstructionMark im(this); \
- if (prefix != 0) emit_byte(prefix); \
- emit_byte(0x0F); \
- emit_byte(opcode); \
- emit_sse_operand(dst, src); \
- } \
- \
- void Assembler:: name (dst_register_type dst, src_register_type src) { \
- assert(VM_Version::supports_##sse_version(), ""); \
- \
- if (prefix != 0) emit_byte(prefix); \
- emit_byte(0x0F); \
- emit_byte(opcode); \
- emit_sse_operand(dst, src); \
- } \
-
-emit_sse_instruction(addss, sse, 0xF3, 0x58, XMMRegister, XMMRegister);
-emit_sse_instruction(addsd, sse2, 0xF2, 0x58, XMMRegister, XMMRegister)
-emit_sse_instruction(subss, sse, 0xF3, 0x5C, XMMRegister, XMMRegister)
-emit_sse_instruction(subsd, sse2, 0xF2, 0x5C, XMMRegister, XMMRegister)
-emit_sse_instruction(mulss, sse, 0xF3, 0x59, XMMRegister, XMMRegister)
-emit_sse_instruction(mulsd, sse2, 0xF2, 0x59, XMMRegister, XMMRegister)
-emit_sse_instruction(divss, sse, 0xF3, 0x5E, XMMRegister, XMMRegister)
-emit_sse_instruction(divsd, sse2, 0xF2, 0x5E, XMMRegister, XMMRegister)
-emit_sse_instruction(sqrtss, sse, 0xF3, 0x51, XMMRegister, XMMRegister)
-emit_sse_instruction(sqrtsd, sse2, 0xF2, 0x51, XMMRegister, XMMRegister)
-
-emit_sse_instruction(pxor, sse2, 0x66, 0xEF, XMMRegister, XMMRegister)
-
-emit_sse_instruction(comiss, sse, 0, 0x2F, XMMRegister, XMMRegister)
-emit_sse_instruction(comisd, sse2, 0x66, 0x2F, XMMRegister, XMMRegister)
-emit_sse_instruction(ucomiss, sse, 0, 0x2E, XMMRegister, XMMRegister)
-emit_sse_instruction(ucomisd, sse2, 0x66, 0x2E, XMMRegister, XMMRegister)
-
-emit_sse_instruction(cvtss2sd, sse2, 0xF3, 0x5A, XMMRegister, XMMRegister);
-emit_sse_instruction(cvtsd2ss, sse2, 0xF2, 0x5A, XMMRegister, XMMRegister)
-emit_sse_instruction(cvtsi2ss, sse, 0xF3, 0x2A, XMMRegister, Register);
-emit_sse_instruction(cvtsi2sd, sse2, 0xF2, 0x2A, XMMRegister, Register)
-emit_sse_instruction(cvtss2si, sse, 0xF3, 0x2D, Register, XMMRegister);
-emit_sse_instruction(cvtsd2si, sse2, 0xF2, 0x2D, Register, XMMRegister)
-emit_sse_instruction(cvttss2si, sse, 0xF3, 0x2C, Register, XMMRegister);
-emit_sse_instruction(cvttsd2si, sse2, 0xF2, 0x2C, Register, XMMRegister)
-
-emit_sse_instruction(movss, sse, 0xF3, 0x10, XMMRegister, XMMRegister)
-emit_sse_instruction(movsd, sse2, 0xF2, 0x10, XMMRegister, XMMRegister)
-
-emit_sse_instruction(movq, sse2, 0xF3, 0x7E, XMMRegister, XMMRegister);
-emit_sse_instruction(movd, sse2, 0x66, 0x6E, XMMRegister, Register);
-emit_sse_instruction(movdqa, sse2, 0x66, 0x6F, XMMRegister, XMMRegister);
-
-emit_sse_instruction(punpcklbw, sse2, 0x66, 0x60, XMMRegister, XMMRegister);
-
-
-// Instruction not covered by macro
-void Assembler::movq(Address dst, XMMRegister src) {
- assert(VM_Version::supports_sse2(), "");
-
- InstructionMark im(this);
- emit_byte(0x66);
- emit_byte(0x0F);
- emit_byte(0xD6);
- emit_sse_operand(src, dst);
-}
-
-void Assembler::movd(Address dst, XMMRegister src) {
- assert(VM_Version::supports_sse2(), "");
-
- InstructionMark im(this);
- emit_byte(0x66);
- emit_byte(0x0F);
- emit_byte(0x7E);
- emit_sse_operand(src, dst);
-}
-
-void Assembler::movd(Register dst, XMMRegister src) {
- assert(VM_Version::supports_sse2(), "");
-
- emit_byte(0x66);
- emit_byte(0x0F);
- emit_byte(0x7E);
- emit_sse_operand(src, dst);
-}
-
-void Assembler::movdqa(Address dst, XMMRegister src) {
- assert(VM_Version::supports_sse2(), "");
-
- InstructionMark im(this);
- emit_byte(0x66);
- emit_byte(0x0F);
- emit_byte(0x7F);
- emit_sse_operand(src, dst);
-}
-
-void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
- assert(isByte(mode), "invalid value");
- assert(VM_Version::supports_sse2(), "");
-
- emit_byte(0x66);
- emit_byte(0x0F);
- emit_byte(0x70);
- emit_sse_operand(dst, src);
- emit_byte(mode & 0xFF);
-}
-
-void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
- assert(isByte(mode), "invalid value");
- assert(VM_Version::supports_sse2(), "");
-
- InstructionMark im(this);
- emit_byte(0x66);
- emit_byte(0x0F);
- emit_byte(0x70);
- emit_sse_operand(dst, src);
- emit_byte(mode & 0xFF);
-}
-
-void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
- assert(isByte(mode), "invalid value");
- assert(VM_Version::supports_sse2(), "");
-
- emit_byte(0xF2);
- emit_byte(0x0F);
- emit_byte(0x70);
- emit_sse_operand(dst, src);
- emit_byte(mode & 0xFF);
-}
-
-void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
- assert(isByte(mode), "invalid value");
- assert(VM_Version::supports_sse2(), "");
-
- InstructionMark im(this);
- emit_byte(0xF2);
- emit_byte(0x0F);
- emit_byte(0x70);
- emit_sse_operand(dst, src);
- emit_byte(mode & 0xFF);
-}
-
-void Assembler::psrlq(XMMRegister dst, int shift) {
- assert(VM_Version::supports_sse2(), "");
-
- emit_byte(0x66);
- emit_byte(0x0F);
- emit_byte(0x73);
- emit_sse_operand(xmm2, dst);
- emit_byte(shift);
-}
-
-void Assembler::movss( Address dst, XMMRegister src ) {
- assert(VM_Version::supports_sse(), "");
-
- InstructionMark im(this);
- emit_byte(0xF3); // single
- emit_byte(0x0F);
- emit_byte(0x11); // store
- emit_sse_operand(src, dst);
-}
-
-void Assembler::movsd( Address dst, XMMRegister src ) {
- assert(VM_Version::supports_sse2(), "");
-
- InstructionMark im(this);
- emit_byte(0xF2); // double
- emit_byte(0x0F);
- emit_byte(0x11); // store
- emit_sse_operand(src,dst);
-}
-
-// New cpus require to use movaps and movapd to avoid partial register stall
-// when moving between registers.
-void Assembler::movaps(XMMRegister dst, XMMRegister src) {
- assert(VM_Version::supports_sse(), "");
-
- emit_byte(0x0F);
- emit_byte(0x28);
- emit_sse_operand(dst, src);
-}
-void Assembler::movapd(XMMRegister dst, XMMRegister src) {
- assert(VM_Version::supports_sse2(), "");
-
- emit_byte(0x66);
- emit_byte(0x0F);
- emit_byte(0x28);
- emit_sse_operand(dst, src);
-}
-
-// New cpus require to use movsd and movss to avoid partial register stall
-// when loading from memory. But for old Opteron use movlpd instead of movsd.
-// The selection is done in MacroAssembler::movdbl() and movflt().
-void Assembler::movlpd(XMMRegister dst, Address src) {
- assert(VM_Version::supports_sse(), "");
-
- InstructionMark im(this);
- emit_byte(0x66);
- emit_byte(0x0F);
- emit_byte(0x12);
- emit_sse_operand(dst, src);
-}
-
-void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
- assert(VM_Version::supports_sse2(), "");
-
- emit_byte(0xF3);
- emit_byte(0x0F);
- emit_byte(0xE6);
- emit_sse_operand(dst, src);
-}
-
-void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
- assert(VM_Version::supports_sse2(), "");
-
- emit_byte(0x0F);
- emit_byte(0x5B);
- emit_sse_operand(dst, src);
-}
-
-emit_sse_instruction(andps, sse, 0, 0x54, XMMRegister, XMMRegister);
-emit_sse_instruction(andpd, sse2, 0x66, 0x54, XMMRegister, XMMRegister);
-emit_sse_instruction(andnps, sse, 0, 0x55, XMMRegister, XMMRegister);
-emit_sse_instruction(andnpd, sse2, 0x66, 0x55, XMMRegister, XMMRegister);
-emit_sse_instruction(orps, sse, 0, 0x56, XMMRegister, XMMRegister);
-emit_sse_instruction(orpd, sse2, 0x66, 0x56, XMMRegister, XMMRegister);
-emit_sse_instruction(xorps, sse, 0, 0x57, XMMRegister, XMMRegister);
-emit_sse_instruction(xorpd, sse2, 0x66, 0x57, XMMRegister, XMMRegister);
-
-
-void Assembler::ldmxcsr( Address src) {
- InstructionMark im(this);
- emit_byte(0x0F);
- emit_byte(0xAE);
- emit_operand(rdx /* 2 */, src);
-}
-
-void Assembler::stmxcsr( Address dst) {
- InstructionMark im(this);
- emit_byte(0x0F);
- emit_byte(0xAE);
- emit_operand(rbx /* 3 */, dst);
-}
-
-// Implementation of MacroAssembler
-
-Address MacroAssembler::as_Address(AddressLiteral adr) {
- // amd64 always does this as a pc-rel
- // we can be absolute or disp based on the instruction type
- // jmp/call are displacements others are absolute
- assert(!adr.is_lval(), "must be rval");
-
- return Address(adr.target(), adr.rspec());
-}
-
-Address MacroAssembler::as_Address(ArrayAddress adr) {
- return Address::make_array(adr);
-}
-
-void MacroAssembler::fat_nop() {
- // A 5 byte nop that is safe for patching (see patch_verified_entry)
- emit_byte(0x26); // es:
- emit_byte(0x2e); // cs:
- emit_byte(0x64); // fs:
- emit_byte(0x65); // gs:
- emit_byte(0x90);
-}
-
-// 32bit can do a case table jump in one instruction but we no longer allow the base
-// to be installed in the Address class
-void MacroAssembler::jump(ArrayAddress entry) {
- jmp(as_Address(entry));
-}
-
-void MacroAssembler::jump(AddressLiteral dst) {
- jmp_literal(dst.target(), dst.rspec());
-}
-
-void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
- assert((0 <= cc) && (cc < 16), "illegal cc");
-
- InstructionMark im(this);
-
- relocInfo::relocType rtype = dst.reloc();
- relocate(rtype);
- const int short_size = 2;
- const int long_size = 6;
- int offs = (int)dst.target() - ((int)_code_pos);
- if (rtype == relocInfo::none && is8bit(offs - short_size)) {
- // 0111 tttn #8-bit disp
- emit_byte(0x70 | cc);
- emit_byte((offs - short_size) & 0xFF);
- } else {
- // 0000 1111 1000 tttn #32-bit disp
- emit_byte(0x0F);
- emit_byte(0x80 | cc);
- emit_long(offs - long_size);
- }
-}
-
-// Calls
-void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
- Assembler::call(L, rtype);
-}
-
-void MacroAssembler::call(Register entry) {
- Assembler::call(entry);
-}
-
-void MacroAssembler::call(AddressLiteral entry) {
- Assembler::call_literal(entry.target(), entry.rspec());
-}
-
-
-void MacroAssembler::cmp8(AddressLiteral src1, int8_t imm) {
- Assembler::cmpb(as_Address(src1), imm);
-}
-
-void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
- Assembler::cmpl(as_Address(src1), imm);
-}
-
-void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
- if (src2.is_lval()) {
- cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
- } else {
- Assembler::cmpl(src1, as_Address(src2));
- }
-}
-
-void MacroAssembler::cmp32(Register src1, int32_t imm) {
- Assembler::cmpl(src1, imm);
-}
-
-void MacroAssembler::cmp32(Register src1, Address src2) {
- Assembler::cmpl(src1, src2);
-}
-
-void MacroAssembler::cmpoop(Address src1, jobject obj) {
- cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
-}
-
-void MacroAssembler::cmpoop(Register src1, jobject obj) {
- cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
-}
-
-void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
- if (src2.is_lval()) {
- // compare the effect address of src2 to src1
- cmp_literal32(src1, (int32_t)src2.target(), src2.rspec());
- } else {
- Assembler::cmpl(src1, as_Address(src2));
- }
-}
-
-void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
- assert(src2.is_lval(), "not a mem-mem compare");
- cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
-}
-
-
-void MacroAssembler::cmpxchgptr(Register reg, AddressLiteral adr) {
- cmpxchg(reg, as_Address(adr));
-}
-
-void MacroAssembler::increment(AddressLiteral dst) {
- increment(as_Address(dst));
-}
-
-void MacroAssembler::increment(ArrayAddress dst) {
- increment(as_Address(dst));
-}
-
-void MacroAssembler::lea(Register dst, AddressLiteral adr) {
- // leal(dst, as_Address(adr));
- // see note in movl as to why we musr use a move
- mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
-}
-
-void MacroAssembler::lea(Address dst, AddressLiteral adr) {
- // leal(dst, as_Address(adr));
- // see note in movl as to why we musr use a move
- mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
-}
-
-void MacroAssembler::mov32(AddressLiteral dst, Register src) {
- Assembler::movl(as_Address(dst), src);
-}
-
-void MacroAssembler::mov32(Register dst, AddressLiteral src) {
- Assembler::movl(dst, as_Address(src));
-}
-
-void MacroAssembler::movbyte(ArrayAddress dst, int src) {
- movb(as_Address(dst), src);
-}
-
-void MacroAssembler::movoop(Address dst, jobject obj) {
- mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
-}
-
-void MacroAssembler::movoop(Register dst, jobject obj) {
- mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
-}
-
-void MacroAssembler::movptr(Register dst, AddressLiteral src) {
- if (src.is_lval()) {
- // essentially an lea
- mov_literal32(dst, (int32_t) src.target(), src.rspec());
- } else {
- // mov 32bits from an absolute address
- movl(dst, as_Address(src));
- }
-}
-
-void MacroAssembler::movptr(ArrayAddress dst, Register src) {
- movl(as_Address(dst), src);
-}
-
-void MacroAssembler::movptr(Register dst, ArrayAddress src) {
- movl(dst, as_Address(src));
-}
-
-void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
- movss(dst, as_Address(src));
-}
-
-void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
- if (UseXmmLoadAndClearUpper) { movsd (dst, as_Address(src)); return; }
- else { movlpd(dst, as_Address(src)); return; }
-}
-
-void Assembler::pushoop(jobject obj) {
- push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
-}
-
-
-void MacroAssembler::pushptr(AddressLiteral src) {
- if (src.is_lval()) {
- push_literal32((int32_t)src.target(), src.rspec());
- } else {
- pushl(as_Address(src));
- }
-}
-
-void MacroAssembler::test32(Register src1, AddressLiteral src2) {
- // src2 must be rval
- testl(src1, as_Address(src2));
-}
-
-// FPU
-
-void MacroAssembler::fld_x(AddressLiteral src) {
- Assembler::fld_x(as_Address(src));
-}
-
-void MacroAssembler::fld_d(AddressLiteral src) {
- fld_d(as_Address(src));
-}
-
-void MacroAssembler::fld_s(AddressLiteral src) {
- fld_s(as_Address(src));
-}
-
-void MacroAssembler::fldcw(AddressLiteral src) {
- Assembler::fldcw(as_Address(src));
-}
-
-void MacroAssembler::ldmxcsr(AddressLiteral src) {
- Assembler::ldmxcsr(as_Address(src));
-}
-
-// SSE
-
-void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
- andpd(dst, as_Address(src));
-}
-
-void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
- comisd(dst, as_Address(src));
-}
-
-void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
- comiss(dst, as_Address(src));
-}
-
-void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
- movsd(dst, as_Address(src));
-}
-
-void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
- movss(dst, as_Address(src));
-}
-
-void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
- xorpd(dst, as_Address(src));
-}
-
-void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
- xorps(dst, as_Address(src));
-}
-
-void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
- ucomisd(dst, as_Address(src));
-}
-
-void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
- ucomiss(dst, as_Address(src));
-}
-
-void MacroAssembler::null_check(Register reg, int offset) {
- if (needs_explicit_null_check(offset)) {
- // provoke OS NULL exception if reg = NULL by
- // accessing M[reg] w/o changing any (non-CC) registers
- cmpl(rax, Address(reg, 0));
- // Note: should probably use testl(rax, Address(reg, 0));
- // may be shorter code (however, this version of
- // testl needs to be implemented first)
- } else {
- // nothing to do, (later) access of M[reg + offset]
- // will provoke OS NULL exception if reg = NULL
- }
-}
-
-
-int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
- // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
- // and "3.9 Partial Register Penalties", p. 22).
- int off;
- if (VM_Version::is_P6() || src.uses(dst)) {
- off = offset();
- movzxb(dst, src);
- } else {
- xorl(dst, dst);
- off = offset();
- movb(dst, src);
- }
- return off;
-}
-
-
-int MacroAssembler::load_unsigned_word(Register dst, Address src) {
- // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
- // and "3.9 Partial Register Penalties", p. 22).
- int off;
- if (VM_Version::is_P6() || src.uses(dst)) {
- off = offset();
- movzxw(dst, src);
- } else {
- xorl(dst, dst);
- off = offset();
- movw(dst, src);
- }
- return off;
-}
-
-
-int MacroAssembler::load_signed_byte(Register dst, Address src) {
- int off;
- if (VM_Version::is_P6()) {
- off = offset();
- movsxb(dst, src);
- } else {
- off = load_unsigned_byte(dst, src);
- shll(dst, 24);
- sarl(dst, 24);
- }
- return off;
-}
-
-
-int MacroAssembler::load_signed_word(Register dst, Address src) {
- int off;
- if (VM_Version::is_P6()) {
- off = offset();
- movsxw(dst, src);
- } else {
- off = load_unsigned_word(dst, src);
- shll(dst, 16);
- sarl(dst, 16);
- }
- return off;
-}
-
-
-void MacroAssembler::extend_sign(Register hi, Register lo) {
- // According to Intel Doc. AP-526, "Integer Divide", p.18.
- if (VM_Version::is_P6() && hi == rdx && lo == rax) {
- cdql();
- } else {
- movl(hi, lo);
- sarl(hi, 31);
- }
-}
-
-
-void MacroAssembler::increment(Register reg, int value) {
- if (value == min_jint) {addl(reg, value); return; }
- if (value < 0) { decrement(reg, -value); return; }
- if (value == 0) { ; return; }
- if (value == 1 && UseIncDec) { incl(reg); return; }
- /* else */ { addl(reg, value) ; return; }
-}
-
-void MacroAssembler::increment(Address dst, int value) {
- if (value == min_jint) {addl(dst, value); return; }
- if (value < 0) { decrement(dst, -value); return; }
- if (value == 0) { ; return; }
- if (value == 1 && UseIncDec) { incl(dst); return; }
- /* else */ { addl(dst, value) ; return; }
-}
-
-void MacroAssembler::decrement(Register reg, int value) {
- if (value == min_jint) {subl(reg, value); return; }
- if (value < 0) { increment(reg, -value); return; }
- if (value == 0) { ; return; }
- if (value == 1 && UseIncDec) { decl(reg); return; }
- /* else */ { subl(reg, value) ; return; }
-}
-
-void MacroAssembler::decrement(Address dst, int value) {
- if (value == min_jint) {subl(dst, value); return; }
- if (value < 0) { increment(dst, -value); return; }
- if (value == 0) { ; return; }
- if (value == 1 && UseIncDec) { decl(dst); return; }
- /* else */ { subl(dst, value) ; return; }
-}
-
-void MacroAssembler::align(int modulus) {
- if (offset() % modulus != 0) nop(modulus - (offset() % modulus));
-}
-
-
-void MacroAssembler::enter() {
- pushl(rbp);
- movl(rbp, rsp);
-}
-
-
-void MacroAssembler::leave() {
- movl(rsp, rbp);
- popl(rbp);
-}
-
-void MacroAssembler::set_last_Java_frame(Register java_thread,
- Register last_java_sp,
- Register last_java_fp,
- address last_java_pc) {
- // determine java_thread register
- if (!java_thread->is_valid()) {
- java_thread = rdi;
- get_thread(java_thread);
- }
- // determine last_java_sp register
- if (!last_java_sp->is_valid()) {
- last_java_sp = rsp;
- }
-
- // last_java_fp is optional
-
- if (last_java_fp->is_valid()) {
- movl(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
- }
-
- // last_java_pc is optional
-
- if (last_java_pc != NULL) {
- lea(Address(java_thread,
- JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
- InternalAddress(last_java_pc));
-
- }
- movl(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
-}
-
-void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) {
- // determine java_thread register
- if (!java_thread->is_valid()) {
- java_thread = rdi;
- get_thread(java_thread);
- }
- // we must set sp to zero to clear frame
- movl(Address(java_thread, JavaThread::last_Java_sp_offset()), 0);
- if (clear_fp) {
- movl(Address(java_thread, JavaThread::last_Java_fp_offset()), 0);
- }
-
- if (clear_pc)
- movl(Address(java_thread, JavaThread::last_Java_pc_offset()), 0);
-
-}
-
-
-
-// Implementation of call_VM versions
-
-void MacroAssembler::call_VM_leaf_base(
- address entry_point,
- int number_of_arguments
-) {
- call(RuntimeAddress(entry_point));
- increment(rsp, number_of_arguments * wordSize);
-}
-
-
-void MacroAssembler::call_VM_base(
- Register oop_result,
- Register java_thread,
- Register last_java_sp,
- address entry_point,
- int number_of_arguments,
- bool check_exceptions
-) {
- // determine java_thread register
- if (!java_thread->is_valid()) {
- java_thread = rdi;
- get_thread(java_thread);
- }
- // determine last_java_sp register
- if (!last_java_sp->is_valid()) {
- last_java_sp = rsp;
- }
- // debugging support
- assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
- assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
- assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
- // push java thread (becomes first argument of C function)
- pushl(java_thread);
- // set last Java frame before call
- assert(last_java_sp != rbp, "this code doesn't work for last_java_sp == rbp, which currently can't portably work anyway since C2 doesn't save rbp,");
- // Only interpreter should have to set fp
- set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
- // do the call
- call(RuntimeAddress(entry_point));
- // restore the thread (cannot use the pushed argument since arguments
- // may be overwritten by C code generated by an optimizing compiler);
- // however can use the register value directly if it is callee saved.
- if (java_thread == rdi || java_thread == rsi) {
- // rdi & rsi are callee saved -> nothing to do
-#ifdef ASSERT
- guarantee(java_thread != rax, "change this code");
- pushl(rax);
- { Label L;
- get_thread(rax);
- cmpl(java_thread, rax);
- jcc(Assembler::equal, L);
- stop("MacroAssembler::call_VM_base: rdi not callee saved?");
- bind(L);
- }
- popl(rax);
-#endif
- } else {
- get_thread(java_thread);
- }
- // reset last Java frame
- // Only interpreter should have to clear fp
- reset_last_Java_frame(java_thread, true, false);
- // discard thread and arguments
- addl(rsp, (1 + number_of_arguments)*wordSize);
-
-#ifndef CC_INTERP
- // C++ interp handles this in the interpreter
- check_and_handle_popframe(java_thread);
- check_and_handle_earlyret(java_thread);
-#endif /* CC_INTERP */
-
- if (check_exceptions) {
- // check for pending exceptions (java_thread is set upon return)
- cmpl(Address(java_thread, Thread::pending_exception_offset()), NULL_WORD);
- jump_cc(Assembler::notEqual,
- RuntimeAddress(StubRoutines::forward_exception_entry()));
- }
-
- // get oop result if there is one and reset the value in the thread
- if (oop_result->is_valid()) {
- movl(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
- movl(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
- verify_oop(oop_result);
- }
-}
-
-
-void MacroAssembler::check_and_handle_popframe(Register java_thread) {
-}
-
-void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
-}
-
-void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
- leal(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
- call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
-}
-
-
-void MacroAssembler::call_VM(Register oop_result, address entry_point, bool check_exceptions) {
- Label C, E;
- call(C, relocInfo::none);
- jmp(E);
-
- bind(C);
- call_VM_helper(oop_result, entry_point, 0, check_exceptions);
- ret(0);
-
- bind(E);
-}
-
-
-void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions) {
- Label C, E;
- call(C, relocInfo::none);
- jmp(E);
-
- bind(C);
- pushl(arg_1);
- call_VM_helper(oop_result, entry_point, 1, check_exceptions);
- ret(0);
-
- bind(E);
-}
-
-
-void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) {
- Label C, E;
- call(C, relocInfo::none);
- jmp(E);
-
- bind(C);
- pushl(arg_2);
- pushl(arg_1);
- call_VM_helper(oop_result, entry_point, 2, check_exceptions);
- ret(0);
-
- bind(E);
-}
-
-
-void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) {
- Label C, E;
- call(C, relocInfo::none);
- jmp(E);
-
- bind(C);
- pushl(arg_3);
- pushl(arg_2);
- pushl(arg_1);
- call_VM_helper(oop_result, entry_point, 3, check_exceptions);
- ret(0);
-
- bind(E);
-}
-
-
-void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments, bool check_exceptions) {
- call_VM_base(oop_result, noreg, last_java_sp, entry_point, number_of_arguments, check_exceptions);
-}
-
-
-void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions) {
- pushl(arg_1);
- call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
-}
-
-
-void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) {
- pushl(arg_2);
- pushl(arg_1);
- call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
-}
-
-
-void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) {
- pushl(arg_3);
- pushl(arg_2);
- pushl(arg_1);
- call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
-}
-
-
-void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
- call_VM_leaf_base(entry_point, number_of_arguments);
-}
-
-
-void MacroAssembler::call_VM_leaf(address entry_point, Register arg_1) {
- pushl(arg_1);
- call_VM_leaf(entry_point, 1);
-}
-
-
-void MacroAssembler::call_VM_leaf(address entry_point, Register arg_1, Register arg_2) {
- pushl(arg_2);
- pushl(arg_1);
- call_VM_leaf(entry_point, 2);
-}
-
-
-void MacroAssembler::call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3) {
- pushl(arg_3);
- pushl(arg_2);
- pushl(arg_1);
- call_VM_leaf(entry_point, 3);
-}
-
-
-// Calls to C land
-//
-// When entering C land, the rbp, & rsp of the last Java frame have to be recorded
-// in the (thread-local) JavaThread object. When leaving C land, the last Java fp
-// has to be reset to 0. This is required to allow proper stack traversal.
-
-void MacroAssembler::store_check(Register obj) {
- // Does a store check for the oop in register obj. The content of
- // register obj is destroyed afterwards.
- store_check_part_1(obj);
- store_check_part_2(obj);
-}
-
-
-void MacroAssembler::store_check(Register obj, Address dst) {
- store_check(obj);
-}
-
-
-// split the store check operation so that other instructions can be scheduled inbetween
-void MacroAssembler::store_check_part_1(Register obj) {
- BarrierSet* bs = Universe::heap()->barrier_set();
- assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
- shrl(obj, CardTableModRefBS::card_shift);
-}
-
-
-void MacroAssembler::store_check_part_2(Register obj) {
- BarrierSet* bs = Universe::heap()->barrier_set();
- assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
- CardTableModRefBS* ct = (CardTableModRefBS*)bs;
- assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
-
- // The calculation for byte_map_base is as follows:
- // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift);
- // So this essentially converts an address to a displacement and
- // it will never need to be relocated. On 64bit however the value may be too
- // large for a 32bit displacement
-
- intptr_t disp = (intptr_t) ct->byte_map_base;
- Address cardtable(noreg, obj, Address::times_1, disp);
- movb(cardtable, 0);
-}
-
-
-void MacroAssembler::c2bool(Register x) {
- // implements x == 0 ? 0 : 1
- // note: must only look at least-significant byte of x
- // since C-style booleans are stored in one byte
- // only! (was bug)
- andl(x, 0xFF);
- setb(Assembler::notZero, x);
-}
-
-
-int MacroAssembler::corrected_idivl(Register reg) {
- // Full implementation of Java idiv and irem; checks for
- // special case as described in JVM spec., p.243 & p.271.
- // The function returns the (pc) offset of the idivl
- // instruction - may be needed for implicit exceptions.
- //
- // normal case special case
- //
- // input : rax,: dividend min_int
- // reg: divisor (may not be rax,/rdx) -1
- //
- // output: rax,: quotient (= rax, idiv reg) min_int
- // rdx: remainder (= rax, irem reg) 0
- assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
- const int min_int = 0x80000000;
- Label normal_case, special_case;
-
- // check for special case
- cmpl(rax, min_int);
- jcc(Assembler::notEqual, normal_case);
- xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
- cmpl(reg, -1);
- jcc(Assembler::equal, special_case);
-
- // handle normal case
- bind(normal_case);
- cdql();
- int idivl_offset = offset();
- idivl(reg);
-
- // normal and special case exit
- bind(special_case);
-
- return idivl_offset;
-}
-
-
-void MacroAssembler::lneg(Register hi, Register lo) {
- negl(lo);
- adcl(hi, 0);
- negl(hi);
-}
-
-
-void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
- // Multiplication of two Java long values stored on the stack
- // as illustrated below. Result is in rdx:rax.
- //
- // rsp ---> [ ?? ] \ \
- // .... | y_rsp_offset |
- // [ y_lo ] / (in bytes) | x_rsp_offset
- // [ y_hi ] | (in bytes)
- // .... |
- // [ x_lo ] /
- // [ x_hi ]
- // ....
- //
- // Basic idea: lo(result) = lo(x_lo * y_lo)
- // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
- Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
- Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
- Label quick;
- // load x_hi, y_hi and check if quick
- // multiplication is possible
- movl(rbx, x_hi);
- movl(rcx, y_hi);
- movl(rax, rbx);
- orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
- jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
- // do full multiplication
- // 1st step
- mull(y_lo); // x_hi * y_lo
- movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
- // 2nd step
- movl(rax, x_lo);
- mull(rcx); // x_lo * y_hi
- addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
- // 3rd step
- bind(quick); // note: rbx, = 0 if quick multiply!
- movl(rax, x_lo);
- mull(y_lo); // x_lo * y_lo
- addl(rdx, rbx); // correct hi(x_lo * y_lo)
-}
-
-
-void MacroAssembler::lshl(Register hi, Register lo) {
- // Java shift left long support (semantics as described in JVM spec., p.305)
- // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
- // shift value is in rcx !
- assert(hi != rcx, "must not use rcx");
- assert(lo != rcx, "must not use rcx");
- const Register s = rcx; // shift count
- const int n = BitsPerWord;
- Label L;
- andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
- cmpl(s, n); // if (s < n)
- jcc(Assembler::less, L); // else (s >= n)
- movl(hi, lo); // x := x << n
- xorl(lo, lo);
- // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
- bind(L); // s (mod n) < n
- shldl(hi, lo); // x := x << s
- shll(lo);
-}
-
-
-void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
- // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
- // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
- assert(hi != rcx, "must not use rcx");
- assert(lo != rcx, "must not use rcx");
- const Register s = rcx; // shift count
- const int n = BitsPerWord;
- Label L;
- andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
- cmpl(s, n); // if (s < n)
- jcc(Assembler::less, L); // else (s >= n)
- movl(lo, hi); // x := x >> n
- if (sign_extension) sarl(hi, 31);
- else xorl(hi, hi);
- // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
- bind(L); // s (mod n) < n
- shrdl(lo, hi); // x := x >> s
- if (sign_extension) sarl(hi);
- else shrl(hi);
-}
-
-
-// Note: y_lo will be destroyed
-void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
- // Long compare for Java (semantics as described in JVM spec.)
- Label high, low, done;
-
- cmpl(x_hi, y_hi);
- jcc(Assembler::less, low);
- jcc(Assembler::greater, high);
- // x_hi is the return register
- xorl(x_hi, x_hi);
- cmpl(x_lo, y_lo);
- jcc(Assembler::below, low);
- jcc(Assembler::equal, done);
-
- bind(high);
- xorl(x_hi, x_hi);
- increment(x_hi);
- jmp(done);
-
- bind(low);
- xorl(x_hi, x_hi);
- decrement(x_hi);
-
- bind(done);
-}
-
-
-void MacroAssembler::save_rax(Register tmp) {
- if (tmp == noreg) pushl(rax);
- else if (tmp != rax) movl(tmp, rax);
-}
-
-
-void MacroAssembler::restore_rax(Register tmp) {
- if (tmp == noreg) popl(rax);
- else if (tmp != rax) movl(rax, tmp);
-}
-
-
-void MacroAssembler::fremr(Register tmp) {
- save_rax(tmp);
- { Label L;
- bind(L);
- fprem();
- fwait(); fnstsw_ax();
- sahf();
- jcc(Assembler::parity, L);
- }
- restore_rax(tmp);
- // Result is in ST0.
- // Note: fxch & fpop to get rid of ST1
- // (otherwise FPU stack could overflow eventually)
- fxch(1);
- fpop();
-}
-
-
-static const double pi_4 = 0.7853981633974483;
-
-void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) {
- // A hand-coded argument reduction for values in fabs(pi/4, pi/2)
- // was attempted in this code; unfortunately it appears that the
- // switch to 80-bit precision and back causes this to be
- // unprofitable compared with simply performing a runtime call if
- // the argument is out of the (-pi/4, pi/4) range.
-
- Register tmp = noreg;
- if (!VM_Version::supports_cmov()) {
- // fcmp needs a temporary so preserve rbx,
- tmp = rbx;
- pushl(tmp);
- }
-
- Label slow_case, done;
-
- // x ?<= pi/4
- fld_d(ExternalAddress((address)&pi_4));
- fld_s(1); // Stack: X PI/4 X
- fabs(); // Stack: |X| PI/4 X
- fcmp(tmp);
- jcc(Assembler::above, slow_case);
-
- // fastest case: -pi/4 <= x <= pi/4
- switch(trig) {
- case 's':
- fsin();
- break;
- case 'c':
- fcos();
- break;
- case 't':
- ftan();
- break;
- default:
- assert(false, "bad intrinsic");
- break;
- }
- jmp(done);
-
- // slow case: runtime call
- bind(slow_case);
- // Preserve registers across runtime call
- pushad();
- int incoming_argument_and_return_value_offset = -1;
- if (num_fpu_regs_in_use > 1) {
- // Must preserve all other FPU regs (could alternatively convert
- // SharedRuntime::dsin and dcos into assembly routines known not to trash
- // FPU state, but can not trust C compiler)
- NEEDS_CLEANUP;
- // NOTE that in this case we also push the incoming argument to
- // the stack and restore it later; we also use this stack slot to
- // hold the return value from dsin or dcos.
- for (int i = 0; i < num_fpu_regs_in_use; i++) {
- subl(rsp, wordSize*2);
- fstp_d(Address(rsp, 0));
- }
- incoming_argument_and_return_value_offset = 2*wordSize*(num_fpu_regs_in_use-1);
- fld_d(Address(rsp, incoming_argument_and_return_value_offset));
- }
- subl(rsp, wordSize*2);
- fstp_d(Address(rsp, 0));
- // NOTE: we must not use call_VM_leaf here because that requires a
- // complete interpreter frame in debug mode -- same bug as 4387334
- NEEDS_CLEANUP;
- // Need to add stack banging before this runtime call if it needs to
- // be taken; however, there is no generic stack banging routine at
- // the MacroAssembler level
- switch(trig) {
- case 's':
- {
- call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dsin)));
- }
- break;
- case 'c':
- {
- call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dcos)));
- }
- break;
- case 't':
- {
- call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtan)));
- }
- break;
- default:
- assert(false, "bad intrinsic");
- break;
- }
- addl(rsp, wordSize * 2);
- if (num_fpu_regs_in_use > 1) {
- // Must save return value to stack and then restore entire FPU stack
- fstp_d(Address(rsp, incoming_argument_and_return_value_offset));
- for (int i = 0; i < num_fpu_regs_in_use; i++) {
- fld_d(Address(rsp, 0));
- addl(rsp, wordSize*2);
- }
- }
- popad();
-
- // Come here with result in F-TOS
- bind(done);
-
- if (tmp != noreg) {
- popl(tmp);
- }
-}
-
-void MacroAssembler::jC2(Register tmp, Label& L) {
- // set parity bit if FPU flag C2 is set (via rax)
- save_rax(tmp);
- fwait(); fnstsw_ax();
- sahf();
- restore_rax(tmp);
- // branch
- jcc(Assembler::parity, L);
-}
-
-
-void MacroAssembler::jnC2(Register tmp, Label& L) {
- // set parity bit if FPU flag C2 is set (via rax)
- save_rax(tmp);
- fwait(); fnstsw_ax();
- sahf();
- restore_rax(tmp);
- // branch
- jcc(Assembler::noParity, L);
-}
-
-
-void MacroAssembler::fcmp(Register tmp) {
- fcmp(tmp, 1, true, true);
-}
-
-
-void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
- assert(!pop_right || pop_left, "usage error");
- if (VM_Version::supports_cmov()) {
- assert(tmp == noreg, "unneeded temp");
- if (pop_left) {
- fucomip(index);
- } else {
- fucomi(index);
- }
- if (pop_right) {
- fpop();
- }
- } else {
- assert(tmp != noreg, "need temp");
- if (pop_left) {
- if (pop_right) {
- fcompp();
- } else {
- fcomp(index);
- }
- } else {
- fcom(index);
- }
- // convert FPU condition into eflags condition via rax,
- save_rax(tmp);
- fwait(); fnstsw_ax();
- sahf();
- restore_rax(tmp);
- }
- // condition codes set as follows:
- //
- // CF (corresponds to C0) if x < y
- // PF (corresponds to C2) if unordered
- // ZF (corresponds to C3) if x = y
-}
-
-
-void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
- fcmp2int(dst, unordered_is_less, 1, true, true);
-}
-
-
-void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
- fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
- Label L;
- if (unordered_is_less) {
- movl(dst, -1);
- jcc(Assembler::parity, L);
- jcc(Assembler::below , L);
- movl(dst, 0);
- jcc(Assembler::equal , L);
- increment(dst);
- } else { // unordered is greater
- movl(dst, 1);
- jcc(Assembler::parity, L);
- jcc(Assembler::above , L);
- movl(dst, 0);
- jcc(Assembler::equal , L);
- decrement(dst);
- }
- bind(L);
-}
-
-void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
- ucomiss(opr1, opr2);
-
- Label L;
- if (unordered_is_less) {
- movl(dst, -1);
- jcc(Assembler::parity, L);
- jcc(Assembler::below , L);
- movl(dst, 0);
- jcc(Assembler::equal , L);
- increment(dst);
- } else { // unordered is greater
- movl(dst, 1);
- jcc(Assembler::parity, L);
- jcc(Assembler::above , L);
- movl(dst, 0);
- jcc(Assembler::equal , L);
- decrement(dst);
- }
- bind(L);
-}
-
-void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
- ucomisd(opr1, opr2);
-
- Label L;
- if (unordered_is_less) {
- movl(dst, -1);
- jcc(Assembler::parity, L);
- jcc(Assembler::below , L);
- movl(dst, 0);
- jcc(Assembler::equal , L);
- increment(dst);
- } else { // unordered is greater
- movl(dst, 1);
- jcc(Assembler::parity, L);
- jcc(Assembler::above , L);
- movl(dst, 0);
- jcc(Assembler::equal , L);
- decrement(dst);
- }
- bind(L);
-}
-
-
-
-void MacroAssembler::fpop() {
- ffree();
- fincstp();
-}
-
-
-void MacroAssembler::sign_extend_short(Register reg) {
- if (VM_Version::is_P6()) {
- movsxw(reg, reg);
- } else {
- shll(reg, 16);
- sarl(reg, 16);
- }
-}
-
-
-void MacroAssembler::sign_extend_byte(Register reg) {
- if (VM_Version::is_P6() && reg->has_byte_register()) {
- movsxb(reg, reg);
- } else {
- shll(reg, 24);
- sarl(reg, 24);
- }
-}
-
-
-void MacroAssembler::division_with_shift (Register reg, int shift_value) {
- assert (shift_value > 0, "illegal shift value");
- Label _is_positive;
- testl (reg, reg);
- jcc (Assembler::positive, _is_positive);
- int offset = (1 << shift_value) - 1 ;
-
- increment(reg, offset);
-
- bind (_is_positive);
- sarl(reg, shift_value);
-}
-
-
-void MacroAssembler::round_to(Register reg, int modulus) {
- addl(reg, modulus - 1);
- andl(reg, -modulus);
-}
-
-// C++ bool manipulation
-
-void MacroAssembler::movbool(Register dst, Address src) {
- if(sizeof(bool) == 1)
- movb(dst, src);
- else if(sizeof(bool) == 2)
- movw(dst, src);
- else if(sizeof(bool) == 4)
- movl(dst, src);
- else
- // unsupported
- ShouldNotReachHere();
-}
-
-void MacroAssembler::movbool(Address dst, bool boolconst) {
- if(sizeof(bool) == 1)
- movb(dst, (int) boolconst);
- else if(sizeof(bool) == 2)
- movw(dst, (int) boolconst);
- else if(sizeof(bool) == 4)
- movl(dst, (int) boolconst);
- else
- // unsupported
- ShouldNotReachHere();
-}
-
-void MacroAssembler::movbool(Address dst, Register src) {
- if(sizeof(bool) == 1)
- movb(dst, src);
- else if(sizeof(bool) == 2)
- movw(dst, src);
- else if(sizeof(bool) == 4)
- movl(dst, src);
- else
- // unsupported
- ShouldNotReachHere();
-}
-
-void MacroAssembler::testbool(Register dst) {
- if(sizeof(bool) == 1)
- testb(dst, (int) 0xff);
- else if(sizeof(bool) == 2) {
- // testw implementation needed for two byte bools
- ShouldNotReachHere();
- } else if(sizeof(bool) == 4)
- testl(dst, dst);
- else
- // unsupported
- ShouldNotReachHere();
-}
-
-void MacroAssembler::verify_oop(Register reg, const char* s) {
- if (!VerifyOops) return;
- // Pass register number to verify_oop_subroutine
- char* b = new char[strlen(s) + 50];
- sprintf(b, "verify_oop: %s: %s", reg->name(), s);
- pushl(rax); // save rax,
- pushl(reg); // pass register argument
- ExternalAddress buffer((address) b);
- pushptr(buffer.addr());
- // call indirectly to solve generation ordering problem
- movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
- call(rax);
-}
-
-
-void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
- if (!VerifyOops) return;
- // QQQ fix this
- // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
- // Pass register number to verify_oop_subroutine
- char* b = new char[strlen(s) + 50];
- sprintf(b, "verify_oop_addr: %s", s);
- pushl(rax); // save rax,
- // addr may contain rsp so we will have to adjust it based on the push
- // we just did
- if (addr.uses(rsp)) {
- leal(rax, addr);
- pushl(Address(rax, BytesPerWord));
- } else {
- pushl(addr);
- }
- ExternalAddress buffer((address) b);
- // pass msg argument
- pushptr(buffer.addr());
- // call indirectly to solve generation ordering problem
- movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
- call(rax);
- // Caller pops the arguments and restores rax, from the stack
-}
-
-
-void MacroAssembler::stop(const char* msg) {
- ExternalAddress message((address)msg);
- // push address of message
- pushptr(message.addr());
- { Label L; call(L, relocInfo::none); bind(L); } // push eip
- pushad(); // push registers
- call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug)));
- hlt();
-}
-
-
-void MacroAssembler::warn(const char* msg) {
- push_CPU_state();
-
- ExternalAddress message((address) msg);
- // push address of message
- pushptr(message.addr());
-
- call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
- addl(rsp, wordSize); // discard argument
- pop_CPU_state();
-}
-
-
-void MacroAssembler::debug(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
- // In order to get locks to work, we need to fake a in_VM state
- JavaThread* thread = JavaThread::current();
- JavaThreadState saved_state = thread->thread_state();
- thread->set_thread_state(_thread_in_vm);
- if (ShowMessageBoxOnError) {
- JavaThread* thread = JavaThread::current();
- JavaThreadState saved_state = thread->thread_state();
- thread->set_thread_state(_thread_in_vm);
- ttyLocker ttyl;
- if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
- BytecodeCounter::print();
- }
- // To see where a verify_oop failed, get $ebx+40/X for this frame.
- // This is the value of eip which points to where verify_oop will return.
- if (os::message_box(msg, "Execution stopped, print registers?")) {
- tty->print_cr("eip = 0x%08x", eip);
- tty->print_cr("rax, = 0x%08x", rax);
- tty->print_cr("rbx, = 0x%08x", rbx);
- tty->print_cr("rcx = 0x%08x", rcx);
- tty->print_cr("rdx = 0x%08x", rdx);
- tty->print_cr("rdi = 0x%08x", rdi);
- tty->print_cr("rsi = 0x%08x", rsi);
- tty->print_cr("rbp, = 0x%08x", rbp);
- tty->print_cr("rsp = 0x%08x", rsp);
- BREAKPOINT;
- }
- } else {
- ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
- assert(false, "DEBUG MESSAGE");
- }
- ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
-}
-
-
-
-void MacroAssembler::os_breakpoint() {
- // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
- // (e.g., MSVC can't call ps() otherwise)
- call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
-}
-
-
-void MacroAssembler::push_fTOS() {
- subl(rsp, 2 * wordSize);
- fstp_d(Address(rsp, 0));
-}
-
-
-void MacroAssembler::pop_fTOS() {
- fld_d(Address(rsp, 0));
- addl(rsp, 2 * wordSize);
-}
-
-
-void MacroAssembler::empty_FPU_stack() {
- if (VM_Version::supports_mmx()) {
- emms();
- } else {
- for (int i = 8; i-- > 0; ) ffree(i);
- }
-}
-
-
-class ControlWord {
- public:
- int32_t _value;
-
- int rounding_control() const { return (_value >> 10) & 3 ; }
- int precision_control() const { return (_value >> 8) & 3 ; }
- bool precision() const { return ((_value >> 5) & 1) != 0; }
- bool underflow() const { return ((_value >> 4) & 1) != 0; }
- bool overflow() const { return ((_value >> 3) & 1) != 0; }
- bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
- bool denormalized() const { return ((_value >> 1) & 1) != 0; }
- bool invalid() const { return ((_value >> 0) & 1) != 0; }
-
- void print() const {
- // rounding control
- const char* rc;
- switch (rounding_control()) {
- case 0: rc = "round near"; break;
- case 1: rc = "round down"; break;
- case 2: rc = "round up "; break;
- case 3: rc = "chop "; break;
- };
- // precision control
- const char* pc;
- switch (precision_control()) {
- case 0: pc = "24 bits "; break;
- case 1: pc = "reserved"; break;
- case 2: pc = "53 bits "; break;
- case 3: pc = "64 bits "; break;
- };
- // flags
- char f[9];
- f[0] = ' ';
- f[1] = ' ';
- f[2] = (precision ()) ? 'P' : 'p';
- f[3] = (underflow ()) ? 'U' : 'u';
- f[4] = (overflow ()) ? 'O' : 'o';
- f[5] = (zero_divide ()) ? 'Z' : 'z';
- f[6] = (denormalized()) ? 'D' : 'd';
- f[7] = (invalid ()) ? 'I' : 'i';
- f[8] = '\x0';
- // output
- printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
- }
-
-};
-
-
-class StatusWord {
- public:
- int32_t _value;
-
- bool busy() const { return ((_value >> 15) & 1) != 0; }
- bool C3() const { return ((_value >> 14) & 1) != 0; }
- bool C2() const { return ((_value >> 10) & 1) != 0; }
- bool C1() const { return ((_value >> 9) & 1) != 0; }
- bool C0() const { return ((_value >> 8) & 1) != 0; }
- int top() const { return (_value >> 11) & 7 ; }
- bool error_status() const { return ((_value >> 7) & 1) != 0; }
- bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
- bool precision() const { return ((_value >> 5) & 1) != 0; }
- bool underflow() const { return ((_value >> 4) & 1) != 0; }
- bool overflow() const { return ((_value >> 3) & 1) != 0; }
- bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
- bool denormalized() const { return ((_value >> 1) & 1) != 0; }
- bool invalid() const { return ((_value >> 0) & 1) != 0; }
-
- void print() const {
- // condition codes
- char c[5];
- c[0] = (C3()) ? '3' : '-';
- c[1] = (C2()) ? '2' : '-';
- c[2] = (C1()) ? '1' : '-';
- c[3] = (C0()) ? '0' : '-';
- c[4] = '\x0';
- // flags
- char f[9];
- f[0] = (error_status()) ? 'E' : '-';
- f[1] = (stack_fault ()) ? 'S' : '-';
- f[2] = (precision ()) ? 'P' : '-';
- f[3] = (underflow ()) ? 'U' : '-';
- f[4] = (overflow ()) ? 'O' : '-';
- f[5] = (zero_divide ()) ? 'Z' : '-';
- f[6] = (denormalized()) ? 'D' : '-';
- f[7] = (invalid ()) ? 'I' : '-';
- f[8] = '\x0';
- // output
- printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
- }
-
-};
-
-
-class TagWord {
- public:
- int32_t _value;
-
- int tag_at(int i) const { return (_value >> (i*2)) & 3; }
-
- void print() const {
- printf("%04x", _value & 0xFFFF);
- }
-
-};
-
-
-class FPU_Register {
- public:
- int32_t _m0;
- int32_t _m1;
- int16_t _ex;
-
- bool is_indefinite() const {
- return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
- }
-
- void print() const {
- char sign = (_ex < 0) ? '-' : '+';
- const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
- printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
- };
-
-};
-
-
-class FPU_State {
- public:
- enum {
- register_size = 10,
- number_of_registers = 8,
- register_mask = 7
- };
-
- ControlWord _control_word;
- StatusWord _status_word;
- TagWord _tag_word;
- int32_t _error_offset;
- int32_t _error_selector;
- int32_t _data_offset;
- int32_t _data_selector;
- int8_t _register[register_size * number_of_registers];
-
- int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
- FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
-
- const char* tag_as_string(int tag) const {
- switch (tag) {
- case 0: return "valid";
- case 1: return "zero";
- case 2: return "special";
- case 3: return "empty";
- }
- ShouldNotReachHere()
- return NULL;
- }
-
- void print() const {
- // print computation registers
- { int t = _status_word.top();
- for (int i = 0; i < number_of_registers; i++) {
- int j = (i - t) & register_mask;
- printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
- st(j)->print();
- printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
- }
- }
- printf("\n");
- // print control registers
- printf("ctrl = "); _control_word.print(); printf("\n");
- printf("stat = "); _status_word .print(); printf("\n");
- printf("tags = "); _tag_word .print(); printf("\n");
- }
-
-};
-
-
-class Flag_Register {
- public:
- int32_t _value;
-
- bool overflow() const { return ((_value >> 11) & 1) != 0; }
- bool direction() const { return ((_value >> 10) & 1) != 0; }
- bool sign() const { return ((_value >> 7) & 1) != 0; }
- bool zero() const { return ((_value >> 6) & 1) != 0; }
- bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
- bool parity() const { return ((_value >> 2) & 1) != 0; }
- bool carry() const { return ((_value >> 0) & 1) != 0; }
-
- void print() const {
- // flags
- char f[8];
- f[0] = (overflow ()) ? 'O' : '-';
- f[1] = (direction ()) ? 'D' : '-';
- f[2] = (sign ()) ? 'S' : '-';
- f[3] = (zero ()) ? 'Z' : '-';
- f[4] = (auxiliary_carry()) ? 'A' : '-';
- f[5] = (parity ()) ? 'P' : '-';
- f[6] = (carry ()) ? 'C' : '-';
- f[7] = '\x0';
- // output
- printf("%08x flags = %s", _value, f);
- }
-
-};
-
-
-class IU_Register {
- public:
- int32_t _value;
-
- void print() const {
- printf("%08x %11d", _value, _value);
- }
-
-};
-
-
-class IU_State {
- public:
- Flag_Register _eflags;
- IU_Register _rdi;
- IU_Register _rsi;
- IU_Register _rbp;
- IU_Register _rsp;
- IU_Register _rbx;
- IU_Register _rdx;
- IU_Register _rcx;
- IU_Register _rax;
-
- void print() const {
- // computation registers
- printf("rax, = "); _rax.print(); printf("\n");
- printf("rbx, = "); _rbx.print(); printf("\n");
- printf("rcx = "); _rcx.print(); printf("\n");
- printf("rdx = "); _rdx.print(); printf("\n");
- printf("rdi = "); _rdi.print(); printf("\n");
- printf("rsi = "); _rsi.print(); printf("\n");
- printf("rbp, = "); _rbp.print(); printf("\n");
- printf("rsp = "); _rsp.print(); printf("\n");
- printf("\n");
- // control registers
- printf("flgs = "); _eflags.print(); printf("\n");
- }
-};
-
-
-class CPU_State {
- public:
- FPU_State _fpu_state;
- IU_State _iu_state;
-
- void print() const {
- printf("--------------------------------------------------\n");
- _iu_state .print();
- printf("\n");
- _fpu_state.print();
- printf("--------------------------------------------------\n");
- }
-
-};
-
-
-static void _print_CPU_state(CPU_State* state) {
- state->print();
-};
-
-
-void MacroAssembler::print_CPU_state() {
- push_CPU_state();
- pushl(rsp); // pass CPU state
- call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
- addl(rsp, wordSize); // discard argument
- pop_CPU_state();
-}
-
-
-static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
- static int counter = 0;
- FPU_State* fs = &state->_fpu_state;
- counter++;
- // For leaf calls, only verify that the top few elements remain empty.
- // We only need 1 empty at the top for C2 code.
- if( stack_depth < 0 ) {
- if( fs->tag_for_st(7) != 3 ) {
- printf("FPR7 not empty\n");
- state->print();
- assert(false, "error");
- return false;
- }
- return true; // All other stack states do not matter
- }
-
- assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
- "bad FPU control word");
-
- // compute stack depth
- int i = 0;
- while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
- int d = i;
- while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
- // verify findings
- if (i != FPU_State::number_of_registers) {
- // stack not contiguous
- printf("%s: stack not contiguous at ST%d\n", s, i);
- state->print();
- assert(false, "error");
- return false;
- }
- // check if computed stack depth corresponds to expected stack depth
- if (stack_depth < 0) {
- // expected stack depth is -stack_depth or less
- if (d > -stack_depth) {
- // too many elements on the stack
- printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
- state->print();
- assert(false, "error");
- return false;
- }
- } else {
- // expected stack depth is stack_depth
- if (d != stack_depth) {
- // wrong stack depth
- printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
- state->print();
- assert(false, "error");
- return false;
- }
- }
- // everything is cool
- return true;
-}
-
-
-void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
- if (!VerifyFPU) return;
- push_CPU_state();
- pushl(rsp); // pass CPU state
- ExternalAddress msg((address) s);
- // pass message string s
- pushptr(msg.addr());
- pushl(stack_depth); // pass stack depth
- call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
- addl(rsp, 3 * wordSize); // discard arguments
- // check for error
- { Label L;
- testl(rax, rax);
- jcc(Assembler::notZero, L);
- int3(); // break if error condition
- bind(L);
- }
- pop_CPU_state();
-}
-
-
-void MacroAssembler::push_IU_state() {
- pushad();
- pushfd();
-}
-
-
-void MacroAssembler::pop_IU_state() {
- popfd();
- popad();
-}
-
-
-void MacroAssembler::push_FPU_state() {
- subl(rsp, FPUStateSizeInWords * wordSize);
- fnsave(Address(rsp, 0));
- fwait();
-}
-
-
-void MacroAssembler::pop_FPU_state() {
- frstor(Address(rsp, 0));
- addl(rsp, FPUStateSizeInWords * wordSize);
-}
-
-
-void MacroAssembler::push_CPU_state() {
- push_IU_state();
- push_FPU_state();
-}
-
-
-void MacroAssembler::pop_CPU_state() {
- pop_FPU_state();
- pop_IU_state();
-}
-
-
-void MacroAssembler::push_callee_saved_registers() {
- pushl(rsi);
- pushl(rdi);
- pushl(rdx);
- pushl(rcx);
-}
-
-
-void MacroAssembler::pop_callee_saved_registers() {
- popl(rcx);
- popl(rdx);
- popl(rdi);
- popl(rsi);
-}
-
-
-void MacroAssembler::set_word_if_not_zero(Register dst) {
- xorl(dst, dst);
- set_byte_if_not_zero(dst);
-}
-
-// Write serialization page so VM thread can do a pseudo remote membar.
-// We use the current thread pointer to calculate a thread specific
-// offset to write to within the page. This minimizes bus traffic
-// due to cache line collision.
-void MacroAssembler::serialize_memory(Register thread, Register tmp) {
- movl(tmp, thread);
- shrl(tmp, os::get_serialize_page_shift_count());
- andl(tmp, (os::vm_page_size() - sizeof(int)));
-
- Address index(noreg, tmp, Address::times_1);
- ExternalAddress page(os::get_memory_serialize_page());
-
- movptr(ArrayAddress(page, index), tmp);
-}
-
-
-void MacroAssembler::verify_tlab() {
-#ifdef ASSERT
- if (UseTLAB && VerifyOops) {
- Label next, ok;
- Register t1 = rsi;
- Register thread_reg = rbx;
-
- pushl(t1);
- pushl(thread_reg);
- get_thread(thread_reg);
-
- movl(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
- cmpl(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
- jcc(Assembler::aboveEqual, next);
- stop("assert(top >= start)");
- should_not_reach_here();
-
- bind(next);
- movl(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
- cmpl(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
- jcc(Assembler::aboveEqual, ok);
- stop("assert(top <= end)");
- should_not_reach_here();
-
- bind(ok);
- popl(thread_reg);
- popl(t1);
- }
-#endif
-}
-
-
-// Defines obj, preserves var_size_in_bytes
-void MacroAssembler::eden_allocate(Register obj, Register var_size_in_bytes, int con_size_in_bytes,
- Register t1, Label& slow_case) {
- assert(obj == rax, "obj must be in rax, for cmpxchg");
- assert_different_registers(obj, var_size_in_bytes, t1);
- Register end = t1;
- Label retry;
- bind(retry);
- ExternalAddress heap_top((address) Universe::heap()->top_addr());
- movptr(obj, heap_top);
- if (var_size_in_bytes == noreg) {
- leal(end, Address(obj, con_size_in_bytes));
- } else {
- leal(end, Address(obj, var_size_in_bytes, Address::times_1));
- }
- // if end < obj then we wrapped around => object too long => slow case
- cmpl(end, obj);
- jcc(Assembler::below, slow_case);
- cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr()));
- jcc(Assembler::above, slow_case);
- // Compare obj with the top addr, and if still equal, store the new top addr in
- // end at the address of the top addr pointer. Sets ZF if was equal, and clears
- // it otherwise. Use lock prefix for atomicity on MPs.
- if (os::is_MP()) {
- lock();
- }
- cmpxchgptr(end, heap_top);
- jcc(Assembler::notEqual, retry);
-}
-
-
-// Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
-void MacroAssembler::tlab_allocate(Register obj, Register var_size_in_bytes, int con_size_in_bytes,
- Register t1, Register t2, Label& slow_case) {
- assert_different_registers(obj, t1, t2);
- assert_different_registers(obj, var_size_in_bytes, t1);
- Register end = t2;
- Register thread = t1;
-
- verify_tlab();
-
- get_thread(thread);
-
- movl(obj, Address(thread, JavaThread::tlab_top_offset()));
- if (var_size_in_bytes == noreg) {
- leal(end, Address(obj, con_size_in_bytes));
- } else {
- leal(end, Address(obj, var_size_in_bytes, Address::times_1));
- }
- cmpl(end, Address(thread, JavaThread::tlab_end_offset()));
- jcc(Assembler::above, slow_case);
-
- // update the tlab top pointer
- movl(Address(thread, JavaThread::tlab_top_offset()), end);
-
- // recover var_size_in_bytes if necessary
- if (var_size_in_bytes == end) {
- subl(var_size_in_bytes, obj);
- }
- verify_tlab();
-}
-
-// Preserves rbx, and rdx.
-void MacroAssembler::tlab_refill(Label& retry, Label& try_eden, Label& slow_case) {
- Register top = rax;
- Register t1 = rcx;
- Register t2 = rsi;
- Register thread_reg = rdi;
- assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx);
- Label do_refill, discard_tlab;
-
- if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
- // No allocation in the shared eden.
- jmp(slow_case);
- }
-
- get_thread(thread_reg);
-
- movl(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
- movl(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
-
- // calculate amount of free space
- subl(t1, top);
- shrl(t1, LogHeapWordSize);
-
- // Retain tlab and allocate object in shared space if
- // the amount free in the tlab is too large to discard.
- cmpl(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
- jcc(Assembler::lessEqual, discard_tlab);
-
- // Retain
- movl(t2, ThreadLocalAllocBuffer::refill_waste_limit_increment());
- addl(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2);
- if (TLABStats) {
- // increment number of slow_allocations
- addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1);
- }
- jmp(try_eden);
-
- bind(discard_tlab);
- if (TLABStats) {
- // increment number of refills
- addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1);
- // accumulate wastage -- t1 is amount free in tlab
- addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1);
- }
-
- // if tlab is currently allocated (top or end != null) then
- // fill [top, end + alignment_reserve) with array object
- testl (top, top);
- jcc(Assembler::zero, do_refill);
-
- // set up the mark word
- movl(Address(top, oopDesc::mark_offset_in_bytes()), (int)markOopDesc::prototype()->copy_set_hash(0x2));
- // set the length to the remaining space
- subl(t1, typeArrayOopDesc::header_size(T_INT));
- addl(t1, ThreadLocalAllocBuffer::alignment_reserve());
- shll(t1, log2_intptr(HeapWordSize/sizeof(jint)));
- movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1);
- // set klass to intArrayKlass
- // dubious reloc why not an oop reloc?
- movptr(t1, ExternalAddress((address) Universe::intArrayKlassObj_addr()));
- movl(Address(top, oopDesc::klass_offset_in_bytes()), t1);
-
- // refill the tlab with an eden allocation
- bind(do_refill);
- movl(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
- shll(t1, LogHeapWordSize);
- // add object_size ??
- eden_allocate(top, t1, 0, t2, slow_case);
-
- // Check that t1 was preserved in eden_allocate.
-#ifdef ASSERT
- if (UseTLAB) {
- Label ok;
- Register tsize = rsi;
- assert_different_registers(tsize, thread_reg, t1);
- pushl(tsize);
- movl(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
- shll(tsize, LogHeapWordSize);
- cmpl(t1, tsize);
- jcc(Assembler::equal, ok);
- stop("assert(t1 != tlab size)");
- should_not_reach_here();
-
- bind(ok);
- popl(tsize);
- }
-#endif
- movl(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top);
- movl(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top);
- addl(top, t1);
- subl(top, ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
- movl(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top);
- verify_tlab();
- jmp(retry);
-}
-
-
-int MacroAssembler::biased_locking_enter(Register lock_reg, Register obj_reg, Register swap_reg, Register tmp_reg,
- bool swap_reg_contains_mark,
- Label& done, Label* slow_case,
- BiasedLockingCounters* counters) {
- assert(UseBiasedLocking, "why call this otherwise?");
- assert(swap_reg == rax, "swap_reg must be rax, for cmpxchg");
- assert_different_registers(lock_reg, obj_reg, swap_reg);
-
- if (PrintBiasedLockingStatistics && counters == NULL)
- counters = BiasedLocking::counters();
-
- bool need_tmp_reg = false;
- if (tmp_reg == noreg) {
- need_tmp_reg = true;
- tmp_reg = lock_reg;
- } else {
- assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
- }
- assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
- Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
- Address klass_addr (obj_reg, oopDesc::klass_offset_in_bytes());
- Address saved_mark_addr(lock_reg, 0);
-
- // Biased locking
- // See whether the lock is currently biased toward our thread and
- // whether the epoch is still valid
- // Note that the runtime guarantees sufficient alignment of JavaThread
- // pointers to allow age to be placed into low bits
- // First check to see whether biasing is even enabled for this object
- Label cas_label;
- int null_check_offset = -1;
- if (!swap_reg_contains_mark) {
- null_check_offset = offset();
- movl(swap_reg, mark_addr);
- }
- if (need_tmp_reg) {
- pushl(tmp_reg);
- }
- movl(tmp_reg, swap_reg);
- andl(tmp_reg, markOopDesc::biased_lock_mask_in_place);
- cmpl(tmp_reg, markOopDesc::biased_lock_pattern);
- if (need_tmp_reg) {
- popl(tmp_reg);
- }
- jcc(Assembler::notEqual, cas_label);
- // The bias pattern is present in the object's header. Need to check
- // whether the bias owner and the epoch are both still current.
- // Note that because there is no current thread register on x86 we
- // need to store off the mark word we read out of the object to
- // avoid reloading it and needing to recheck invariants below. This
- // store is unfortunate but it makes the overall code shorter and
- // simpler.
- movl(saved_mark_addr, swap_reg);
- if (need_tmp_reg) {
- pushl(tmp_reg);
- }
- get_thread(tmp_reg);
- xorl(swap_reg, tmp_reg);
- if (swap_reg_contains_mark) {
- null_check_offset = offset();
- }
- movl(tmp_reg, klass_addr);
- xorl(swap_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
- andl(swap_reg, ~((int) markOopDesc::age_mask_in_place));
- if (need_tmp_reg) {
- popl(tmp_reg);
- }
- if (counters != NULL) {
- cond_inc32(Assembler::zero,
- ExternalAddress((address)counters->biased_lock_entry_count_addr()));
- }
- jcc(Assembler::equal, done);
-
- Label try_revoke_bias;
- Label try_rebias;
-
- // At this point we know that the header has the bias pattern and
- // that we are not the bias owner in the current epoch. We need to
- // figure out more details about the state of the header in order to
- // know what operations can be legally performed on the object's
- // header.
-
- // If the low three bits in the xor result aren't clear, that means
- // the prototype header is no longer biased and we have to revoke
- // the bias on this object.
- testl(swap_reg, markOopDesc::biased_lock_mask_in_place);
- jcc(Assembler::notZero, try_revoke_bias);
-
- // Biasing is still enabled for this data type. See whether the
- // epoch of the current bias is still valid, meaning that the epoch
- // bits of the mark word are equal to the epoch bits of the
- // prototype header. (Note that the prototype header's epoch bits
- // only change at a safepoint.) If not, attempt to rebias the object
- // toward the current thread. Note that we must be absolutely sure
- // that the current epoch is invalid in order to do this because
- // otherwise the manipulations it performs on the mark word are
- // illegal.
- testl(swap_reg, markOopDesc::epoch_mask_in_place);
- jcc(Assembler::notZero, try_rebias);
-
- // The epoch of the current bias is still valid but we know nothing
- // about the owner; it might be set or it might be clear. Try to
- // acquire the bias of the object using an atomic operation. If this
- // fails we will go in to the runtime to revoke the object's bias.
- // Note that we first construct the presumed unbiased header so we
- // don't accidentally blow away another thread's valid bias.
- movl(swap_reg, saved_mark_addr);
- andl(swap_reg,
- markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
- if (need_tmp_reg) {
- pushl(tmp_reg);
- }
- get_thread(tmp_reg);
- orl(tmp_reg, swap_reg);
- if (os::is_MP()) {
- lock();
- }
- cmpxchg(tmp_reg, Address(obj_reg, 0));
- if (need_tmp_reg) {
- popl(tmp_reg);
- }
- // If the biasing toward our thread failed, this means that
- // another thread succeeded in biasing it toward itself and we
- // need to revoke that bias. The revocation will occur in the
- // interpreter runtime in the slow case.
- if (counters != NULL) {
- cond_inc32(Assembler::zero,
- ExternalAddress((address)counters->anonymously_biased_lock_entry_count_addr()));
- }
- if (slow_case != NULL) {
- jcc(Assembler::notZero, *slow_case);
- }
- jmp(done);
-
- bind(try_rebias);
- // At this point we know the epoch has expired, meaning that the
- // current "bias owner", if any, is actually invalid. Under these
- // circumstances _only_, we are allowed to use the current header's
- // value as the comparison value when doing the cas to acquire the
- // bias in the current epoch. In other words, we allow transfer of
- // the bias from one thread to another directly in this situation.
- //
- // FIXME: due to a lack of registers we currently blow away the age
- // bits in this situation. Should attempt to preserve them.
- if (need_tmp_reg) {
- pushl(tmp_reg);
- }
- get_thread(tmp_reg);
- movl(swap_reg, klass_addr);
- orl(tmp_reg, Address(swap_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
- movl(swap_reg, saved_mark_addr);
- if (os::is_MP()) {
- lock();
- }
- cmpxchg(tmp_reg, Address(obj_reg, 0));
- if (need_tmp_reg) {
- popl(tmp_reg);
- }
- // If the biasing toward our thread failed, then another thread
- // succeeded in biasing it toward itself and we need to revoke that
- // bias. The revocation will occur in the runtime in the slow case.
- if (counters != NULL) {
- cond_inc32(Assembler::zero,
- ExternalAddress((address)counters->rebiased_lock_entry_count_addr()));
- }
- if (slow_case != NULL) {
- jcc(Assembler::notZero, *slow_case);
- }
- jmp(done);
-
- bind(try_revoke_bias);
- // The prototype mark in the klass doesn't have the bias bit set any
- // more, indicating that objects of this data type are not supposed
- // to be biased any more. We are going to try to reset the mark of
- // this object to the prototype value and fall through to the
- // CAS-based locking scheme. Note that if our CAS fails, it means
- // that another thread raced us for the privilege of revoking the
- // bias of this particular object, so it's okay to continue in the
- // normal locking code.
- //
- // FIXME: due to a lack of registers we currently blow away the age
- // bits in this situation. Should attempt to preserve them.
- movl(swap_reg, saved_mark_addr);
- if (need_tmp_reg) {
- pushl(tmp_reg);
- }
- movl(tmp_reg, klass_addr);
- movl(tmp_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
- if (os::is_MP()) {
- lock();
- }
- cmpxchg(tmp_reg, Address(obj_reg, 0));
- if (need_tmp_reg) {
- popl(tmp_reg);
- }
- // Fall through to the normal CAS-based lock, because no matter what
- // the result of the above CAS, some thread must have succeeded in
- // removing the bias bit from the object's header.
- if (counters != NULL) {
- cond_inc32(Assembler::zero,
- ExternalAddress((address)counters->revoked_lock_entry_count_addr()));
- }
-
- bind(cas_label);
-
- return null_check_offset;
-}
-
-
-void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
- assert(UseBiasedLocking, "why call this otherwise?");
-
- // Check for biased locking unlock case, which is a no-op
- // Note: we do not have to check the thread ID for two reasons.
- // First, the interpreter checks for IllegalMonitorStateException at
- // a higher level. Second, if the bias was revoked while we held the
- // lock, the object could not be rebiased toward another thread, so
- // the bias bit would be clear.
- movl(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
- andl(temp_reg, markOopDesc::biased_lock_mask_in_place);
- cmpl(temp_reg, markOopDesc::biased_lock_pattern);
- jcc(Assembler::equal, done);
-}
-
-
-Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
- switch (cond) {
- // Note some conditions are synonyms for others
- case Assembler::zero: return Assembler::notZero;
- case Assembler::notZero: return Assembler::zero;
- case Assembler::less: return Assembler::greaterEqual;
- case Assembler::lessEqual: return Assembler::greater;
- case Assembler::greater: return Assembler::lessEqual;
- case Assembler::greaterEqual: return Assembler::less;
- case Assembler::below: return Assembler::aboveEqual;
- case Assembler::belowEqual: return Assembler::above;
- case Assembler::above: return Assembler::belowEqual;
- case Assembler::aboveEqual: return Assembler::below;
- case Assembler::overflow: return Assembler::noOverflow;
- case Assembler::noOverflow: return Assembler::overflow;
- case Assembler::negative: return Assembler::positive;
- case Assembler::positive: return Assembler::negative;
- case Assembler::parity: return Assembler::noParity;
- case Assembler::noParity: return Assembler::parity;
- }
- ShouldNotReachHere(); return Assembler::overflow;
-}
-
-
-void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
- Condition negated_cond = negate_condition(cond);
- Label L;
- jcc(negated_cond, L);
- atomic_incl(counter_addr);
- bind(L);
-}
-
-void MacroAssembler::atomic_incl(AddressLiteral counter_addr) {
- pushfd();
- if (os::is_MP())
- lock();
- increment(counter_addr);
- popfd();
-}
-
-SkipIfEqual::SkipIfEqual(
- MacroAssembler* masm, const bool* flag_addr, bool value) {
- _masm = masm;
- _masm->cmp8(ExternalAddress((address)flag_addr), value);
- _masm->jcc(Assembler::equal, _label);
-}
-
-SkipIfEqual::~SkipIfEqual() {
- _masm->bind(_label);
-}
-
-
-// Writes to stack successive pages until offset reached to check for
-// stack overflow + shadow pages. This clobbers tmp.
-void MacroAssembler::bang_stack_size(Register size, Register tmp) {
- movl(tmp, rsp);
- // Bang stack for total size given plus shadow page size.
- // Bang one page at a time because large size can bang beyond yellow and
- // red zones.
- Label loop;
- bind(loop);
- movl(Address(tmp, (-os::vm_page_size())), size );
- subl(tmp, os::vm_page_size());
- subl(size, os::vm_page_size());
- jcc(Assembler::greater, loop);
-
- // Bang down shadow pages too.
- // The -1 because we already subtracted 1 page.
- for (int i = 0; i< StackShadowPages-1; i++) {
- movl(Address(tmp, (-i*os::vm_page_size())), size );
- }
-}
diff --git a/hotspot/src/cpu/x86/vm/assembler_x86_32.inline.hpp b/hotspot/src/cpu/x86/vm/assembler_x86_32.inline.hpp
deleted file mode 100644
index 8e20a2e0620..00000000000
--- a/hotspot/src/cpu/x86/vm/assembler_x86_32.inline.hpp
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright 1997-2005 Sun Microsystems, Inc. All Rights Reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
- * CA 95054 USA or visit www.sun.com if you need additional information or
- * have any questions.
- *
- */
-
-inline void MacroAssembler::pd_patch_instruction(address branch, address target) {
- unsigned char op = branch[0];
- assert(op == 0xE8 /* call */ ||
- op == 0xE9 /* jmp */ ||
- op == 0xEB /* short jmp */ ||
- (op & 0xF0) == 0x70 /* short jcc */ ||
- op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */,
- "Invalid opcode at patch point");
-
- if (op == 0xEB || (op & 0xF0) == 0x70) {
- // short offset operators (jmp and jcc)
- char* disp = (char*) &branch[1];
- int imm8 = target - (address) &disp[1];
- guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset");
- *disp = imm8;
- } else {
- int* disp = (int*) &branch[(op == 0x0F)? 2: 1];
- int imm32 = target - (address) &disp[1];
- *disp = imm32;
- }
-}
-
-#ifndef PRODUCT
-inline void MacroAssembler::pd_print_patched_instruction(address branch) {
- const char* s;
- unsigned char op = branch[0];
- if (op == 0xE8) {
- s = "call";
- } else if (op == 0xE9 || op == 0xEB) {
- s = "jmp";
- } else if ((op & 0xF0) == 0x70) {
- s = "jcc";
- } else if (op == 0x0F) {
- s = "jcc";
- } else {
- s = "????";
- }
- tty->print("%s (unresolved)", s);
-}
-#endif // ndef PRODUCT
diff --git a/hotspot/src/cpu/x86/vm/assembler_x86_64.hpp b/hotspot/src/cpu/x86/vm/assembler_x86_64.hpp
deleted file mode 100644
index bf509e02b22..00000000000
--- a/hotspot/src/cpu/x86/vm/assembler_x86_64.hpp
+++ /dev/null
@@ -1,1477 +0,0 @@
-/*
- * Copyright 2003-2008 Sun Microsystems, Inc. All Rights Reserved.
- * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
- *
- * This code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 only, as
- * published by the Free Software Foundation.
- *
- * This code is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * version 2 for more details (a copy is included in the LICENSE file that
- * accompanied this code).
- *
- * You should have received a copy of the GNU General Public License version
- * 2 along with this work; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
- * CA 95054 USA or visit www.sun.com if you need additional information or
- * have any questions.
- *
- */
-
-class BiasedLockingCounters;
-
-// Contains all the definitions needed for amd64 assembly code generation.
-
-#ifdef _LP64
-// Calling convention
-class Argument VALUE_OBJ_CLASS_SPEC {
- public:
- enum {
-#ifdef _WIN64
- n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
- n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... )
-#else
- n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
- n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... )
-#endif // _WIN64
- n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ...
- n_float_register_parameters_j = 8 // j_farg0, j_farg1, ...
- };
-};
-
-
-// Symbolically name the register arguments used by the c calling convention.
-// Windows is different from linux/solaris. So much for standards...
-
-#ifdef _WIN64
-
-REGISTER_DECLARATION(Register, c_rarg0, rcx);
-REGISTER_DECLARATION(Register, c_rarg1, rdx);
-REGISTER_DECLARATION(Register, c_rarg2, r8);
-REGISTER_DECLARATION(Register, c_rarg3, r9);
-
-REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
-REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
-REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
-REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
-
-#else
-
-REGISTER_DECLARATION(Register, c_rarg0, rdi);
-REGISTER_DECLARATION(Register, c_rarg1, rsi);
-REGISTER_DECLARATION(Register, c_rarg2, rdx);
-REGISTER_DECLARATION(Register, c_rarg3, rcx);
-REGISTER_DECLARATION(Register, c_rarg4, r8);
-REGISTER_DECLARATION(Register, c_rarg5, r9);
-
-REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
-REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
-REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
-REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
-REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);
-REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);
-REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);
-REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);
-
-#endif // _WIN64
-
-// Symbolically name the register arguments used by the Java calling convention.
-// We have control over the convention for java so we can do what we please.
-// What pleases us is to offset the java calling convention so that when
-// we call a suitable jni method the arguments are lined up and we don't
-// have to do little shuffling. A suitable jni method is non-static and a
-// small number of arguments (two fewer args on windows)
-//
-// |-------------------------------------------------------|
-// | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 |
-// |-------------------------------------------------------|
-// | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg)
-// | rdi rsi rdx rcx r8 r9 | solaris/linux
-// |-------------------------------------------------------|
-// | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 |
-// |-------------------------------------------------------|
-
-REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
-REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
-REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
-// Windows runs out of register args here
-#ifdef _WIN64
-REGISTER_DECLARATION(Register, j_rarg3, rdi);
-REGISTER_DECLARATION(Register, j_rarg4, rsi);
-#else
-REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
-REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
-#endif // _WIN64
-REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
-
-REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);
-REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);
-REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);
-REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);
-REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
-REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
-REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
-REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
-
-REGISTER_DECLARATION(Register, rscratch1, r10); // volatile
-REGISTER_DECLARATION(Register, rscratch2, r11); // volatile
-
-REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
-REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
-
-#endif // _LP64
-
-// Address is an abstraction used to represent a memory location
-// using any of the amd64 addressing modes with one object.
-//
-// Note: A register location is represented via a Register, not
-// via an address for efficiency & simplicity reasons.
-
-class ArrayAddress;
-
-class Address VALUE_OBJ_CLASS_SPEC {
- public:
- enum ScaleFactor {
- no_scale = -1,
- times_1 = 0,
- times_2 = 1,
- times_4 = 2,
- times_8 = 3
- };
-
- private:
- Register _base;
- Register _index;
- ScaleFactor _scale;
- int _disp;
- RelocationHolder _rspec;
-
- // Easily misused constructors make them private
- Address(int disp, address loc, relocInfo::relocType rtype);
- Address(int disp, address loc, RelocationHolder spec);
-
- public:
- // creation
- Address()
- : _base(noreg),
- _index(noreg),
- _scale(no_scale),
- _disp(0) {
- }
-
- // No default displacement otherwise Register can be implicitly
- // converted to 0(Register) which is quite a different animal.
-
- Address(Register base, int disp)
- : _base(base),
- _index(noreg),
- _scale(no_scale),
- _disp(disp) {
- }
-
- Address(Register base, Register index, ScaleFactor scale, int disp = 0)
- : _base (base),
- _index(index),
- _scale(scale),
- _disp (disp) {
- assert(!index->is_valid() == (scale == Address::no_scale),
- "inconsistent address");
- }
-
- // The following two overloads are used in connection with the
- // ByteSize type (see sizes.hpp). They simplify the use of
- // ByteSize'd arguments in assembly code. Note that their equivalent
- // for the optimized build are the member functions with int disp
- // argument since ByteSize is mapped to an int type in that case.
- //
- // Note: DO NOT introduce similar overloaded functions for WordSize
- // arguments as in the optimized mode, both ByteSize and WordSize
- // are mapped to the same type and thus the compiler cannot make a
- // distinction anymore (=> compiler errors).
-
-#ifdef ASSERT
- Address(Register base, ByteSize disp)
- : _base(base),
- _index(noreg),
- _scale(no_scale),
- _disp(in_bytes(disp)) {
- }
-
- Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
- : _base(base),
- _index(index),
- _scale(scale),
- _disp(in_bytes(disp)) {
- assert(!index->is_valid() == (scale == Address::no_scale),
- "inconsistent address");
- }
-#endif // ASSERT
-
- // accessors
- bool uses(Register reg) const {
- return _base == reg || _index == reg;
- }
-
- // Convert the raw encoding form into the form expected by the constructor for
- // Address. An index of 4 (rsp) corresponds to having no index, so convert
- // that to noreg for the Address constructor.
- static Address make_raw(int base, int index, int scale, int disp);
-
- static Address make_array(ArrayAddress);
-
- private:
- bool base_needs_rex() const {
- return _base != noreg && _base->encoding() >= 8;
- }
-
- bool index_needs_rex() const {
- return _index != noreg &&_index->encoding() >= 8;
- }
-
- relocInfo::relocType reloc() const { return _rspec.type(); }
-
- friend class Assembler;
- friend class MacroAssembler;
- friend class LIR_Assembler; // base/index/scale/disp
-};
-
-//
-// AddressLiteral has been split out from Address because operands of this type
-// need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
-// the few instructions that need to deal with address literals are unique and the
-// MacroAssembler does not have to implement every instruction in the Assembler
-// in order to search for address literals that may need special handling depending
-// on the instruction and the platform. As small step on the way to merging i486/amd64
-// directories.
-//
-class AddressLiteral VALUE_OBJ_CLASS_SPEC {
- friend class ArrayAddress;
- RelocationHolder _rspec;
- // Typically we use AddressLiterals we want to use their rval
- // However in some situations we want the lval (effect address) of the item.
- // We provide a special factory for making those lvals.
- bool _is_lval;
-
- // If the target is far we'll need to load the ea of this to
- // a register to reach it. Otherwise if near we can do rip
- // relative addressing.
-
- address _target;
-
- protected:
- // creation
- AddressLiteral()
- : _is_lval(false),
- _target(NULL)
- {}
-
- public:
-
-
- AddressLiteral(address target, relocInfo::relocType rtype);
-
- AddressLiteral(address target, RelocationHolder const& rspec)
- : _rspec(rspec),
- _is_lval(false),
- _target(target)
- {}
-
- AddressLiteral addr() {
- AddressLiteral ret = *this;
- ret._is_lval = true;
- return ret;
- }
-
-
- private:
-
- address target() { return _target; }
- bool is_lval() { return _is_lval; }
-
- relocInfo::relocType reloc() const { return _rspec.type(); }
- const RelocationHolder& rspec() const { return _rspec; }
-
- friend class Assembler;
- friend class MacroAssembler;
- friend class Address;
- friend class LIR_Assembler;
-};
-
-// Convience classes
-class RuntimeAddress: public AddressLiteral {
-
- public:
-
- RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
-
-};
-
-class OopAddress: public AddressLiteral {
-
- public:
-
- OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){}
-
-};
-
-class ExternalAddress: public AddressLiteral {
-
- public:
-
- ExternalAddress(address target) : AddressLiteral(target, relocInfo::external_word_type){}
-
-};
-
-class InternalAddress: public AddressLiteral {
-
- public:
-
- InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
-
-};
-
-// x86 can do array addressing as a single operation since disp can be an absolute
-// address but amd64 can't [e.g. array_base(rx, ry:width) ]. We create a class
-// that expresses the concept but does extra magic on amd64 to get the final result
-
-class ArrayAddress VALUE_OBJ_CLASS_SPEC {
- private:
-
- AddressLiteral _base;
- Address _index;
-
- public:
-
- ArrayAddress() {};
- ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
- AddressLiteral base() { return _base; }
- Address index() { return _index; }
-
-};
-
-// The amd64 Assembler: Pure assembler doing NO optimizations on
-// the instruction level (e.g. mov rax, 0 is not translated into xor
-// rax, rax!); i.e., what you write is what you get. The Assembler is
-// generating code into a CodeBuffer.
-
-const int FPUStateSizeInWords = 512 / wordSize;
-
-class Assembler : public AbstractAssembler {
- friend class AbstractAssembler; // for the non-virtual hack
- friend class StubGenerator;
-
-
- protected:
-#ifdef ASSERT
- void check_relocation(RelocationHolder const& rspec, int format);
-#endif
-
- inline void emit_long64(jlong x);
-
- void emit_data(jint data, relocInfo::relocType rtype, int format /* = 1 */);
- void emit_data(jint data, RelocationHolder const& rspec, int format /* = 1 */);
- void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
- void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
-
- // Helper functions for groups of instructions
- void emit_arith_b(int op1, int op2, Register dst, int imm8);
-
- void emit_arith(int op1, int op2, Register dst, int imm32);
- // only x86??
- void emit_arith(int op1, int op2, Register dst, jobject obj);
- void emit_arith(int op1, int op2, Register dst, Register src);
-
- void emit_operand(Register reg,
- Register base, Register index, Address::ScaleFactor scale,
- int disp,
- RelocationHolder const& rspec,
- int rip_relative_correction = 0);
- void emit_operand(Register reg, Address adr,
- int rip_relative_correction = 0);
- void emit_operand(XMMRegister reg,
- Register base, Register index, Address::ScaleFactor scale,
- int disp,
- RelocationHolder const& rspec,
- int rip_relative_correction = 0);
- void emit_operand(XMMRegister reg, Address adr,
- int rip_relative_correction = 0);
-
- // Immediate-to-memory forms
- void emit_arith_operand(int op1, Register rm, Address adr, int imm32);
-
- void emit_farith(int b1, int b2, int i);
-
- bool reachable(AddressLiteral adr);
-
- // These are all easily abused and hence protected
-
- // Make these disappear in 64bit mode since they would never be correct
-#ifndef _LP64
- void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec);
- void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec);
-
- void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec);
- void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec);
-
- void push_literal32(int32_t imm32, RelocationHolder const& rspec);
-#endif // _LP64
-
-
- void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec);
-
- // These are unique in that we are ensured by the caller that the 32bit
- // relative in these instructions will always be able to reach the potentially
- // 64bit address described by entry. Since they can take a 64bit address they
- // don't have the 32 suffix like the other instructions in this class.
- void jmp_literal(address entry, RelocationHolder const& rspec);
- void call_literal(address entry, RelocationHolder const& rspec);
-
- public:
- enum Condition { // The amd64 condition codes used for conditional jumps/moves.
- zero = 0x4,
- notZero = 0x5,
- equal = 0x4,
- notEqual = 0x5,
- less = 0xc,
- lessEqual = 0xe,
- greater = 0xf,
- greaterEqual = 0xd,
- below = 0x2,
- belowEqual = 0x6,
- above = 0x7,
- aboveEqual = 0x3,
- overflow = 0x0,
- noOverflow = 0x1,
- carrySet = 0x2,
- carryClear = 0x3,
- negative = 0x8,
- positive = 0x9,
- parity = 0xa,
- noParity = 0xb
- };
-
- enum Prefix {
- // segment overrides
- // XXX remove segment prefixes
- CS_segment = 0x2e,
- SS_segment = 0x36,
- DS_segment = 0x3e,
- ES_segment = 0x26,
- FS_segment = 0x64,
- GS_segment = 0x65,
-
- REX = 0x40,
-
- REX_B = 0x41,
- REX_X = 0x42,
- REX_XB = 0x43,
- REX_R = 0x44,
- REX_RB = 0x45,
- REX_RX = 0x46,
- REX_RXB = 0x47,
-
- REX_W = 0x48,
-
- REX_WB = 0x49,
- REX_WX = 0x4A,
- REX_WXB = 0x4B,
- REX_WR = 0x4C,
- REX_WRB = 0x4D,
- REX_WRX = 0x4E,
- REX_WRXB = 0x4F
- };
-
- enum WhichOperand {
- // input to locate_operand, and format code for relocations
- imm64_operand = 0, // embedded 64-bit immediate operand
- disp32_operand = 1, // embedded 32-bit displacement
- call32_operand = 2, // embedded 32-bit self-relative displacement
-#ifndef AMD64
- _WhichOperand_limit = 3
-#else
- narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop
- _WhichOperand_limit = 4
-#endif
- };
-
- public:
-
- // Creation
- Assembler(CodeBuffer* code)
- : AbstractAssembler(code) {
- }
-
- // Decoding
- static address locate_operand(address inst, WhichOperand which);
- static address locate_next_instruction(address inst);
-
- // Utilities
-
- static bool is_simm(int64_t x, int nbits) { return -( CONST64(1) << (nbits-1) ) <= x && x < ( CONST64(1) << (nbits-1) ); }
- static bool is_simm32 (int64_t x) { return x == (int64_t)(int32_t)x; }
-
-
- // Stack
- void pushaq();
- void popaq();
-
- void pushfq();
- void popfq();
-
- void pushq(int imm32);
-
- void pushq(Register src);
- void pushq(Address src);
-
- void popq(Register dst);
- void popq(Address dst);
-
- // Instruction prefixes
- void prefix(Prefix p);
-
- int prefix_and_encode(int reg_enc, bool byteinst = false);
- int prefixq_and_encode(int reg_enc);
-
- int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false);
- int prefixq_and_encode(int dst_enc, int src_enc);
-
- void prefix(Register reg);
- void prefix(Address adr);
- void prefixq(Address adr);
-
- void prefix(Address adr, Register reg, bool byteinst = false);
- void prefixq(Address adr, Register reg);
-
- void prefix(Address adr, XMMRegister reg);
-
- // Moves
- void movb(Register dst, Address src);
- void movb(Address dst, int imm8);
- void movb(Address dst, Register src);
-
- void movw(Address dst, int imm16);
- void movw(Register dst, Address src);
- void movw(Address dst, Register src);
-
- void movl(Register dst, int imm32);
- void movl(Register dst, Register src);
- void movl(Register dst, Address src);
- void movl(Address dst, int imm32);
- void movl(Address dst, Register src);
-
- void movq(Register dst, Register src);
- void movq(Register dst, Address src);
- void movq(Address dst, Register src);
- // These prevent using movq from converting a zero (like NULL) into Register
- // by giving the compiler two choices it can't resolve
- void movq(Address dst, void* dummy);
- void movq(Register dst, void* dummy);
-
- void mov64(Register dst, intptr_t imm64);
- void mov64(Address dst, intptr_t imm64);
-
- void movsbl(Register dst, Address src);
- void movsbl(Register dst, Register src);
- void movswl(Register dst, Address src);
- void movswl(Register dst, Register src);
- void movslq(Register dst, Address src);
- void movslq(Register dst, Register src);
-
- void movzbl(Register dst, Address src);
- void movzbl(Register dst, Register src);
- void movzwl(Register dst, Address src);
- void movzwl(Register dst, Register src);
-
- protected: // Avoid using the next instructions directly.
- // New cpus require use of movsd and movss to avoid partial register stall
- // when loading from memory. But for old Opteron use movlpd instead of movsd.
- // The selection is done in MacroAssembler::movdbl() and movflt().
- void movss(XMMRegister dst, XMMRegister src);
- void movss(XMMRegister dst, Address src);
- void movss(Address dst, XMMRegister src);
- void movsd(XMMRegister dst, XMMRegister src);
- void movsd(Address dst, XMMRegister src);
- void movsd(XMMRegister dst, Address src);
- void movlpd(XMMRegister dst, Address src);
- // New cpus require use of movaps and movapd to avoid partial register stall
- // when moving between registers.
- void movapd(XMMRegister dst, XMMRegister src);
- void movaps(XMMRegister dst, XMMRegister src);
- public:
-
- void movdl(XMMRegister dst, Register src);
- void movdl(Register dst, XMMRegister src);
- void movdq(XMMRegister dst, Register src);
- void movdq(Register dst, XMMRegister src);
-
- void cmovl(Condition cc, Register dst, Register src);
- void cmovl(Condition cc, Register dst, Address src);
- void cmovq(Condition cc, Register dst, Register src);
- void cmovq(Condition cc, Register dst, Address src);
-
- // Prefetches
- private:
- void prefetch_prefix(Address src);
- public:
- void prefetcht0(Address src);
- void prefetcht1(Address src);
- void prefetcht2(Address src);
- void prefetchnta(Address src);
- void prefetchw(Address src);
-
- // Arithmetics
- void adcl(Register dst, int imm32);
- void adcl(Register dst, Address src);
- void adcl(Register dst, Register src);
- void adcq(Register dst, int imm32);
- void adcq(Register dst, Address src);
- void adcq(Register dst, Register src);
-
- void addl(Address dst, int imm32);
- void addl(Address dst, Register src);
- void addl(Register dst, int imm32);
- void addl(Register dst, Address src);
- void addl(Register dst, Register src);
- void addq(Address dst, int imm32);
- void addq(Address dst, Register src);
- void addq(Register dst, int imm32);
- void addq(Register dst, Address src);
- void addq(Register dst, Register src);
-
- void andl(Register dst, int imm32);
- void andl(Register dst, Address src);
- void andl(Register dst, Register src);
- void andq(Register dst, int imm32);
- void andq(Register dst, Address src);
- void andq(Register dst, Register src);
-
- void cmpb(Address dst, int imm8);
- void cmpl(Address dst, int imm32);
- void cmpl(Register dst, int imm32);
- void cmpl(Register dst, Register src);
- void cmpl(Register dst, Address src);
- void cmpq(Address dst, int imm32);
- void cmpq(Address dst, Register src);
- void cmpq(Register dst, int imm32);
- void cmpq(Register dst, Register src);
- void cmpq(Register dst, Address src);
-
- void ucomiss(XMMRegister dst, XMMRegister src);
- void ucomisd(XMMRegister dst, XMMRegister src);
-
- protected:
- // Don't use next inc() and dec() methods directly. INC & DEC instructions
- // could cause a partial flag stall since they don't set CF flag.
- // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
- // which call inc() & dec() or add() & sub() in accordance with
- // the product flag UseIncDec value.
-
- void decl(Register dst);
- void decl(Address dst);
- void decq(Register dst);
- void decq(Address dst);
-
- void incl(Register dst);
- void incl(Address dst);
- void incq(Register dst);
- void incq(Address dst);
-
- public:
- void idivl(Register src);
- void idivq(Register src);
- void cdql();
- void cdqq();
-
- void imull(Register dst, Register src);
- void imull(Register dst, Register src, int value);
- void imulq(Register dst, Register src);
- void imulq(Register dst, Register src, int value);
-
- void leal(Register dst, Address src);
- void leaq(Register dst, Address src);
-
- void mull(Address src);
- void mull(Register src);
-
- void negl(Register dst);
- void negq(Register dst);
-
- void notl(Register dst);
- void notq(Register dst);
-
- void orl(Address dst, int imm32);
- void orl(Register dst, int imm32);
- void orl(Register dst, Address src);
- void orl(Register dst, Register src);
- void orq(Address dst, int imm32);
- void orq(Register dst, int imm32);
- void orq(Register dst, Address src);
- void orq(Register dst, Register src);
-
- void rcll(Register dst, int imm8);
- void rclq(Register dst, int imm8);
-
- void sarl(Register dst, int imm8);
- void sarl(Register dst);
- void sarq(Register dst, int imm8);
- void sarq(Register dst);
-
- void sbbl(Address dst, int imm32);
- void sbbl(Register dst, int imm32);
- void sbbl(Register dst, Address src);
- void sbbl(Register dst, Register src);
- void sbbq(Address dst, int imm32);
- void sbbq(Register dst, int imm32);
- void sbbq(Register dst, Address src);
- void sbbq(Register dst, Register src);
-
- void shll(Register dst, int imm8);
- void shll(Register dst);
- void shlq(Register dst, int imm8);
- void shlq(Register dst);
-
- void shrl(Register dst, int imm8);
- void shrl(Register dst);
- void shrq(Register dst, int imm8);
- void shrq(Register dst);
-
- void subl(Address dst, int imm32);
- void subl(Address dst, Register src);
- void subl(Register dst, int imm32);
- void subl(Register dst, Address src);
- void subl(Register dst, Register src);
- void subq(Address dst, int imm32);
- void subq(Address dst, Register src);
- void subq(Register dst, int imm32);
- void subq(Register dst, Address src);
- void subq(Register dst, Register src);
-
- void testb(Register dst, int imm8);
- void testl(Register dst, int imm32);
- void testl(Register dst, Register src);
- void testq(Register dst, int imm32);
- void testq(Register dst, Register src);
-
- void xaddl(Address dst, Register src);
- void xaddq(Address dst, Register src);
-
- void xorl(Register dst, int imm32);
- void xorl(Register dst, Address src);
- void xorl(Register dst, Register src);
- void xorq(Register dst, int imm32);
- void xorq(Register dst, Address src);
- void xorq(Register dst, Register src);
-
- // Miscellaneous
- void bswapl(Register reg);
- void bswapq(Register reg);
- void lock();
-
- void xchgl(Register reg, Address adr);
- void xchgl(Register dst, Register src);
- void xchgq(Register reg, Address adr);
- void xchgq(Register dst, Register src);
-
- void cmpxchgl(Register reg, Address adr);
- void cmpxchgq(Register reg, Address adr);
-
- void nop(int i = 1);
- void addr_nop_4();
- void addr_nop_5();
- void addr_nop_7();
- void addr_nop_8();
-
- void hlt();
- void ret(int imm16);
- void smovl();
- void rep_movl();
- void rep_movq();
- void rep_set();
- void repne_scanl();
- void repne_scanq();
- void setb(Condition cc, Register dst);
-
- void clflush(Address adr);
-
- enum Membar_mask_bits {
- StoreStore = 1 << 3,
- LoadStore = 1 << 2,
- StoreLoad = 1 << 1,
- LoadLoad = 1 << 0
- };
-
- // Serializes memory.
- void membar(Membar_mask_bits order_constraint) {
- // We only have to handle StoreLoad and LoadLoad
- if (order_constraint & StoreLoad) {
- // MFENCE subsumes LFENCE
- mfence();
- } /* [jk] not needed currently: else if (order_constraint & LoadLoad) {
- lfence();
- } */
- }
-
- void lfence() {
- emit_byte(0x0F);
- emit_byte(0xAE);
- emit_byte(0xE8);
- }
-
- void mfence() {
- emit_byte(0x0F);
- emit_byte(0xAE);
- emit_byte(0xF0);
- }
-
- // Identify processor type and features
- void cpuid() {
- emit_byte(0x0F);
- emit_byte(0xA2);
- }
-
- void cld() { emit_byte(0xfc);
- }
-
- void std() { emit_byte(0xfd);
- }
-
-
- // Calls
-
- void call(Label& L, relocInfo::relocType rtype);
- void call(Register reg);
- void call(Address adr);
-
- // Jumps
-
- void jmp(Register reg);
- void jmp(Address adr);
-
- // Label operations & relative jumps (PPUM Appendix D)
- // unconditional jump to L
- void jmp(Label& L, relocInfo::relocType rtype = relocInfo::none);
-
-
- // Unconditional 8-bit offset jump to L.
- // WARNING: be very careful using this for forward jumps. If the label is
- // not bound within an 8-bit offset of this instruction, a run-time error
- // will occur.
- void jmpb(Label& L);
-
- // jcc is the generic conditional branch generator to run- time
- // routines, jcc is used for branches to labels. jcc takes a branch
- // opcode (cc) and a label (L) and generates either a backward
- // branch or a forward branch and links it to the label fixup
- // chain. Usage:
- //
- // Label L; // unbound label
- // jcc(cc, L); // forward branch to unbound label
- // bind(L); // bind label to the current pc
- // jcc(cc, L); // backward branch to bound label
- // bind(L); // illegal: a label may be bound only once
- //
- // Note: The same Label can be used for forward and backward branches
- // but it may be bound only once.
-
- void jcc(Condition cc, Label& L,
- relocInfo::relocType rtype = relocInfo::none);
-
- // Conditional jump to a 8-bit offset to L.
- // WARNING: be very careful using this for forward jumps. If the label is
- // not bound within an 8-bit offset of this instruction, a run-time error
- // will occur.
- void jccb(Condition cc, Label& L);
-
- // Floating-point operations
-
- void fxsave(Address dst);
- void fxrstor(Address src);
- void ldmxcsr(Address src);
- void stmxcsr(Address dst);
-
- void addss(XMMRegister dst, XMMRegister src);
- void addss(XMMRegister dst, Address src);
- void subss(XMMRegister dst, XMMRegister src);
- void subss(XMMRegister dst, Address src);
- void mulss(XMMRegister dst, XMMRegister src);
- void mulss(XMMRegister dst, Address src);
- void divss(XMMRegister dst, XMMRegister src);
- void divss(XMMRegister dst, Address src);
- void addsd(XMMRegister dst, XMMRegister src);
- void addsd(XMMRegister dst, Address src);
- void subsd(XMMRegister dst, XMMRegister src);
- void subsd(XMMRegister dst, Address src);
- void mulsd(XMMRegister dst, XMMRegister src);
- void mulsd(XMMRegister dst, Address src);
- void divsd(XMMRegister dst, XMMRegister src);
- void divsd(XMMRegister dst, Address src);
-
- // We only need the double form
- void sqrtsd(XMMRegister dst, XMMRegister src);
- void sqrtsd(XMMRegister dst, Address src);
-
- void xorps(XMMRegister dst, XMMRegister src);
- void xorps(XMMRegister dst, Address src);
- void xorpd(XMMRegister dst, XMMRegister src);
- void xorpd(XMMRegister dst, Address src);
-
- void cvtsi2ssl(XMMRegister dst, Register src);
- void cvtsi2ssq(XMMRegister dst, Register src);
- void cvtsi2sdl(XMMRegister dst, Register src);
- void cvtsi2sdq(XMMRegister dst, Register src);
- void cvttss2sil(Register dst, XMMRegister src); // truncates
- void cvttss2siq(Register dst, XMMRegister src); // truncates
- void cvttsd2sil(Register dst, XMMRegister src); // truncates
- void cvttsd2siq(Register dst, XMMRegister src); // truncates
- void cvtss2sd(XMMRegister dst, XMMRegister src);
- void cvtsd2ss(XMMRegister dst, XMMRegister src);
- void cvtdq2pd(XMMRegister dst, XMMRegister src);
- void cvtdq2ps(XMMRegister dst, XMMRegister src);
-
- void pxor(XMMRegister dst, Address src); // Xor Packed Byte Integer Values
- void pxor(XMMRegister dst, XMMRegister src); // Xor Packed Byte Integer Values
-
- void movdqa(XMMRegister dst, Address src); // Move Aligned Double Quadword
- void movdqa(XMMRegister dst, XMMRegister src);
- void movdqa(Address dst, XMMRegister src);
-
- void movq(XMMRegister dst, Address src);
- void movq(Address dst, XMMRegister src);
-
- void pshufd(XMMRegister dst, XMMRegister src, int mode); // Shuffle Packed Doublewords
- void pshufd(XMMRegister dst, Address src, int mode);
- void pshuflw(XMMRegister dst, XMMRegister src, int mode); // Shuffle Packed Low Words
- void pshuflw(XMMRegister dst, Address src, int mode);
-
- void psrlq(XMMRegister dst, int shift); // Shift Right Logical Quadword Immediate
-
- void punpcklbw(XMMRegister dst, XMMRegister src); // Interleave Low Bytes
- void punpcklbw(XMMRegister dst, Address src);
-};
-
-
-// MacroAssembler extends Assembler by frequently used macros.
-//
-// Instructions for which a 'better' code sequence exists depending
-// on arguments should also go in here.
-
-class MacroAssembler : public Assembler {
- friend class LIR_Assembler;
- protected:
-
- Address as_Address(AddressLiteral adr);
- Address as_Address(ArrayAddress adr);
-
- // Support for VM calls
- //
- // This is the base routine called by the different versions of
- // call_VM_leaf. The interpreter may customize this version by
- // overriding it for its purposes (e.g., to save/restore additional
- // registers when doing a VM call).
-
- virtual void call_VM_leaf_base(
- address entry_point, // the entry point
- int number_of_arguments // the number of arguments to
- // pop after the call
- );
-
- // This is the base routine called by the different versions of
- // call_VM. The interpreter may customize this version by overriding
- // it for its purposes (e.g., to save/restore additional registers
- // when doing a VM call).
- //
- // If no java_thread register is specified (noreg) than rdi will be
- // used instead. call_VM_base returns the register which contains
- // the thread upon return. If a thread register has been specified,
- // the return value will correspond to that register. If no
- // last_java_sp is specified (noreg) than rsp will be used instead.
- virtual void call_VM_base( // returns the register
- // containing the thread upon
- // return
- Register oop_result, // where an oop-result ends up
- // if any; use noreg otherwise
- Register java_thread, // the thread if computed
- // before ; use noreg otherwise
- Register last_java_sp, // to set up last_Java_frame in
- // stubs; use noreg otherwise
- address entry_point, // the entry point
- int number_of_arguments, // the number of arguments (w/o
- // thread) to pop after the
- // call
- bool check_exceptions // whether to check for pending
- // exceptions after return
- );
-
- // This routines should emit JVMTI PopFrame handling and ForceEarlyReturn code.
- // The implementation is only non-empty for the InterpreterMacroAssembler,
- // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
- virtual void check_and_handle_popframe(Register java_thread);
- virtual void check_and_handle_earlyret(Register java_thread);
-
- void call_VM_helper(Register oop_result,
- address entry_point,
- int number_of_arguments,
- bool check_exceptions = true);
-
- public:
- MacroAssembler(CodeBuffer* code) : Assembler(code) {}
-
- // Support for NULL-checks
- //
- // Generates code that causes a NULL OS exception if the content of
- // reg is NULL. If the accessed location is M[reg + offset] and the
- // offset is known, provide the offset. No explicit code generation
- // is needed if the offset is within a certain range (0 <= offset <=
- // page_size).
- void null_check(Register reg, int offset = -1);
- static bool needs_explicit_null_check(intptr_t offset);
-
- // Required platform-specific helpers for Label::patch_instructions.
- // They _shadow_ the declarations in AbstractAssembler, which are undefined.
- void pd_patch_instruction(address branch, address target);
-#ifndef PRODUCT
- static void pd_print_patched_instruction(address branch);
-#endif
-
-
- // The following 4 methods return the offset of the appropriate move
- // instruction. Note: these are 32 bit instructions
-
- // Support for fast byte/word loading with zero extension (depending
- // on particular CPU)
- int load_unsigned_byte(Register dst, Address src);
- int load_unsigned_word(Register dst, Address src);
-
- // Support for fast byte/word loading with sign extension (depending
- // on particular CPU)
- int load_signed_byte(Register dst, Address src);
- int load_signed_word(Register dst, Address src);
-
- // Support for inc/dec with optimal instruction selection depending
- // on value
- void incrementl(Register reg, int value = 1);
- void decrementl(Register reg, int value = 1);
- void incrementq(Register reg, int value = 1);
- void decrementq(Register reg, int value = 1);
-
- void incrementl(Address dst, int value = 1);
- void decrementl(Address dst, int value = 1);
- void incrementq(Address dst, int value = 1);
- void decrementq(Address dst, int value = 1);
-
- // Support optimal SSE move instructions.
- void movflt(XMMRegister dst, XMMRegister src) {
- if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
- else { movss (dst, src); return; }
- }
-
- void movflt(XMMRegister dst, Address src) { movss(dst, src); }
-
- void movflt(XMMRegister dst, AddressLiteral src);
-
- void movflt(Address dst, XMMRegister src) { movss(dst, src); }
-
- void movdbl(XMMRegister dst, XMMRegister src) {
- if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
- else { movsd (dst, src); return; }
- }
-
- void movdbl(XMMRegister dst, AddressLiteral src);
-
- void movdbl(XMMRegister dst, Address src) {
- if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
- else { movlpd(dst, src); return; }
- }
-
- void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
-
- void incrementl(AddressLiteral dst);
- void incrementl(ArrayAddress dst);
-
- // Alignment
- void align(int modulus);
-
- // Misc
- void fat_nop(); // 5 byte nop
-
-
- // C++ bool manipulation
-
- void movbool(Register dst, Address src);
- void movbool(Address dst, bool boolconst);
- void movbool(Address dst, Register src);
- void testbool(Register dst);
-
- // oop manipulations
- void load_klass(Register dst, Register src);
- void store_klass(Register dst, Register src);
- void store_klass_gap(Register dst, Register src);
-
- void load_prototype_header(Register dst, Register src);
-
- void load_heap_oop(Register dst, Address src);
- void store_heap_oop(Address dst, Register src);
- void encode_heap_oop(Register r);
- void decode_heap_oop(Register r);
- void encode_heap_oop_not_null(Register r);
- void decode_heap_oop_not_null(Register r);
- void encode_heap_oop_not_null(Register dst, Register src);
- void decode_heap_oop_not_null(Register dst, Register src);
-
- void set_narrow_oop(Register dst, jobject obj);
-
- // Stack frame creation/removal
- void enter();
- void leave();
-
- // Support for getting the JavaThread pointer (i.e.; a reference to
- // thread-local information) The pointer will be loaded into the
- // thread register.
- void get_thread(Register thread);
-
- void int3();
-
- // Support for VM calls
- //
- // It is imperative that all calls into the VM are handled via the
- // call_VM macros. They make sure that the stack linkage is setup
- // correctly. call_VM's correspond to ENTRY/ENTRY_X entry points
- // while call_VM_leaf's correspond to LEAF entry points.
- void call_VM(Register oop_result,
- address entry_point,
- bool check_exceptions = true);
- void call_VM(Register oop_result,
- address entry_point,
- Register arg_1,
- bool check_exceptions = true);
- void call_VM(Register oop_result,
- address entry_point,
- Register arg_1, Register arg_2,
- bool check_exceptions = true);
- void call_VM(Register oop_result,
- address entry_point,
- Register arg_1, Register arg_2, Register arg_3,
- bool check_exceptions = true);
-
- // Overloadings with last_Java_sp
- void call_VM(Register oop_result,
- Register last_java_sp,
- address entry_point,
- int number_of_arguments = 0,
- bool check_exceptions = true);
- void call_VM(Register oop_result,
- Register last_java_sp,
- address entry_point,
- Register arg_1, bool
- check_exceptions = true);
- void call_VM(Register oop_result,
- Register last_java_sp,
- address entry_point,
- Register arg_1, Register arg_2,
- bool check_exceptions = true);
- void call_VM(Register oop_result,
- Register last_java_sp,
- address entry_point,
- Register arg_1, Register arg_2, Register arg_3,
- bool check_exceptions = true);
-
- void call_VM_leaf(address entry_point,
- int number_of_arguments = 0);
- void call_VM_leaf(address entry_point,
- Register arg_1);
- void call_VM_leaf(address entry_point,
- Register arg_1, Register arg_2);
- void call_VM_leaf(address entry_point,
- Register arg_1, Register arg_2, Register arg_3);
-
- // last Java Frame (fills frame anchor)
- void set_last_Java_frame(Register last_java_sp,
- Register last_java_fp,
- address last_java_pc);
- void reset_last_Java_frame(bool clear_fp, bool clear_pc);
-
- // Stores
- void store_check(Register obj); // store check for
- // obj - register is
- // destroyed
- // afterwards
- void store_check(Register obj, Address dst); // same as above, dst
- // is exact store
- // location (reg. is
- // destroyed)
-
- // split store_check(Register obj) to enhance instruction interleaving
- void store_check_part_1(Register obj);
- void store_check_part_2(Register obj);
-
- // C 'boolean' to Java boolean: x == 0 ? 0 : 1
- void c2bool(Register x);
-
- // Int division/reminder for Java
- // (as idivl, but checks for special case as described in JVM spec.)
- // returns idivl instruction offset for implicit exception handling
- int corrected_idivl(Register reg);
- // Long division/reminder for Java
- // (as idivq, but checks for special case as described in JVM spec.)
- // returns idivq instruction offset for implicit exception handling
- int corrected_idivq(Register reg);
-
- // Push and pop integer/fpu/cpu state
- void push_IU_state();
- void pop_IU_state();
-
- void push_FPU_state();
- void pop_FPU_state();
-
- void push_CPU_state();
- void pop_CPU_state();
-
- // Sign extension
- void sign_extend_short(Register reg);
- void sign_extend_byte(Register reg);
-
- // Division by power of 2, rounding towards 0
- void division_with_shift(Register reg, int shift_value);
-
- // Round up to a power of two
- void round_to_l(Register reg, int modulus);
- void round_to_q(Register reg, int modulus);
-
- // allocation
- void eden_allocate(
- Register obj, // result: pointer to object after
- // successful allocation
- Register var_size_in_bytes, // object size in bytes if unknown at
- // compile time; invalid otherwise
- int con_size_in_bytes, // object size in bytes if known at
- // compile time
- Register t1, // temp register
- Label& slow_case // continuation point if fast
- // allocation fails
- );
- void tlab_allocate(
- Register obj, // result: pointer to object after
- // successful allocation
- Register var_size_in_bytes, // object size in bytes if unknown at
- // compile time; invalid otherwise
- int con_size_in_bytes, // object size in bytes if known at
- // compile time
- Register t1, // temp register
- Register t2, // temp register
- Label& slow_case // continuation point if fast
- // allocation fails
- );
- void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case);
-
- //----
-
- // Debugging
-
- // only if +VerifyOops
- void verify_oop(Register reg, const char* s = "broken oop");
- void verify_oop_addr(Address addr, const char * s = "broken oop addr");
-
- // if heap base register is used - reinit it with the correct value
- void reinit_heapbase();
-
- // only if +VerifyFPU
- void verify_FPU(int stack_depth, const char* s = "illegal FPU state") {}
-
- // prints msg, dumps registers and stops execution
- void stop(const char* msg);
-
- // prints message and continues
- void warn(const char* msg);
-
- static void debug(char* msg, int64_t pc, int64_t regs[]);
-
- void os_breakpoint();
-
- void untested()
- {
- stop("untested");
- }
-
- void unimplemented(const char* what = "")
- {
- char* b = new char[1024];
- sprintf(b, "unimplemented: %s", what);
- stop(b);
- }
-
- void should_not_reach_here()
- {
- stop("should not reach here");
- }
-
- // Stack overflow checking
- void bang_stack_with_offset(int offset)
- {
- // stack grows down, caller passes positive offset
- assert(offset > 0, "must bang with negative offset");
- movl(Address(rsp, (-offset)), rax);
- }
-
- // Writes to stack successive pages until offset reached to check for
- // stack overflow + shadow pages. Also, clobbers tmp
- void bang_stack_size(Register offset, Register tmp);
-
- // Support for serializing memory accesses between threads.
- void serialize_memory(Register thread, Register tmp);
-
- void verify_tlab();
-
- // Biased locking support
- // lock_reg and obj_reg must be loaded up with the appropriate values.
- // swap_reg must be rax and is killed.
- // tmp_reg must be supplied and is killed.
- // If swap_reg_contains_mark is true then the code assumes that the
- // mark word of the object has already been loaded into swap_reg.
- // Optional slow case is for implementations (interpreter and C1) which branch to
- // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
- // Returns offset of first potentially-faulting instruction for null
- // check info (currently consumed only by C1). If
- // swap_reg_contains_mark is true then returns -1 as it is assumed
- // the calling code has already passed any potential faults.
- int biased_locking_enter(Register lock_reg, Register obj_reg, Register swap_reg, Register tmp_reg,
- bool swap_reg_contains_mark,
- Label& done, Label* slow_case = NULL,
- BiasedLockingCounters* counters = NULL);
- void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
-
- Condition negate_condition(Condition cond);
-
- // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
- // operands. In general the names are modified to avoid hiding the instruction in Assembler
- // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
- // here in MacroAssembler. The major exception to this rule is call
-
- // Arithmetics
-
- void cmp8(AddressLiteral src1, int8_t imm32);
-
- void cmp32(AddressLiteral src1, int32_t src2);
- // compare reg - mem, or reg - &mem
- void cmp32(Register src1, AddressLiteral src2);
-
- void cmp32(Register src1, Address src2);
-
-#ifndef _LP64
- void cmpoop(Address dst, jobject obj);
- void cmpoop(Register dst, jobject obj);
-#endif // _LP64
-
- // NOTE src2 must be the lval. This is NOT an mem-mem compare
- void cmpptr(Address src1, AddressLiteral src2);
-
- void cmpptr(Register src1, AddressLiteral src);
-
- // will be cmpreg(?)
- void cmp64(Register src1, AddressLiteral src);
-
- void cmpxchgptr(Register reg, Address adr);
- void cmpxchgptr(Register reg, AddressLiteral adr);
-
- // Helper functions for statistics gathering.
- // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
- void cond_inc32(Condition cond, AddressLiteral counter_addr);
- // Unconditional atomic increment.
- void atomic_incl(AddressLiteral counter_addr);
-
-
- void lea(Register dst, AddressLiteral src);
- void lea(Register dst, Address src);
-
-
- // Calls
- void call(Label& L, relocInfo::relocType rtype);
- void call(Register entry);
- void call(AddressLiteral entry);
-
- // Jumps
-
- // 32bit can do a case table jump in one instruction but we no longer allow the base
- // to be installed in the Address class
- void jump(ArrayAddress entry);
-
- void jump(AddressLiteral entry);
- void jump_cc(Condition cc, AddressLiteral dst);
-
- // Floating
-
- void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
- void ldmxcsr(AddressLiteral src);
-
-private:
- // these are private because users should be doing movflt/movdbl
-
- void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
- void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
- void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
- void movss(XMMRegister dst, AddressLiteral src);
-
- void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
- void movlpd(XMMRegister dst, AddressLiteral src);
-
-public:
-
-
- void xorpd(XMMRegister dst, XMMRegister src) {Assembler::xorpd(dst, src); }
- void xorpd(XMMRegister dst, Address src) {Assembler::xorpd(dst, src); }
- void xorpd(XMMRegister dst, AddressLiteral src);
-
- void xorps(XMMRegister dst, XMMRegister src) {Assembler::xorps(dst, src); }
- void xorps(XMMRegister dst, Address src) {Assembler::xorps(dst, src); }
- void xorps(XMMRegister dst, AddressLiteral src);
-
-
- // Data
-
- void movoop(Register dst, jobject obj);
- void movoop(Address dst, jobject obj);
-
- void movptr(ArrayAddress dst, Register src);
- void movptr(Register dst, AddressLiteral src);
-
- void movptr(Register dst, intptr_t src);
- void movptr(Address dst, intptr_t src);
-
- void movptr(Register dst, ArrayAddress src);
-
- // to avoid hiding movl
- void mov32(AddressLiteral dst, Register src);
- void mov32(Register dst, AddressLiteral src);
-
- void pushoop(jobject obj);
-
- // Can push value or effective address
- void pushptr(AddressLiteral src);
-
-};
-
-/**
- * class SkipIfEqual:
- *
- * Instantiating this class will result in assembly code being output that will
- * jump around any code emitted between the creation of the instance and it's
- * automatic destruction at the end of a scope block, depending on the value of
- * the flag passed to the constructor, which will be checked at run-time.
- */
-class SkipIfEqual {
- private:
- MacroAssembler* _masm;
- Label _label;
-
- public:
- SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
- ~SkipIfEqual();
-};
-
-
-#ifdef ASSERT
-inline bool AbstractAssembler::pd_check_instruction_mark() { return true; }
-#endif
diff --git a/hotspot/src/cpu/x86/vm/c1_CodeStubs_x86.cpp b/hotspot/src/cpu/x86/vm/c1_CodeStubs_x86.cpp
index 09419c95650..283a63d8541 100644
--- a/hotspot/src/cpu/x86/vm/c1_CodeStubs_x86.cpp
+++ b/hotspot/src/cpu/x86/vm/c1_CodeStubs_x86.cpp
@@ -43,11 +43,12 @@ void ConversionStub::emit_code(LIR_Assembler* ce) {
__ comisd(input()->as_xmm_double_reg(),
ExternalAddress((address)&double_zero));
} else {
- __ pushl(rax);
+ LP64_ONLY(ShouldNotReachHere());
+ __ push(rax);
__ ftst();
__ fnstsw_ax();
__ sahf();
- __ popl(rax);
+ __ pop(rax);
}
Label NaN, do_return;
@@ -61,7 +62,7 @@ void ConversionStub::emit_code(LIR_Assembler* ce) {
// input is NaN -> return 0
__ bind(NaN);
- __ xorl(result()->as_register(), result()->as_register());
+ __ xorptr(result()->as_register(), result()->as_register());
__ bind(do_return);
__ jmp(_continuation);
@@ -139,7 +140,7 @@ NewInstanceStub::NewInstanceStub(LIR_Opr klass_reg, LIR_Opr result, ciInstanceKl
void NewInstanceStub::emit_code(LIR_Assembler* ce) {
assert(__ rsp_offset() == 0, "frame size should be fixed");
__ bind(_entry);
- __ movl(rdx, _klass_reg->as_register());
+ __ movptr(rdx, _klass_reg->as_register());
__ call(RuntimeAddress(Runtime1::entry_for(_stub_id)));
ce->add_call_info_here(_info);
ce->verify_oop_map(_info);
@@ -306,10 +307,10 @@ void PatchingStub::emit_code(LIR_Assembler* ce) {
assert(_obj != noreg, "must be a valid register");
Register tmp = rax;
if (_obj == tmp) tmp = rbx;
- __ pushl(tmp);
+ __ push(tmp);
__ get_thread(tmp);
- __ cmpl(tmp, Address(_obj, instanceKlass::init_thread_offset_in_bytes() + sizeof(klassOopDesc)));
- __ popl(tmp);
+ __ cmpptr(tmp, Address(_obj, instanceKlass::init_thread_offset_in_bytes() + sizeof(klassOopDesc)));
+ __ pop(tmp);
__ jcc(Assembler::notEqual, call_patch);
// access_field patches may execute the patched code before it's
@@ -434,7 +435,7 @@ void ArrayCopyStub::emit_code(LIR_Assembler* ce) {
VMReg r_1 = args[i].first();
if (r_1->is_stack()) {
int st_off = r_1->reg2stack() * wordSize;
- __ movl (Address(rsp, st_off), r[i]);
+ __ movptr (Address(rsp, st_off), r[i]);
} else {
assert(r[i] == args[i].first()->as_Register(), "Wrong register for arg ");
}
@@ -449,7 +450,7 @@ void ArrayCopyStub::emit_code(LIR_Assembler* ce) {
ce->add_call_info_here(info());
#ifndef PRODUCT
- __ increment(ExternalAddress((address)&Runtime1::_arraycopy_slowcase_cnt));
+ __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_slowcase_cnt));
#endif
__ jmp(_continuation);
diff --git a/hotspot/src/cpu/x86/vm/c1_Defs_x86.hpp b/hotspot/src/cpu/x86/vm/c1_Defs_x86.hpp
index 8594a834907..e8d3e8b6714 100644
--- a/hotspot/src/cpu/x86/vm/c1_Defs_x86.hpp
+++ b/hotspot/src/cpu/x86/vm/c1_Defs_x86.hpp
@@ -36,27 +36,34 @@ enum {
// registers
enum {
- pd_nof_cpu_regs_frame_map = 8, // number of registers used during code emission
- pd_nof_fpu_regs_frame_map = 8, // number of registers used during code emission
- pd_nof_xmm_regs_frame_map = 8, // number of registers used during code emission
- pd_nof_caller_save_cpu_regs_frame_map = 6, // number of registers killed by calls
- pd_nof_caller_save_fpu_regs_frame_map = 8, // number of registers killed by calls
- pd_nof_caller_save_xmm_regs_frame_map = 8, // number of registers killed by calls
+ pd_nof_cpu_regs_frame_map = RegisterImpl::number_of_registers, // number of registers used during code emission
+ pd_nof_fpu_regs_frame_map = FloatRegisterImpl::number_of_registers, // number of registers used during code emission
+ pd_nof_xmm_regs_frame_map = XMMRegisterImpl::number_of_registers, // number of registers used during code emission
- pd_nof_cpu_regs_reg_alloc = 6, // number of registers that are visible to register allocator
+#ifdef _LP64
+ #define UNALLOCATED 4 // rsp, rbp, r15, r10
+#else
+ #define UNALLOCATED 2 // rsp, rbp
+#endif // LP64
+
+ pd_nof_caller_save_cpu_regs_frame_map = pd_nof_cpu_regs_frame_map - UNALLOCATED, // number of registers killed by calls
+ pd_nof_caller_save_fpu_regs_frame_map = pd_nof_fpu_regs_frame_map, // number of registers killed by calls
+ pd_nof_caller_save_xmm_regs_frame_map = pd_nof_xmm_regs_frame_map, // number of registers killed by calls
+
+ pd_nof_cpu_regs_reg_alloc = pd_nof_caller_save_cpu_regs_frame_map, // number of registers that are visible to register allocator
pd_nof_fpu_regs_reg_alloc = 6, // number of registers that are visible to register allocator
- pd_nof_cpu_regs_linearscan = 8, // number of registers visible to linear scan
- pd_nof_fpu_regs_linearscan = 8, // number of registers visible to linear scan
- pd_nof_xmm_regs_linearscan = 8, // number of registers visible to linear scan
+ pd_nof_cpu_regs_linearscan = pd_nof_cpu_regs_frame_map, // number of registers visible to linear scan
+ pd_nof_fpu_regs_linearscan = pd_nof_fpu_regs_frame_map, // number of registers visible to linear scan
+ pd_nof_xmm_regs_linearscan = pd_nof_xmm_regs_frame_map, // number of registers visible to linear scan
pd_first_cpu_reg = 0,
- pd_last_cpu_reg = 5,
+ pd_last_cpu_reg = NOT_LP64(5) LP64_ONLY(11),
pd_first_byte_reg = 2,
pd_last_byte_reg = 5,
pd_first_fpu_reg = pd_nof_cpu_regs_frame_map,
pd_last_fpu_reg = pd_first_fpu_reg + 7,
pd_first_xmm_reg = pd_nof_cpu_regs_frame_map + pd_nof_fpu_regs_frame_map,
- pd_last_xmm_reg = pd_first_xmm_reg + 7
+ pd_last_xmm_reg = pd_first_xmm_reg + pd_nof_xmm_regs_frame_map - 1
};
diff --git a/hotspot/src/cpu/x86/vm/c1_FrameMap_x86.cpp b/hotspot/src/cpu/x86/vm/c1_FrameMap_x86.cpp
index 2118ec4483e..a48a8576fc9 100644
--- a/hotspot/src/cpu/x86/vm/c1_FrameMap_x86.cpp
+++ b/hotspot/src/cpu/x86/vm/c1_FrameMap_x86.cpp
@@ -39,10 +39,15 @@ LIR_Opr FrameMap::map_to_opr(BasicType type, VMRegPair* reg, bool) {
opr = LIR_OprFact::address(new LIR_Address(rsp_opr, st_off, type));
} else if (r_1->is_Register()) {
Register reg = r_1->as_Register();
- if (r_2->is_Register()) {
+ if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) {
Register reg2 = r_2->as_Register();
+#ifdef _LP64
+ assert(reg2 == reg, "must be same register");
+ opr = as_long_opr(reg);
+#else
opr = as_long_opr(reg2, reg);
- } else if (type == T_OBJECT) {
+#endif // _LP64
+ } else if (type == T_OBJECT || type == T_ARRAY) {
opr = as_oop_opr(reg);
} else {
opr = as_opr(reg);
@@ -88,18 +93,39 @@ LIR_Opr FrameMap::rax_oop_opr;
LIR_Opr FrameMap::rdx_oop_opr;
LIR_Opr FrameMap::rcx_oop_opr;
-LIR_Opr FrameMap::rax_rdx_long_opr;
-LIR_Opr FrameMap::rbx_rcx_long_opr;
+LIR_Opr FrameMap::long0_opr;
+LIR_Opr FrameMap::long1_opr;
LIR_Opr FrameMap::fpu0_float_opr;
LIR_Opr FrameMap::fpu0_double_opr;
LIR_Opr FrameMap::xmm0_float_opr;
LIR_Opr FrameMap::xmm0_double_opr;
+#ifdef _LP64
+
+LIR_Opr FrameMap::r8_opr;
+LIR_Opr FrameMap::r9_opr;
+LIR_Opr FrameMap::r10_opr;
+LIR_Opr FrameMap::r11_opr;
+LIR_Opr FrameMap::r12_opr;
+LIR_Opr FrameMap::r13_opr;
+LIR_Opr FrameMap::r14_opr;
+LIR_Opr FrameMap::r15_opr;
+
+// r10 and r15 can never contain oops since they aren't available to
+// the allocator
+LIR_Opr FrameMap::r8_oop_opr;
+LIR_Opr FrameMap::r9_oop_opr;
+LIR_Opr FrameMap::r11_oop_opr;
+LIR_Opr FrameMap::r12_oop_opr;
+LIR_Opr FrameMap::r13_oop_opr;
+LIR_Opr FrameMap::r14_oop_opr;
+#endif // _LP64
+
LIR_Opr FrameMap::_caller_save_cpu_regs[] = { 0, };
LIR_Opr FrameMap::_caller_save_fpu_regs[] = { 0, };
LIR_Opr FrameMap::_caller_save_xmm_regs[] = { 0, };
-XMMRegister FrameMap::_xmm_regs [8] = { 0, };
+XMMRegister FrameMap::_xmm_regs [] = { 0, };
XMMRegister FrameMap::nr2xmmreg(int rnr) {
assert(_init_done, "tables not initialized");
@@ -113,18 +139,39 @@ XMMRegister FrameMap::nr2xmmreg(int rnr) {
void FrameMap::init() {
if (_init_done) return;
- assert(nof_cpu_regs == 8, "wrong number of CPU registers");
- map_register(0, rsi); rsi_opr = LIR_OprFact::single_cpu(0); rsi_oop_opr = LIR_OprFact::single_cpu_oop(0);
- map_register(1, rdi); rdi_opr = LIR_OprFact::single_cpu(1); rdi_oop_opr = LIR_OprFact::single_cpu_oop(1);
- map_register(2, rbx); rbx_opr = LIR_OprFact::single_cpu(2); rbx_oop_opr = LIR_OprFact::single_cpu_oop(2);
- map_register(3, rax); rax_opr = LIR_OprFact::single_cpu(3); rax_oop_opr = LIR_OprFact::single_cpu_oop(3);
- map_register(4, rdx); rdx_opr = LIR_OprFact::single_cpu(4); rdx_oop_opr = LIR_OprFact::single_cpu_oop(4);
- map_register(5, rcx); rcx_opr = LIR_OprFact::single_cpu(5); rcx_oop_opr = LIR_OprFact::single_cpu_oop(5);
- map_register(6, rsp); rsp_opr = LIR_OprFact::single_cpu(6);
- map_register(7, rbp); rbp_opr = LIR_OprFact::single_cpu(7);
+ assert(nof_cpu_regs == LP64_ONLY(16) NOT_LP64(8), "wrong number of CPU registers");
+ map_register(0, rsi); rsi_opr = LIR_OprFact::single_cpu(0);
+ map_register(1, rdi); rdi_opr = LIR_OprFact::single_cpu(1);
+ map_register(2, rbx); rbx_opr = LIR_OprFact::single_cpu(2);
+ map_register(3, rax); rax_opr = LIR_OprFact::single_cpu(3);
+ map_register(4, rdx); rdx_opr = LIR_OprFact::single_cpu(4);
+ map_register(5, rcx); rcx_opr = LIR_OprFact::single_cpu(5);
- rax_rdx_long_opr = LIR_OprFact::double_cpu(3 /*eax*/, 4 /*edx*/);
- rbx_rcx_long_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 5 /*ecx*/);
+#ifndef _LP64
+ // The unallocatable registers are at the end
+ map_register(6, rsp);
+ map_register(7, rbp);
+#else
+ map_register( 6, r8); r8_opr = LIR_OprFact::single_cpu(6);
+ map_register( 7, r9); r9_opr = LIR_OprFact::single_cpu(7);
+ map_register( 8, r11); r11_opr = LIR_OprFact::single_cpu(8);
+ map_register( 9, r12); r12_opr = LIR_OprFact::single_cpu(9);
+ map_register(10, r13); r13_opr = LIR_OprFact::single_cpu(10);
+ map_register(11, r14); r14_opr = LIR_OprFact::single_cpu(11);
+ // The unallocatable registers are at the end
+ map_register(12, r10); r10_opr = LIR_OprFact::single_cpu(12);
+ map_register(13, r15); r15_opr = LIR_OprFact::single_cpu(13);
+ map_register(14, rsp);
+ map_register(15, rbp);
+#endif // _LP64
+
+#ifdef _LP64
+ long0_opr = LIR_OprFact::double_cpu(3 /*eax*/, 3 /*eax*/);
+ long1_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 2 /*ebx*/);
+#else
+ long0_opr = LIR_OprFact::double_cpu(3 /*eax*/, 4 /*edx*/);
+ long1_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 5 /*ecx*/);
+#endif // _LP64
fpu0_float_opr = LIR_OprFact::single_fpu(0);
fpu0_double_opr = LIR_OprFact::double_fpu(0);
xmm0_float_opr = LIR_OprFact::single_xmm(0);
@@ -137,6 +184,15 @@ void FrameMap::init() {
_caller_save_cpu_regs[4] = rdx_opr;
_caller_save_cpu_regs[5] = rcx_opr;
+#ifdef _LP64
+ _caller_save_cpu_regs[6] = r8_opr;
+ _caller_save_cpu_regs[7] = r9_opr;
+ _caller_save_cpu_regs[8] = r11_opr;
+ _caller_save_cpu_regs[9] = r12_opr;
+ _caller_save_cpu_regs[10] = r13_opr;
+ _caller_save_cpu_regs[11] = r14_opr;
+#endif // _LP64
+
_xmm_regs[0] = xmm0;
_xmm_regs[1] = xmm1;
@@ -147,18 +203,51 @@ void FrameMap::init() {
_xmm_regs[6] = xmm6;
_xmm_regs[7] = xmm7;
+#ifdef _LP64
+ _xmm_regs[8] = xmm8;
+ _xmm_regs[9] = xmm9;
+ _xmm_regs[10] = xmm10;
+ _xmm_regs[11] = xmm11;
+ _xmm_regs[12] = xmm12;
+ _xmm_regs[13] = xmm13;
+ _xmm_regs[14] = xmm14;
+ _xmm_regs[15] = xmm15;
+#endif // _LP64
+
for (int i = 0; i < 8; i++) {
_caller_save_fpu_regs[i] = LIR_OprFact::single_fpu(i);
+ }
+
+ for (int i = 0; i < nof_caller_save_xmm_regs ; i++) {
_caller_save_xmm_regs[i] = LIR_OprFact::single_xmm(i);
}
_init_done = true;
+ rsi_oop_opr = as_oop_opr(rsi);
+ rdi_oop_opr = as_oop_opr(rdi);
+ rbx_oop_opr = as_oop_opr(rbx);
+ rax_oop_opr = as_oop_opr(rax);
+ rdx_oop_opr = as_oop_opr(rdx);
+ rcx_oop_opr = as_oop_opr(rcx);
+
+ rsp_opr = as_pointer_opr(rsp);
+ rbp_opr = as_pointer_opr(rbp);
+
+#ifdef _LP64
+ r8_oop_opr = as_oop_opr(r8);
+ r9_oop_opr = as_oop_opr(r9);
+ r11_oop_opr = as_oop_opr(r11);
+ r12_oop_opr = as_oop_opr(r12);
+ r13_oop_opr = as_oop_opr(r13);
+ r14_oop_opr = as_oop_opr(r14);
+#endif // _LP64
+
VMRegPair regs;
BasicType sig_bt = T_OBJECT;
SharedRuntime::java_calling_convention(&sig_bt, ®s, 1, true);
receiver_opr = as_oop_opr(regs.first()->as_Register());
- assert(receiver_opr == rcx_oop_opr, "rcvr ought to be rcx");
+
}
diff --git a/hotspot/src/cpu/x86/vm/c1_FrameMap_x86.hpp b/hotspot/src/cpu/x86/vm/c1_FrameMap_x86.hpp
index 419b8600a3c..d5d9816b7b2 100644
--- a/hotspot/src/cpu/x86/vm/c1_FrameMap_x86.hpp
+++ b/hotspot/src/cpu/x86/vm/c1_FrameMap_x86.hpp
@@ -38,8 +38,13 @@
nof_xmm_regs = pd_nof_xmm_regs_frame_map,
nof_caller_save_xmm_regs = pd_nof_caller_save_xmm_regs_frame_map,
first_available_sp_in_frame = 0,
+#ifndef _LP64
frame_pad_in_bytes = 8,
nof_reg_args = 2
+#else
+ frame_pad_in_bytes = 16,
+ nof_reg_args = 6
+#endif // _LP64
};
private:
@@ -65,17 +70,49 @@
static LIR_Opr rax_oop_opr;
static LIR_Opr rdx_oop_opr;
static LIR_Opr rcx_oop_opr;
+#ifdef _LP64
- static LIR_Opr rax_rdx_long_opr;
- static LIR_Opr rbx_rcx_long_opr;
+ static LIR_Opr r8_opr;
+ static LIR_Opr r9_opr;
+ static LIR_Opr r10_opr;
+ static LIR_Opr r11_opr;
+ static LIR_Opr r12_opr;
+ static LIR_Opr r13_opr;
+ static LIR_Opr r14_opr;
+ static LIR_Opr r15_opr;
+
+ static LIR_Opr r8_oop_opr;
+ static LIR_Opr r9_oop_opr;
+
+ static LIR_Opr r11_oop_opr;
+ static LIR_Opr r12_oop_opr;
+ static LIR_Opr r13_oop_opr;
+ static LIR_Opr r14_oop_opr;
+
+#endif // _LP64
+
+ static LIR_Opr long0_opr;
+ static LIR_Opr long1_opr;
static LIR_Opr fpu0_float_opr;
static LIR_Opr fpu0_double_opr;
static LIR_Opr xmm0_float_opr;
static LIR_Opr xmm0_double_opr;
+#ifdef _LP64
+ static LIR_Opr as_long_opr(Register r) {
+ return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r));
+ }
+ static LIR_Opr as_pointer_opr(Register r) {
+ return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r));
+ }
+#else
static LIR_Opr as_long_opr(Register r, Register r2) {
return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r2));
}
+ static LIR_Opr as_pointer_opr(Register r) {
+ return LIR_OprFact::single_cpu(cpu_reg2rnr(r));
+ }
+#endif // _LP64
// VMReg name for spilled physical FPU stack slot n
static VMReg fpu_regname (int n);
diff --git a/hotspot/src/cpu/x86/vm/c1_LIRAssembler_x86.cpp b/hotspot/src/cpu/x86/vm/c1_LIRAssembler_x86.cpp
index 081f38c3bac..c267d0e6ac7 100644
--- a/hotspot/src/cpu/x86/vm/c1_LIRAssembler_x86.cpp
+++ b/hotspot/src/cpu/x86/vm/c1_LIRAssembler_x86.cpp
@@ -113,7 +113,7 @@ bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
LIR_Opr LIR_Assembler::receiverOpr() {
- return FrameMap::rcx_oop_opr;
+ return FrameMap::receiver_opr;
}
LIR_Opr LIR_Assembler::incomingReceiverOpr() {
@@ -121,7 +121,7 @@ LIR_Opr LIR_Assembler::incomingReceiverOpr() {
}
LIR_Opr LIR_Assembler::osrBufferPointer() {
- return FrameMap::rcx_opr;
+ return FrameMap::as_pointer_opr(receiverOpr()->as_register());
}
//--------------fpu register translations-----------------------
@@ -181,7 +181,7 @@ void LIR_Assembler::push(LIR_Opr opr) {
if (opr->is_single_cpu()) {
__ push_reg(opr->as_register());
} else if (opr->is_double_cpu()) {
- __ push_reg(opr->as_register_hi());
+ NOT_LP64(__ push_reg(opr->as_register_hi()));
__ push_reg(opr->as_register_lo());
} else if (opr->is_stack()) {
__ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
@@ -202,31 +202,45 @@ void LIR_Assembler::push(LIR_Opr opr) {
void LIR_Assembler::pop(LIR_Opr opr) {
if (opr->is_single_cpu()) {
- __ pop(opr->as_register());
+ __ pop_reg(opr->as_register());
} else {
ShouldNotReachHere();
}
}
+bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
+ return addr->base()->is_illegal() && addr->index()->is_illegal();
+}
+
//-------------------------------------------
+
Address LIR_Assembler::as_Address(LIR_Address* addr) {
+ return as_Address(addr, rscratch1);
+}
+
+Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
if (addr->base()->is_illegal()) {
assert(addr->index()->is_illegal(), "must be illegal too");
- //return Address(addr->disp(), relocInfo::none);
- // hack for now since this should really return an AddressLiteral
- // which will have to await 64bit c1 changes.
- return Address(noreg, addr->disp());
+ AddressLiteral laddr((address)addr->disp(), relocInfo::none);
+ if (! __ reachable(laddr)) {
+ __ movptr(tmp, laddr.addr());
+ Address res(tmp, 0);
+ return res;
+ } else {
+ return __ as_Address(laddr);
+ }
}
- Register base = addr->base()->as_register();
+ Register base = addr->base()->as_pointer_register();
if (addr->index()->is_illegal()) {
return Address( base, addr->disp());
- } else if (addr->index()->is_single_cpu()) {
- Register index = addr->index()->as_register();
+ } else if (addr->index()->is_cpu_register()) {
+ Register index = addr->index()->as_pointer_register();
return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
} else if (addr->index()->is_constant()) {
- int addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
+ intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
+ assert(Assembler::is_simm32(addr_offset), "must be");
return Address(base, addr_offset);
} else {
@@ -284,7 +298,7 @@ void LIR_Assembler::osr_entry() {
// All other registers are dead at this point and the locals will be
// copied into place by code emitted in the IR.
- Register OSR_buf = osrBufferPointer()->as_register();
+ Register OSR_buf = osrBufferPointer()->as_pointer_register();
{ assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
int monitor_offset = BytesPerWord * method()->max_locals() +
(BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1);
@@ -294,16 +308,16 @@ void LIR_Assembler::osr_entry() {
// verify the interpreter's monitor has a non-null object
{
Label L;
- __ cmpl(Address(OSR_buf, slot_offset + BasicObjectLock::obj_offset_in_bytes()), NULL_WORD);
+ __ cmpptr(Address(OSR_buf, slot_offset + BasicObjectLock::obj_offset_in_bytes()), (int32_t)NULL_WORD);
__ jcc(Assembler::notZero, L);
__ stop("locked object is NULL");
__ bind(L);
}
#endif
- __ movl(rbx, Address(OSR_buf, slot_offset + BasicObjectLock::lock_offset_in_bytes()));
- __ movl(frame_map()->address_for_monitor_lock(i), rbx);
- __ movl(rbx, Address(OSR_buf, slot_offset + BasicObjectLock::obj_offset_in_bytes()));
- __ movl(frame_map()->address_for_monitor_object(i), rbx);
+ __ movptr(rbx, Address(OSR_buf, slot_offset + BasicObjectLock::lock_offset_in_bytes()));
+ __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
+ __ movptr(rbx, Address(OSR_buf, slot_offset + BasicObjectLock::obj_offset_in_bytes()));
+ __ movptr(frame_map()->address_for_monitor_object(i), rbx);
}
}
}
@@ -313,10 +327,11 @@ void LIR_Assembler::osr_entry() {
int LIR_Assembler::check_icache() {
Register receiver = FrameMap::receiver_opr->as_register();
Register ic_klass = IC_Klass;
+ const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
if (!VerifyOops) {
// insert some nops so that the verified entry point is aligned on CodeEntryAlignment
- while ((__ offset() + 9) % CodeEntryAlignment != 0) {
+ while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) {
__ nop();
}
}
@@ -347,7 +362,7 @@ void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register new_
// and cannot block => no GC can happen
// The slow case (MonitorAccessStub) uses the first two stack slots
// ([esp+0] and [esp+4]), therefore we store the exception at [esp+8]
- __ movl (Address(rsp, 2*wordSize), exception);
+ __ movptr (Address(rsp, 2*wordSize), exception);
}
Register obj_reg = obj_opr->as_register();
@@ -360,7 +375,7 @@ void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register new_
lock_reg = new_hdr;
// compute pointer to BasicLock
Address lock_addr = frame_map()->address_for_monitor_lock(monitor_no);
- __ leal(lock_reg, lock_addr);
+ __ lea(lock_reg, lock_addr);
// unlock object
MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, true, monitor_no);
// _slow_case_stubs->append(slow_case);
@@ -385,14 +400,18 @@ void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register new_
if (exception->is_valid()) {
// restore exception
- __ movl (exception, Address(rsp, 2 * wordSize));
+ __ movptr (exception, Address(rsp, 2 * wordSize));
}
}
// This specifies the rsp decrement needed to build the frame
int LIR_Assembler::initial_frame_size_in_bytes() {
// if rounding, must let FrameMap know!
- return (frame_map()->framesize() - 2) * BytesPerWord; // subtract two words to account for return address and link
+
+ // The frame_map records size in slots (32bit word)
+
+ // subtract two words to account for return address and link
+ return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
}
@@ -495,43 +514,43 @@ void LIR_Assembler::emit_deopt_handler() {
// This is the fast version of java.lang.String.compare; it has not
// OSR-entry and therefore, we generate a slow version for OSR's
void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) {
- __ movl (rbx, rcx); // receiver is in rcx
- __ movl (rax, arg1->as_register());
+ __ movptr (rbx, rcx); // receiver is in rcx
+ __ movptr (rax, arg1->as_register());
// Get addresses of first characters from both Strings
- __ movl (rsi, Address(rax, java_lang_String::value_offset_in_bytes()));
- __ movl (rcx, Address(rax, java_lang_String::offset_offset_in_bytes()));
- __ leal (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
+ __ movptr (rsi, Address(rax, java_lang_String::value_offset_in_bytes()));
+ __ movptr (rcx, Address(rax, java_lang_String::offset_offset_in_bytes()));
+ __ lea (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
// rbx, may be NULL
add_debug_info_for_null_check_here(info);
- __ movl (rdi, Address(rbx, java_lang_String::value_offset_in_bytes()));
- __ movl (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes()));
- __ leal (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
+ __ movptr (rdi, Address(rbx, java_lang_String::value_offset_in_bytes()));
+ __ movptr (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes()));
+ __ lea (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
// compute minimum length (in rax) and difference of lengths (on top of stack)
if (VM_Version::supports_cmov()) {
- __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes()));
- __ movl (rax, Address(rax, java_lang_String::count_offset_in_bytes()));
- __ movl (rcx, rbx);
- __ subl (rbx, rax); // subtract lengths
- __ pushl(rbx); // result
- __ cmovl(Assembler::lessEqual, rax, rcx);
+ __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes()));
+ __ movl (rax, Address(rax, java_lang_String::count_offset_in_bytes()));
+ __ mov (rcx, rbx);
+ __ subptr (rbx, rax); // subtract lengths
+ __ push (rbx); // result
+ __ cmov (Assembler::lessEqual, rax, rcx);
} else {
Label L;
- __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes()));
- __ movl (rcx, Address(rax, java_lang_String::count_offset_in_bytes()));
- __ movl (rax, rbx);
- __ subl (rbx, rcx);
- __ pushl(rbx);
- __ jcc (Assembler::lessEqual, L);
- __ movl (rax, rcx);
+ __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes()));
+ __ movl (rcx, Address(rax, java_lang_String::count_offset_in_bytes()));
+ __ mov (rax, rbx);
+ __ subptr (rbx, rcx);
+ __ push (rbx);
+ __ jcc (Assembler::lessEqual, L);
+ __ mov (rax, rcx);
__ bind (L);
}
// is minimum length 0?
Label noLoop, haveResult;
- __ testl (rax, rax);
+ __ testptr (rax, rax);
__ jcc (Assembler::zero, noLoop);
// compare first characters
@@ -546,9 +565,9 @@ void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst,
// set rsi.edi to the end of the arrays (arrays have same length)
// negate the index
- __ leal(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR)));
- __ leal(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR)));
- __ negl(rax);
+ __ lea(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR)));
+ __ lea(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR)));
+ __ negptr(rax);
// compare the strings in a loop
@@ -565,12 +584,12 @@ void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst,
// strings are equal up to min length
__ bind(noLoop);
- __ popl(rax);
+ __ pop(rax);
return_op(LIR_OprFact::illegalOpr);
__ bind(haveResult);
// leave instruction is going to discard the TOS value
- __ movl (rax, rcx); // result of call is in rax,
+ __ mov (rax, rcx); // result of call is in rax,
}
@@ -589,6 +608,11 @@ void LIR_Assembler::return_op(LIR_Opr result) {
// the poll sets the condition code, but no data registers
AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()),
relocInfo::poll_return_type);
+
+ // NOTE: the requires that the polling page be reachable else the reloc
+ // goes to the movq that loads the address and not the faulting instruction
+ // which breaks the signal handler code
+
__ test32(rax, polling_page);
__ ret(0);
@@ -606,17 +630,22 @@ int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
}
int offset = __ offset();
+
+ // NOTE: the requires that the polling page be reachable else the reloc
+ // goes to the movq that loads the address and not the faulting instruction
+ // which breaks the signal handler code
+
__ test32(rax, polling_page);
return offset;
}
void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
- if (from_reg != to_reg) __ movl(to_reg, from_reg);
+ if (from_reg != to_reg) __ mov(to_reg, from_reg);
}
void LIR_Assembler::swap_reg(Register a, Register b) {
- __ xchgl(a, b);
+ __ xchgptr(a, b);
}
@@ -634,8 +663,12 @@ void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_cod
case T_LONG: {
assert(patch_code == lir_patch_none, "no patching handled here");
- __ movl(dest->as_register_lo(), c->as_jint_lo());
- __ movl(dest->as_register_hi(), c->as_jint_hi());
+#ifdef _LP64
+ __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
+#else
+ __ movptr(dest->as_register_lo(), c->as_jint_lo());
+ __ movptr(dest->as_register_hi(), c->as_jint_hi());
+#endif // _LP64
break;
}
@@ -714,10 +747,15 @@ void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
case T_LONG: // fall through
case T_DOUBLE:
- __ movl(frame_map()->address_for_slot(dest->double_stack_ix(),
- lo_word_offset_in_bytes), c->as_jint_lo_bits());
- __ movl(frame_map()->address_for_slot(dest->double_stack_ix(),
- hi_word_offset_in_bytes), c->as_jint_hi_bits());
+#ifdef _LP64
+ __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
+ lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits());
+#else
+ __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
+ lo_word_offset_in_bytes), c->as_jint_lo_bits());
+ __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
+ hi_word_offset_in_bytes), c->as_jint_hi_bits());
+#endif // _LP64
break;
default:
@@ -731,7 +769,7 @@ void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmi
LIR_Const* c = src->as_constant_ptr();
LIR_Address* addr = dest->as_address_ptr();
- if (info != NULL) add_debug_info_for_null_check_here(info);
+ int null_check_here = code_offset();
switch (type) {
case T_INT: // fall through
case T_FLOAT:
@@ -741,16 +779,33 @@ void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmi
case T_OBJECT: // fall through
case T_ARRAY:
if (c->as_jobject() == NULL) {
- __ movl(as_Address(addr), NULL_WORD);
+ __ movptr(as_Address(addr), (int32_t)NULL_WORD);
} else {
- __ movoop(as_Address(addr), c->as_jobject());
+ if (is_literal_address(addr)) {
+ ShouldNotReachHere();
+ __ movoop(as_Address(addr, noreg), c->as_jobject());
+ } else {
+ __ movoop(as_Address(addr), c->as_jobject());
+ }
}
break;
case T_LONG: // fall through
case T_DOUBLE:
- __ movl(as_Address_hi(addr), c->as_jint_hi_bits());
- __ movl(as_Address_lo(addr), c->as_jint_lo_bits());
+#ifdef _LP64
+ if (is_literal_address(addr)) {
+ ShouldNotReachHere();
+ __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
+ } else {
+ __ movptr(r10, (intptr_t)c->as_jlong_bits());
+ null_check_here = code_offset();
+ __ movptr(as_Address_lo(addr), r10);
+ }
+#else
+ // Always reachable in 32bit so this doesn't produce useless move literal
+ __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
+ __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
+#endif // _LP64
break;
case T_BOOLEAN: // fall through
@@ -766,6 +821,10 @@ void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmi
default:
ShouldNotReachHere();
};
+
+ if (info != NULL) {
+ add_debug_info_for_null_check(null_check_here, info);
+ }
}
@@ -775,6 +834,13 @@ void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
// move between cpu-registers
if (dest->is_single_cpu()) {
+#ifdef _LP64
+ if (src->type() == T_LONG) {
+ // Can do LONG -> OBJECT
+ move_regs(src->as_register_lo(), dest->as_register());
+ return;
+ }
+#endif
assert(src->is_single_cpu(), "must match");
if (src->type() == T_OBJECT) {
__ verify_oop(src->as_register());
@@ -782,13 +848,27 @@ void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
move_regs(src->as_register(), dest->as_register());
} else if (dest->is_double_cpu()) {
+#ifdef _LP64
+ if (src->type() == T_OBJECT || src->type() == T_ARRAY) {
+ // Surprising to me but we can see move of a long to t_object
+ __ verify_oop(src->as_register());
+ move_regs(src->as_register(), dest->as_register_lo());
+ return;
+ }
+#endif
assert(src->is_double_cpu(), "must match");
Register f_lo = src->as_register_lo();
Register f_hi = src->as_register_hi();
Register t_lo = dest->as_register_lo();
Register t_hi = dest->as_register_hi();
+#ifdef _LP64
+ assert(f_hi == f_lo, "must be same");
+ assert(t_hi == t_lo, "must be same");
+ move_regs(f_lo, t_lo);
+#else
assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
+
if (f_lo == t_hi && f_hi == t_lo) {
swap_reg(f_lo, f_hi);
} else if (f_hi == t_lo) {
@@ -800,6 +880,7 @@ void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
move_regs(f_lo, t_lo);
move_regs(f_hi, t_hi);
}
+#endif // LP64
// special moves from fpu-register to xmm-register
// necessary for method results
@@ -841,14 +922,16 @@ void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool po
Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
if (type == T_OBJECT || type == T_ARRAY) {
__ verify_oop(src->as_register());
+ __ movptr (dst, src->as_register());
+ } else {
+ __ movl (dst, src->as_register());
}
- __ movl (dst, src->as_register());
} else if (src->is_double_cpu()) {
Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
- __ movl (dstLO, src->as_register_lo());
- __ movl (dstHI, src->as_register_hi());
+ __ movptr (dstLO, src->as_register_lo());
+ NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
} else if (src->is_single_xmm()) {
Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
@@ -885,6 +968,8 @@ void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_Patch
}
if (patch_code != lir_patch_none) {
patch = new PatchingStub(_masm, PatchingStub::access_field_id);
+ Address toa = as_Address(to_addr);
+ assert(toa.disp() != 0, "must have");
}
if (info != NULL) {
add_debug_info_for_null_check_here(info);
@@ -918,6 +1003,10 @@ void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_Patch
case T_ADDRESS: // fall through
case T_ARRAY: // fall through
case T_OBJECT: // fall through
+#ifdef _LP64
+ __ movptr(as_Address(to_addr), src->as_register());
+ break;
+#endif // _LP64
case T_INT:
__ movl(as_Address(to_addr), src->as_register());
break;
@@ -925,6 +1014,9 @@ void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_Patch
case T_LONG: {
Register from_lo = src->as_register_lo();
Register from_hi = src->as_register_hi();
+#ifdef _LP64
+ __ movptr(as_Address_lo(to_addr), from_lo);
+#else
Register base = to_addr->base()->as_register();
Register index = noreg;
if (to_addr->index()->is_register()) {
@@ -950,6 +1042,7 @@ void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_Patch
}
__ movl(as_Address_hi(to_addr), from_hi);
}
+#endif // _LP64
break;
}
@@ -982,16 +1075,18 @@ void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
assert(dest->is_register(), "should not call otherwise");
if (dest->is_single_cpu()) {
- __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
if (type == T_ARRAY || type == T_OBJECT) {
+ __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
__ verify_oop(dest->as_register());
+ } else {
+ __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
}
} else if (dest->is_double_cpu()) {
Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
- __ movl(dest->as_register_hi(), src_addr_HI);
- __ movl(dest->as_register_lo(), src_addr_LO);
+ __ movptr(dest->as_register_lo(), src_addr_LO);
+ NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
} else if (dest->is_single_xmm()) {
Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
@@ -1019,15 +1114,25 @@ void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
if (src->is_single_stack()) {
- __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
- __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
+ if (type == T_OBJECT || type == T_ARRAY) {
+ __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
+ __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
+ } else {
+ __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
+ __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
+ }
} else if (src->is_double_stack()) {
+#ifdef _LP64
+ __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
+ __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
+#else
__ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
- // push and pop the part at src + 4, adding 4 for the previous push
- __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 4 + 4));
- __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 4 + 4));
+ // push and pop the part at src + wordSize, adding wordSize for the previous push
+ __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), wordSize));
+ __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), wordSize));
__ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
+#endif // _LP64
} else {
ShouldNotReachHere();
@@ -1052,7 +1157,7 @@ void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_Patch
// so blow away the value of to_rinfo before loading a
// partial word into it. Do it here so that it precedes
// the potential patch point below.
- __ xorl(dest->as_register(), dest->as_register());
+ __ xorptr(dest->as_register(), dest->as_register());
}
break;
}
@@ -1060,6 +1165,7 @@ void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_Patch
PatchingStub* patch = NULL;
if (patch_code != lir_patch_none) {
patch = new PatchingStub(_masm, PatchingStub::access_field_id);
+ assert(from_addr.disp() != 0, "must have");
}
if (info != NULL) {
add_debug_info_for_null_check_here(info);
@@ -1091,13 +1197,21 @@ void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_Patch
case T_ADDRESS: // fall through
case T_OBJECT: // fall through
case T_ARRAY: // fall through
+#ifdef _LP64
+ __ movptr(dest->as_register(), from_addr);
+ break;
+#endif // _L64
case T_INT:
- __ movl(dest->as_register(), from_addr);
+ // %%% could this be a movl? this is safer but longer instruction
+ __ movl2ptr(dest->as_register(), from_addr);
break;
case T_LONG: {
Register to_lo = dest->as_register_lo();
Register to_hi = dest->as_register_hi();
+#ifdef _LP64
+ __ movptr(to_lo, as_Address_lo(addr));
+#else
Register base = addr->base()->as_register();
Register index = noreg;
if (addr->index()->is_register()) {
@@ -1109,7 +1223,7 @@ void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_Patch
// array access so this code will never have to deal with
// patches or null checks.
assert(info == NULL && patch == NULL, "must be");
- __ leal(to_hi, as_Address(addr));
+ __ lea(to_hi, as_Address(addr));
__ movl(to_lo, Address(to_hi, 0));
__ movl(to_hi, Address(to_hi, BytesPerWord));
} else if (base == to_lo || index == to_lo) {
@@ -1132,6 +1246,7 @@ void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_Patch
}
__ movl(to_hi, as_Address_hi(addr));
}
+#endif // _LP64
break;
}
@@ -1140,12 +1255,13 @@ void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_Patch
Register dest_reg = dest->as_register();
assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
- __ movsxb(dest_reg, from_addr);
+ __ movsbl(dest_reg, from_addr);
} else {
__ movb(dest_reg, from_addr);
__ shll(dest_reg, 24);
__ sarl(dest_reg, 24);
}
+ // These are unsigned so the zero extension on 64bit is just what we need
break;
}
@@ -1153,22 +1269,26 @@ void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_Patch
Register dest_reg = dest->as_register();
assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
- __ movzxw(dest_reg, from_addr);
+ __ movzwl(dest_reg, from_addr);
} else {
__ movw(dest_reg, from_addr);
}
+ // This is unsigned so the zero extension on 64bit is just what we need
+ // __ movl2ptr(dest_reg, dest_reg);
break;
}
case T_SHORT: {
Register dest_reg = dest->as_register();
if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
- __ movsxw(dest_reg, from_addr);
+ __ movswl(dest_reg, from_addr);
} else {
__ movw(dest_reg, from_addr);
__ shll(dest_reg, 16);
__ sarl(dest_reg, 16);
}
+ // Might not be needed in 64bit but certainly doesn't hurt (except for code size)
+ __ movl2ptr(dest_reg, dest_reg);
break;
}
@@ -1306,9 +1426,13 @@ void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
switch (op->bytecode()) {
case Bytecodes::_i2l:
+#ifdef _LP64
+ __ movl2ptr(dest->as_register_lo(), src->as_register());
+#else
move_regs(src->as_register(), dest->as_register_lo());
move_regs(src->as_register(), dest->as_register_hi());
__ sarl(dest->as_register_hi(), 31);
+#endif // LP64
break;
case Bytecodes::_l2i:
@@ -1346,9 +1470,9 @@ void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
case Bytecodes::_i2f:
case Bytecodes::_i2d:
if (dest->is_single_xmm()) {
- __ cvtsi2ss(dest->as_xmm_float_reg(), src->as_register());
+ __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
} else if (dest->is_double_xmm()) {
- __ cvtsi2sd(dest->as_xmm_double_reg(), src->as_register());
+ __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
} else {
assert(dest->fpu() == 0, "result must be on TOS");
__ movl(Address(rsp, 0), src->as_register());
@@ -1359,9 +1483,9 @@ void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
case Bytecodes::_f2i:
case Bytecodes::_d2i:
if (src->is_single_xmm()) {
- __ cvttss2si(dest->as_register(), src->as_xmm_float_reg());
+ __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
} else if (src->is_double_xmm()) {
- __ cvttsd2si(dest->as_register(), src->as_xmm_double_reg());
+ __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
} else {
assert(src->fpu() == 0, "input must be on TOS");
__ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
@@ -1382,8 +1506,8 @@ void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
assert(dest->fpu() == 0, "result must be on TOS");
- __ movl(Address(rsp, 0), src->as_register_lo());
- __ movl(Address(rsp, BytesPerWord), src->as_register_hi());
+ __ movptr(Address(rsp, 0), src->as_register_lo());
+ NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi()));
__ fild_d(Address(rsp, 0));
// float result is rounded later through spilling
break;
@@ -1392,7 +1516,7 @@ void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
case Bytecodes::_d2l:
assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
assert(src->fpu() == 0, "input must be on TOS");
- assert(dest == FrameMap::rax_rdx_long_opr, "runtime stub places result in these registers");
+ assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
// instruction sequence too long to inline it here
{
@@ -1439,7 +1563,7 @@ void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
} else if (len == tmp3) {
// everything is ok
} else {
- __ movl(tmp3, len);
+ __ mov(tmp3, len);
}
__ allocate_array(op->obj()->as_register(),
len,
@@ -1466,31 +1590,32 @@ void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
CodeStub* stub = op->stub();
Label done;
- __ cmpl(value, 0);
+ __ cmpptr(value, (int32_t)NULL_WORD);
__ jcc(Assembler::equal, done);
add_debug_info_for_null_check_here(op->info_for_exception());
- __ movl(k_RInfo, Address(array, oopDesc::klass_offset_in_bytes()));
- __ movl(klass_RInfo, Address(value, oopDesc::klass_offset_in_bytes()));
+ __ movptr(k_RInfo, Address(array, oopDesc::klass_offset_in_bytes()));
+ __ movptr(klass_RInfo, Address(value, oopDesc::klass_offset_in_bytes()));
// get instance klass
- __ movl(k_RInfo, Address(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc)));
+ __ movptr(k_RInfo, Address(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc)));
// get super_check_offset
__ movl(Rtmp1, Address(k_RInfo, sizeof(oopDesc) + Klass::super_check_offset_offset_in_bytes()));
// See if we get an immediate positive hit
- __ cmpl(k_RInfo, Address(klass_RInfo, Rtmp1, Address::times_1));
+ __ cmpptr(k_RInfo, Address(klass_RInfo, Rtmp1, Address::times_1));
__ jcc(Assembler::equal, done);
// check for immediate negative hit
__ cmpl(Rtmp1, sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes());
__ jcc(Assembler::notEqual, *stub->entry());
// check for self
- __ cmpl(klass_RInfo, k_RInfo);
+ __ cmpptr(klass_RInfo, k_RInfo);
__ jcc(Assembler::equal, done);
- __ pushl(klass_RInfo);
- __ pushl(k_RInfo);
+ __ push(klass_RInfo);
+ __ push(k_RInfo);
__ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
- __ popl(klass_RInfo);
- __ popl(k_RInfo);
+ __ pop(klass_RInfo);
+ __ pop(k_RInfo);
+ // result is a boolean
__ cmpl(k_RInfo, 0);
__ jcc(Assembler::equal, *stub->entry());
__ bind(done);
@@ -1521,10 +1646,14 @@ void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
if (!k->is_loaded()) {
jobject2reg_with_patching(k_RInfo, op->info_for_patch());
} else {
+#ifdef _LP64
+ __ movoop(k_RInfo, k->encoding());
+#else
k_RInfo = noreg;
+#endif // _LP64
}
assert(obj != k_RInfo, "must be different");
- __ cmpl(obj, 0);
+ __ cmpptr(obj, (int32_t)NULL_WORD);
if (op->profiled_method() != NULL) {
ciMethod* method = op->profiled_method();
int bci = op->profiled_bci();
@@ -1556,9 +1685,13 @@ void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
// get object classo
// not a safepoint as obj null check happens earlier
if (k->is_loaded()) {
+#ifdef _LP64
+ __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
+#else
__ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->encoding());
+#endif // _LP64
} else {
- __ cmpl(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
+ __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
}
__ jcc(Assembler::notEqual, *stub->entry());
@@ -1566,24 +1699,37 @@ void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
} else {
// get object class
// not a safepoint as obj null check happens earlier
- __ movl(klass_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
+ __ movptr(klass_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
if (k->is_loaded()) {
// See if we get an immediate positive hit
+#ifdef _LP64
+ __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
+#else
__ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->encoding());
+#endif // _LP64
if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() != k->super_check_offset()) {
__ jcc(Assembler::notEqual, *stub->entry());
} else {
// See if we get an immediate positive hit
__ jcc(Assembler::equal, done);
// check for self
+#ifdef _LP64
+ __ cmpptr(klass_RInfo, k_RInfo);
+#else
__ cmpoop(klass_RInfo, k->encoding());
+#endif // _LP64
__ jcc(Assembler::equal, done);
- __ pushl(klass_RInfo);
+ __ push(klass_RInfo);
+#ifdef _LP64
+ __ push(k_RInfo);
+#else
__ pushoop(k->encoding());
+#endif // _LP64
__ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
- __ popl(klass_RInfo);
- __ popl(klass_RInfo);
+ __ pop(klass_RInfo);
+ __ pop(klass_RInfo);
+ // result is a boolean
__ cmpl(klass_RInfo, 0);
__ jcc(Assembler::equal, *stub->entry());
}
@@ -1591,20 +1737,21 @@ void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
} else {
__ movl(Rtmp1, Address(k_RInfo, sizeof(oopDesc) + Klass::super_check_offset_offset_in_bytes()));
// See if we get an immediate positive hit
- __ cmpl(k_RInfo, Address(klass_RInfo, Rtmp1, Address::times_1));
+ __ cmpptr(k_RInfo, Address(klass_RInfo, Rtmp1, Address::times_1));
__ jcc(Assembler::equal, done);
// check for immediate negative hit
__ cmpl(Rtmp1, sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes());
__ jcc(Assembler::notEqual, *stub->entry());
// check for self
- __ cmpl(klass_RInfo, k_RInfo);
+ __ cmpptr(klass_RInfo, k_RInfo);
__ jcc(Assembler::equal, done);
- __ pushl(klass_RInfo);
- __ pushl(k_RInfo);
+ __ push(klass_RInfo);
+ __ push(k_RInfo);
__ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
- __ popl(klass_RInfo);
- __ popl(k_RInfo);
+ __ pop(klass_RInfo);
+ __ pop(k_RInfo);
+ // result is a boolean
__ cmpl(k_RInfo, 0);
__ jcc(Assembler::equal, *stub->entry());
__ bind(done);
@@ -1612,7 +1759,7 @@ void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
}
if (dst != obj) {
- __ movl(dst, obj);
+ __ mov(dst, obj);
}
} else if (code == lir_instanceof) {
Register obj = op->object()->as_register();
@@ -1632,29 +1779,33 @@ void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
// so let's do it before loading the class
if (!k->is_loaded()) {
jobject2reg_with_patching(k_RInfo, op->info_for_patch());
+ } else {
+ LP64_ONLY(__ movoop(k_RInfo, k->encoding()));
}
assert(obj != k_RInfo, "must be different");
__ verify_oop(obj);
if (op->fast_check()) {
- __ cmpl(obj, 0);
+ __ cmpptr(obj, (int32_t)NULL_WORD);
__ jcc(Assembler::equal, zero);
// get object class
// not a safepoint as obj null check happens earlier
- if (k->is_loaded()) {
- __ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->encoding());
+ if (LP64_ONLY(false &&) k->is_loaded()) {
+ NOT_LP64(__ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->encoding()));
k_RInfo = noreg;
} else {
- __ cmpl(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
+ __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
}
__ jcc(Assembler::equal, one);
} else {
// get object class
// not a safepoint as obj null check happens earlier
- __ cmpl(obj, 0);
+ __ cmpptr(obj, (int32_t)NULL_WORD);
__ jcc(Assembler::equal, zero);
- __ movl(klass_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
+ __ movptr(klass_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
+
+#ifndef _LP64
if (k->is_loaded()) {
// See if we get an immediate positive hit
__ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->encoding());
@@ -1663,40 +1814,43 @@ void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
// check for self
__ cmpoop(klass_RInfo, k->encoding());
__ jcc(Assembler::equal, one);
- __ pushl(klass_RInfo);
+ __ push(klass_RInfo);
__ pushoop(k->encoding());
__ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
- __ popl(klass_RInfo);
- __ popl(dst);
+ __ pop(klass_RInfo);
+ __ pop(dst);
__ jmp(done);
}
} else {
+#else
+ { // YUCK
+#endif // LP64
assert(dst != klass_RInfo && dst != k_RInfo, "need 3 registers");
__ movl(dst, Address(k_RInfo, sizeof(oopDesc) + Klass::super_check_offset_offset_in_bytes()));
// See if we get an immediate positive hit
- __ cmpl(k_RInfo, Address(klass_RInfo, dst, Address::times_1));
+ __ cmpptr(k_RInfo, Address(klass_RInfo, dst, Address::times_1));
__ jcc(Assembler::equal, one);
// check for immediate negative hit
__ cmpl(dst, sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes());
__ jcc(Assembler::notEqual, zero);
// check for self
- __ cmpl(klass_RInfo, k_RInfo);
+ __ cmpptr(klass_RInfo, k_RInfo);
__ jcc(Assembler::equal, one);
- __ pushl(klass_RInfo);
- __ pushl(k_RInfo);
+ __ push(klass_RInfo);
+ __ push(k_RInfo);
__ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
- __ popl(klass_RInfo);
- __ popl(dst);
+ __ pop(klass_RInfo);
+ __ pop(dst);
__ jmp(done);
}
}
__ bind(zero);
- __ xorl(dst, dst);
+ __ xorptr(dst, dst);
__ jmp(done);
__ bind(one);
- __ movl(dst, 1);
+ __ movptr(dst, 1);
__ bind(done);
} else {
ShouldNotReachHere();
@@ -1706,8 +1860,7 @@ void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
- if (op->code() == lir_cas_long) {
- assert(VM_Version::supports_cx8(), "wrong machine");
+ if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
assert(op->new_value()->as_register_lo() == rbx, "wrong register");
@@ -1716,10 +1869,11 @@ void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
if (os::is_MP()) {
__ lock();
}
- __ cmpxchg8(Address(addr, 0));
+ NOT_LP64(__ cmpxchg8(Address(addr, 0)));
- } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
- Register addr = op->addr()->as_register();
+ } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
+ NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
+ Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
Register newval = op->new_value()->as_register();
Register cmpval = op->cmp_value()->as_register();
assert(cmpval == rax, "wrong register");
@@ -1730,7 +1884,28 @@ void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
if (os::is_MP()) {
__ lock();
}
- __ cmpxchg(newval, Address(addr, 0));
+ if ( op->code() == lir_cas_obj) {
+ __ cmpxchgptr(newval, Address(addr, 0));
+ } else if (op->code() == lir_cas_int) {
+ __ cmpxchgl(newval, Address(addr, 0));
+ } else {
+ LP64_ONLY(__ cmpxchgq(newval, Address(addr, 0)));
+ }
+#ifdef _LP64
+ } else if (op->code() == lir_cas_long) {
+ Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
+ Register newval = op->new_value()->as_register_lo();
+ Register cmpval = op->cmp_value()->as_register_lo();
+ assert(cmpval == rax, "wrong register");
+ assert(newval != NULL, "new val must be register");
+ assert(cmpval != newval, "cmp and new values must be in different registers");
+ assert(cmpval != addr, "cmp and addr must be in different registers");
+ assert(newval != addr, "new value and addr must be in different registers");
+ if (os::is_MP()) {
+ __ lock();
+ }
+ __ cmpxchgq(newval, Address(addr, 0));
+#endif // _LP64
} else {
Unimplemented();
}
@@ -1765,17 +1940,17 @@ void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, L
// optimized version that does not require a branch
if (opr2->is_single_cpu()) {
assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
- __ cmovl(ncond, result->as_register(), opr2->as_register());
+ __ cmov(ncond, result->as_register(), opr2->as_register());
} else if (opr2->is_double_cpu()) {
assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
- __ cmovl(ncond, result->as_register_lo(), opr2->as_register_lo());
- __ cmovl(ncond, result->as_register_hi(), opr2->as_register_hi());
+ __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
+ NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
} else if (opr2->is_single_stack()) {
__ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
} else if (opr2->is_double_stack()) {
- __ cmovl(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
- __ cmovl(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));
+ __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
+ NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
} else {
ShouldNotReachHere();
}
@@ -1851,23 +2026,28 @@ void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr
// cpu register - cpu register
Register rreg_lo = right->as_register_lo();
Register rreg_hi = right->as_register_hi();
- assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi);
+ NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
+ LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
switch (code) {
case lir_add:
- __ addl(lreg_lo, rreg_lo);
- __ adcl(lreg_hi, rreg_hi);
+ __ addptr(lreg_lo, rreg_lo);
+ NOT_LP64(__ adcl(lreg_hi, rreg_hi));
break;
case lir_sub:
- __ subl(lreg_lo, rreg_lo);
- __ sbbl(lreg_hi, rreg_hi);
+ __ subptr(lreg_lo, rreg_lo);
+ NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
break;
case lir_mul:
+#ifdef _LP64
+ __ imulq(lreg_lo, rreg_lo);
+#else
assert(lreg_lo == rax && lreg_hi == rdx, "must be");
__ imull(lreg_hi, rreg_lo);
__ imull(rreg_hi, lreg_lo);
__ addl (rreg_hi, lreg_hi);
__ mull (rreg_lo);
__ addl (lreg_hi, rreg_hi);
+#endif // _LP64
break;
default:
ShouldNotReachHere();
@@ -1875,20 +2055,35 @@ void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr
} else if (right->is_constant()) {
// cpu register - constant
+#ifdef _LP64
+ jlong c = right->as_constant_ptr()->as_jlong_bits();
+ __ movptr(r10, (intptr_t) c);
+ switch (code) {
+ case lir_add:
+ __ addptr(lreg_lo, r10);
+ break;
+ case lir_sub:
+ __ subptr(lreg_lo, r10);
+ break;
+ default:
+ ShouldNotReachHere();
+ }
+#else
jint c_lo = right->as_constant_ptr()->as_jint_lo();
jint c_hi = right->as_constant_ptr()->as_jint_hi();
switch (code) {
case lir_add:
- __ addl(lreg_lo, c_lo);
+ __ addptr(lreg_lo, c_lo);
__ adcl(lreg_hi, c_hi);
break;
case lir_sub:
- __ subl(lreg_lo, c_lo);
+ __ subptr(lreg_lo, c_lo);
__ sbbl(lreg_hi, c_hi);
break;
default:
ShouldNotReachHere();
}
+#endif // _LP64
} else {
ShouldNotReachHere();
@@ -2065,11 +2260,11 @@ void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr
jint c = right->as_constant_ptr()->as_jint();
switch (code) {
case lir_add: {
- __ increment(laddr, c);
+ __ incrementl(laddr, c);
break;
}
case lir_sub: {
- __ decrement(laddr, c);
+ __ decrementl(laddr, c);
break;
}
default: ShouldNotReachHere();
@@ -2211,9 +2406,9 @@ void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr
} else {
Register rright = right->as_register();
switch (code) {
- case lir_logic_and: __ andl (reg, rright); break;
- case lir_logic_or : __ orl (reg, rright); break;
- case lir_logic_xor: __ xorl (reg, rright); break;
+ case lir_logic_and: __ andptr (reg, rright); break;
+ case lir_logic_or : __ orptr (reg, rright); break;
+ case lir_logic_xor: __ xorptr (reg, rright); break;
default: ShouldNotReachHere();
}
}
@@ -2222,6 +2417,21 @@ void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr
Register l_lo = left->as_register_lo();
Register l_hi = left->as_register_hi();
if (right->is_constant()) {
+#ifdef _LP64
+ __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
+ switch (code) {
+ case lir_logic_and:
+ __ andq(l_lo, rscratch1);
+ break;
+ case lir_logic_or:
+ __ orq(l_lo, rscratch1);
+ break;
+ case lir_logic_xor:
+ __ xorq(l_lo, rscratch1);
+ break;
+ default: ShouldNotReachHere();
+ }
+#else
int r_lo = right->as_constant_ptr()->as_jint_lo();
int r_hi = right->as_constant_ptr()->as_jint_hi();
switch (code) {
@@ -2239,22 +2449,23 @@ void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr
break;
default: ShouldNotReachHere();
}
+#endif // _LP64
} else {
Register r_lo = right->as_register_lo();
Register r_hi = right->as_register_hi();
assert(l_lo != r_hi, "overwriting registers");
switch (code) {
case lir_logic_and:
- __ andl(l_lo, r_lo);
- __ andl(l_hi, r_hi);
+ __ andptr(l_lo, r_lo);
+ NOT_LP64(__ andptr(l_hi, r_hi);)
break;
case lir_logic_or:
- __ orl(l_lo, r_lo);
- __ orl(l_hi, r_hi);
+ __ orptr(l_lo, r_lo);
+ NOT_LP64(__ orptr(l_hi, r_hi);)
break;
case lir_logic_xor:
- __ xorl(l_lo, r_lo);
- __ xorl(l_hi, r_hi);
+ __ xorptr(l_lo, r_lo);
+ NOT_LP64(__ xorptr(l_hi, r_hi);)
break;
default: ShouldNotReachHere();
}
@@ -2263,6 +2474,9 @@ void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr
Register dst_lo = dst->as_register_lo();
Register dst_hi = dst->as_register_hi();
+#ifdef _LP64
+ move_regs(l_lo, dst_lo);
+#else
if (dst_lo == l_hi) {
assert(dst_hi != l_lo, "overwriting registers");
move_regs(l_hi, dst_hi);
@@ -2272,6 +2486,7 @@ void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr
move_regs(l_lo, dst_lo);
move_regs(l_hi, dst_hi);
}
+#endif // _LP64
}
}
@@ -2306,7 +2521,7 @@ void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right,
move_regs(lreg, dreg);
} else if (code == lir_irem) {
Label done;
- __ movl(dreg, lreg);
+ __ mov(dreg, lreg);
__ andl(dreg, 0x80000000 | (divisor - 1));
__ jcc(Assembler::positive, done);
__ decrement(dreg);
@@ -2340,21 +2555,36 @@ void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2,
Register reg1 = opr1->as_register();
if (opr2->is_single_cpu()) {
// cpu register - cpu register
- __ cmpl(reg1, opr2->as_register());
+ if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
+ __ cmpptr(reg1, opr2->as_register());
+ } else {
+ assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
+ __ cmpl(reg1, opr2->as_register());
+ }
} else if (opr2->is_stack()) {
// cpu register - stack
- __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
+ if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
+ __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
+ } else {
+ __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
+ }
} else if (opr2->is_constant()) {
// cpu register - constant
LIR_Const* c = opr2->as_constant_ptr();
if (c->type() == T_INT) {
__ cmpl(reg1, c->as_jint());
- } else if (c->type() == T_OBJECT) {
+ } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
+ // In 64bit oops are single register
jobject o = c->as_jobject();
if (o == NULL) {
- __ cmpl(reg1, NULL_WORD);
+ __ cmpptr(reg1, (int32_t)NULL_WORD);
} else {
+#ifdef _LP64
+ __ movoop(rscratch1, o);
+ __ cmpptr(reg1, rscratch1);
+#else
__ cmpoop(reg1, c->as_jobject());
+#endif // _LP64
}
} else {
ShouldNotReachHere();
@@ -2373,6 +2603,9 @@ void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2,
Register xlo = opr1->as_register_lo();
Register xhi = opr1->as_register_hi();
if (opr2->is_double_cpu()) {
+#ifdef _LP64
+ __ cmpptr(xlo, opr2->as_register_lo());
+#else
// cpu register - cpu register
Register ylo = opr2->as_register_lo();
Register yhi = opr2->as_register_hi();
@@ -2381,11 +2614,16 @@ void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2,
if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
__ orl(xhi, xlo);
}
+#endif // _LP64
} else if (opr2->is_constant()) {
// cpu register - constant 0
assert(opr2->as_jlong() == (jlong)0, "only handles zero");
+#ifdef _LP64
+ __ cmpptr(xlo, (int32_t)opr2->as_jlong());
+#else
assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
__ orl(xhi, xlo);
+#endif // _LP64
} else {
ShouldNotReachHere();
}
@@ -2438,16 +2676,28 @@ void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2,
__ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
} else if (opr1->is_address() && opr2->is_constant()) {
+ LIR_Const* c = opr2->as_constant_ptr();
+#ifdef _LP64
+ if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
+ assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
+ __ movoop(rscratch1, c->as_jobject());
+ }
+#endif // LP64
if (op->info() != NULL) {
add_debug_info_for_null_check_here(op->info());
}
// special case: address - constant
LIR_Address* addr = opr1->as_address_ptr();
- LIR_Const* c = opr2->as_constant_ptr();
if (c->type() == T_INT) {
__ cmpl(as_Address(addr), c->as_jint());
- } else if (c->type() == T_OBJECT) {
+ } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
+#ifdef _LP64
+ // %%% Make this explode if addr isn't reachable until we figure out a
+ // better strategy by giving noreg as the temp for as_Address
+ __ cmpptr(rscratch1, as_Address(addr, noreg));
+#else
__ cmpoop(as_Address(addr), c->as_jobject());
+#endif // _LP64
} else {
ShouldNotReachHere();
}
@@ -2476,11 +2726,27 @@ void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Op
}
} else {
assert(code == lir_cmp_l2i, "check");
+#ifdef _LP64
+ Register dest = dst->as_register();
+ __ xorptr(dest, dest);
+ Label high, done;
+ __ cmpptr(left->as_register_lo(), right->as_register_lo());
+ __ jcc(Assembler::equal, done);
+ __ jcc(Assembler::greater, high);
+ __ decrement(dest);
+ __ jmp(done);
+ __ bind(high);
+ __ increment(dest);
+
+ __ bind(done);
+
+#else
__ lcmp2int(left->as_register_hi(),
left->as_register_lo(),
right->as_register_hi(),
right->as_register_lo());
move_regs(left->as_register_hi(), dst->as_register());
+#endif // _LP64
}
}
@@ -2551,7 +2817,8 @@ void LIR_Assembler::emit_static_call_stub() {
__ movoop(rbx, (jobject)NULL);
// must be set to -1 at code generation time
assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP");
- __ jump(RuntimeAddress((address)-1));
+ // On 64bit this will die since it will take a movq & jmp, must be only a jmp
+ __ jump(RuntimeAddress(__ pc()));
assert(__ offset() - start <= call_stub_size, "stub too big")
__ end_a_stub();
@@ -2616,6 +2883,14 @@ void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr
Register lo = left->as_register_lo();
Register hi = left->as_register_hi();
assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
+#ifdef _LP64
+ switch (code) {
+ case lir_shl: __ shlptr(lo); break;
+ case lir_shr: __ sarptr(lo); break;
+ case lir_ushr: __ shrptr(lo); break;
+ default: ShouldNotReachHere();
+ }
+#else
switch (code) {
case lir_shl: __ lshl(hi, lo); break;
@@ -2623,6 +2898,7 @@ void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr
case lir_ushr: __ lshr(hi, lo, false); break;
default: ShouldNotReachHere();
}
+#endif // LP64
} else {
ShouldNotReachHere();
}
@@ -2643,7 +2919,21 @@ void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr de
default: ShouldNotReachHere();
}
} else if (dest->is_double_cpu()) {
+#ifndef _LP64
Unimplemented();
+#else
+ // first move left into dest so that left is not destroyed by the shift
+ Register value = dest->as_register_lo();
+ count = count & 0x1F; // Java spec
+
+ move_regs(left->as_register_lo(), value);
+ switch (code) {
+ case lir_shl: __ shlptr(value, count); break;
+ case lir_shr: __ sarptr(value, count); break;
+ case lir_ushr: __ shrptr(value, count); break;
+ default: ShouldNotReachHere();
+ }
+#endif // _LP64
} else {
ShouldNotReachHere();
}
@@ -2654,7 +2944,7 @@ void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
- __ movl (Address(rsp, offset_from_rsp_in_bytes), r);
+ __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
}
@@ -2662,7 +2952,7 @@ void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
- __ movl (Address(rsp, offset_from_rsp_in_bytes), c);
+ __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
}
@@ -2710,27 +3000,52 @@ void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
// these are just temporary placements until we need to reload
store_parameter(src_pos, 3);
store_parameter(src, 4);
- assert(src == rcx && src_pos == rdx, "mismatch in calling convention");
+ NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
+
+ address entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy);
// pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
- __ pushl(length);
- __ pushl(dst_pos);
- __ pushl(dst);
- __ pushl(src_pos);
- __ pushl(src);
- address entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy);
+#ifdef _LP64
+ // The arguments are in java calling convention so we can trivially shift them to C
+ // convention
+ assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
+ __ mov(c_rarg0, j_rarg0);
+ assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
+ __ mov(c_rarg1, j_rarg1);
+ assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
+ __ mov(c_rarg2, j_rarg2);
+ assert_different_registers(c_rarg3, j_rarg4);
+ __ mov(c_rarg3, j_rarg3);
+#ifdef _WIN64
+ // Allocate abi space for args but be sure to keep stack aligned
+ __ subptr(rsp, 6*wordSize);
+ store_parameter(j_rarg4, 4);
+ __ call(RuntimeAddress(entry));
+ __ addptr(rsp, 6*wordSize);
+#else
+ __ mov(c_rarg4, j_rarg4);
+ __ call(RuntimeAddress(entry));
+#endif // _WIN64
+#else
+ __ push(length);
+ __ push(dst_pos);
+ __ push(dst);
+ __ push(src_pos);
+ __ push(src);
__ call_VM_leaf(entry, 5); // removes pushed parameter from the stack
+#endif // _LP64
+
__ cmpl(rax, 0);
__ jcc(Assembler::equal, *stub->continuation());
// Reload values from the stack so they are where the stub
// expects them.
- __ movl (dst, Address(rsp, 0*BytesPerWord));
- __ movl (dst_pos, Address(rsp, 1*BytesPerWord));
- __ movl (length, Address(rsp, 2*BytesPerWord));
- __ movl (src_pos, Address(rsp, 3*BytesPerWord));
- __ movl (src, Address(rsp, 4*BytesPerWord));
+ __ movptr (dst, Address(rsp, 0*BytesPerWord));
+ __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
+ __ movptr (length, Address(rsp, 2*BytesPerWord));
+ __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
+ __ movptr (src, Address(rsp, 4*BytesPerWord));
__ jmp(*stub->entry());
__ bind(*stub->continuation());
@@ -2769,13 +3084,15 @@ void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
+ // length and pos's are all sign extended at this point on 64bit
+
// test for NULL
if (flags & LIR_OpArrayCopy::src_null_check) {
- __ testl(src, src);
+ __ testptr(src, src);
__ jcc(Assembler::zero, *stub->entry());
}
if (flags & LIR_OpArrayCopy::dst_null_check) {
- __ testl(dst, dst);
+ __ testptr(dst, dst);
__ jcc(Assembler::zero, *stub->entry());
}
@@ -2794,19 +3111,19 @@ void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
}
if (flags & LIR_OpArrayCopy::src_range_check) {
- __ leal(tmp, Address(src_pos, length, Address::times_1, 0));
+ __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
__ cmpl(tmp, src_length_addr);
__ jcc(Assembler::above, *stub->entry());
}
if (flags & LIR_OpArrayCopy::dst_range_check) {
- __ leal(tmp, Address(dst_pos, length, Address::times_1, 0));
+ __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
__ cmpl(tmp, dst_length_addr);
__ jcc(Assembler::above, *stub->entry());
}
if (flags & LIR_OpArrayCopy::type_check) {
- __ movl(tmp, src_klass_addr);
- __ cmpl(tmp, dst_klass_addr);
+ __ movptr(tmp, src_klass_addr);
+ __ cmpptr(tmp, dst_klass_addr);
__ jcc(Assembler::notEqual, *stub->entry());
}
@@ -2822,14 +3139,14 @@ void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
Label known_ok, halt;
__ movoop(tmp, default_type->encoding());
if (basic_type != T_OBJECT) {
- __ cmpl(tmp, dst_klass_addr);
+ __ cmpptr(tmp, dst_klass_addr);
__ jcc(Assembler::notEqual, halt);
- __ cmpl(tmp, src_klass_addr);
+ __ cmpptr(tmp, src_klass_addr);
__ jcc(Assembler::equal, known_ok);
} else {
- __ cmpl(tmp, dst_klass_addr);
+ __ cmpptr(tmp, dst_klass_addr);
__ jcc(Assembler::equal, known_ok);
- __ cmpl(src, dst);
+ __ cmpptr(src, dst);
__ jcc(Assembler::equal, known_ok);
}
__ bind(halt);
@@ -2838,14 +3155,24 @@ void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
}
#endif
- __ leal(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
- store_parameter(tmp, 0);
- __ leal(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
- store_parameter(tmp, 1);
if (shift_amount > 0 && basic_type != T_OBJECT) {
- __ shll(length, shift_amount);
+ __ shlptr(length, shift_amount);
}
+
+#ifdef _LP64
+ assert_different_registers(c_rarg0, dst, dst_pos, length);
+ __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
+ assert_different_registers(c_rarg1, length);
+ __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
+ __ mov(c_rarg2, length);
+
+#else
+ __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
+ store_parameter(tmp, 0);
+ __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
+ store_parameter(tmp, 1);
store_parameter(length, 2);
+#endif // _LP64
if (basic_type == T_OBJECT) {
__ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::oop_arraycopy), 0);
} else {
@@ -2945,13 +3272,13 @@ void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
}
}
} else {
- __ movl(recv, Address(recv, oopDesc::klass_offset_in_bytes()));
+ __ movptr(recv, Address(recv, oopDesc::klass_offset_in_bytes()));
Label update_done;
uint i;
for (i = 0; i < VirtualCallData::row_limit(); i++) {
Label next_test;
// See if the receiver is receiver[n].
- __ cmpl(recv, Address(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))));
+ __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))));
__ jcc(Assembler::notEqual, next_test);
Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
__ addl(data_addr, DataLayout::counter_increment);
@@ -2963,9 +3290,9 @@ void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
for (i = 0; i < VirtualCallData::row_limit(); i++) {
Label next_test;
Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
- __ cmpl(recv_addr, NULL_WORD);
+ __ cmpptr(recv_addr, (int32_t)NULL_WORD);
__ jcc(Assembler::notEqual, next_test);
- __ movl(recv_addr, recv);
+ __ movptr(recv_addr, recv);
__ movl(Address(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))), DataLayout::counter_increment);
if (i < (VirtualCallData::row_limit() - 1)) {
__ jmp(update_done);
@@ -2985,7 +3312,7 @@ void LIR_Assembler::emit_delay(LIR_OpDelay*) {
void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
- __ leal(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
+ __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
}
@@ -3001,6 +3328,11 @@ void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
} else if (left->is_double_cpu()) {
Register lo = left->as_register_lo();
+#ifdef _LP64
+ Register dst = dest->as_register_lo();
+ __ movptr(dst, lo);
+ __ negptr(dst);
+#else
Register hi = left->as_register_hi();
__ lneg(hi, lo);
if (dest->as_register_lo() == hi) {
@@ -3011,6 +3343,7 @@ void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
move_regs(lo, dest->as_register_lo());
move_regs(hi, dest->as_register_hi());
}
+#endif // _LP64
} else if (dest->is_single_xmm()) {
if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
@@ -3039,8 +3372,9 @@ void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) {
assert(addr->is_address() && dest->is_register(), "check");
- Register reg = dest->as_register();
- __ leal(dest->as_register(), as_Address(addr->as_address_ptr()));
+ Register reg;
+ reg = dest->as_pointer_register();
+ __ lea(reg, as_Address(addr->as_address_ptr()));
}
@@ -3063,9 +3397,13 @@ void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type,
if (src->is_double_xmm()) {
if (dest->is_double_cpu()) {
- __ movd(dest->as_register_lo(), src->as_xmm_double_reg());
+#ifdef _LP64
+ __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
+#else
+ __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
__ psrlq(src->as_xmm_double_reg(), 32);
- __ movd(dest->as_register_hi(), src->as_xmm_double_reg());
+ __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
+#endif // _LP64
} else if (dest->is_double_stack()) {
__ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
} else if (dest->is_address()) {
@@ -3109,7 +3447,8 @@ void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type,
void LIR_Assembler::membar() {
- __ membar();
+ // QQQ sparc TSO uses this,
+ __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
}
void LIR_Assembler::membar_acquire() {
@@ -3124,7 +3463,12 @@ void LIR_Assembler::membar_release() {
void LIR_Assembler::get_thread(LIR_Opr result_reg) {
assert(result_reg->is_register(), "check");
+#ifdef _LP64
+ // __ get_thread(result_reg->as_register_lo());
+ __ mov(result_reg->as_register(), r15_thread);
+#else
__ get_thread(result_reg->as_register());
+#endif // _LP64
}
diff --git a/hotspot/src/cpu/x86/vm/c1_LIRAssembler_x86.hpp b/hotspot/src/cpu/x86/vm/c1_LIRAssembler_x86.hpp
index 5621a95a372..41747a1f4fe 100644
--- a/hotspot/src/cpu/x86/vm/c1_LIRAssembler_x86.hpp
+++ b/hotspot/src/cpu/x86/vm/c1_LIRAssembler_x86.hpp
@@ -36,13 +36,20 @@
address float_constant(float f);
address double_constant(double d);
+ bool is_literal_address(LIR_Address* addr);
+
+ // When we need to use something other than rscratch1 use this
+ // method.
+ Address as_Address(LIR_Address* addr, Register tmp);
+
+
public:
void store_parameter(Register r, int offset_from_esp_in_words);
void store_parameter(jint c, int offset_from_esp_in_words);
void store_parameter(jobject c, int offset_from_esp_in_words);
- enum { call_stub_size = 15,
+ enum { call_stub_size = NOT_LP64(15) LP64_ONLY(28),
exception_handler_size = DEBUG_ONLY(1*K) NOT_DEBUG(175),
- deopt_handler_size = 10
+ deopt_handler_size = NOT_LP64(10) LP64_ONLY(17)
};
diff --git a/hotspot/src/cpu/x86/vm/c1_LIRGenerator_x86.cpp b/hotspot/src/cpu/x86/vm/c1_LIRGenerator_x86.cpp
index d2f9e2d35b7..b8c29fb09a8 100644
--- a/hotspot/src/cpu/x86/vm/c1_LIRGenerator_x86.cpp
+++ b/hotspot/src/cpu/x86/vm/c1_LIRGenerator_x86.cpp
@@ -77,7 +77,7 @@ LIR_Opr LIRGenerator::result_register_for(ValueType* type, bool callee) {
switch (type->tag()) {
case intTag: opr = FrameMap::rax_opr; break;
case objectTag: opr = FrameMap::rax_oop_opr; break;
- case longTag: opr = FrameMap::rax_rdx_long_opr; break;
+ case longTag: opr = FrameMap::long0_opr; break;
case floatTag: opr = UseSSE >= 1 ? FrameMap::xmm0_float_opr : FrameMap::fpu0_float_opr; break;
case doubleTag: opr = UseSSE >= 2 ? FrameMap::xmm0_double_opr : FrameMap::fpu0_double_opr; break;
@@ -117,12 +117,14 @@ bool LIRGenerator::can_store_as_constant(Value v, BasicType type) const {
bool LIRGenerator::can_inline_as_constant(Value v) const {
+ if (v->type()->tag() == longTag) return false;
return v->type()->tag() != objectTag ||
(v->type()->is_constant() && v->type()->as_ObjectType()->constant_value()->is_null_object());
}
bool LIRGenerator::can_inline_as_constant(LIR_Const* c) const {
+ if (c->type() == T_LONG) return false;
return c->type() != T_OBJECT || c->as_jobject() == NULL;
}
@@ -155,6 +157,13 @@ LIR_Address* LIRGenerator::emit_array_address(LIR_Opr array_opr, LIR_Opr index_o
addr = new LIR_Address(array_opr,
offset_in_bytes + index_opr->as_jint() * elem_size, type);
} else {
+#ifdef _LP64
+ if (index_opr->type() == T_INT) {
+ LIR_Opr tmp = new_register(T_LONG);
+ __ convert(Bytecodes::_i2l, index_opr, tmp);
+ index_opr = tmp;
+ }
+#endif // _LP64
addr = new LIR_Address(array_opr,
index_opr,
LIR_Address::scale(type),
@@ -164,7 +173,7 @@ LIR_Address* LIRGenerator::emit_array_address(LIR_Opr array_opr, LIR_Opr index_o
// This store will need a precise card mark, so go ahead and
// compute the full adddres instead of computing once for the
// store and again for the card mark.
- LIR_Opr tmp = new_register(T_INT);
+ LIR_Opr tmp = new_pointer_register();
__ leal(LIR_OprFact::address(addr), tmp);
return new LIR_Address(tmp, 0, type);
} else {
@@ -174,9 +183,8 @@ LIR_Address* LIRGenerator::emit_array_address(LIR_Opr array_opr, LIR_Opr index_o
void LIRGenerator::increment_counter(address counter, int step) {
- LIR_Opr temp = new_register(T_INT);
- LIR_Opr pointer = new_register(T_INT);
- __ move(LIR_OprFact::intConst((int)counter), pointer);
+ LIR_Opr pointer = new_pointer_register();
+ __ move(LIR_OprFact::intptrConst(counter), pointer);
LIR_Address* addr = new LIR_Address(pointer, 0, T_INT);
increment_counter(addr, step);
}
@@ -481,7 +489,7 @@ void LIRGenerator::do_ArithmeticOp_Long(ArithmeticOp* x) {
left.load_item();
right.load_item();
- LIR_Opr reg = FrameMap::rax_rdx_long_opr;
+ LIR_Opr reg = FrameMap::long0_opr;
arithmetic_op_long(x->op(), reg, left.result(), right.result(), NULL);
LIR_Opr result = rlock_result(x);
__ move(reg, result);
@@ -690,10 +698,10 @@ void LIRGenerator::do_AttemptUpdate(Intrinsic* x) {
LIRItem new_value (x->argument_at(2), this); // replace field with new_value if it matches cmp_value
// compare value must be in rdx,eax (hi,lo); may be destroyed by cmpxchg8 instruction
- cmp_value.load_item_force(FrameMap::rax_rdx_long_opr);
+ cmp_value.load_item_force(FrameMap::long0_opr);
// new value must be in rcx,ebx (hi,lo)
- new_value.load_item_force(FrameMap::rbx_rcx_long_opr);
+ new_value.load_item_force(FrameMap::long1_opr);
// object pointer register is overwritten with field address
obj.load_item();
@@ -720,7 +728,10 @@ void LIRGenerator::do_CompareAndSwap(Intrinsic* x, ValueType* type) {
LIRItem val (x->argument_at(3), this); // replace field with val if matches cmp
assert(obj.type()->tag() == objectTag, "invalid type");
- assert(offset.type()->tag() == intTag, "invalid type");
+
+ // In 64bit the type can be long, sparc doesn't have this assert
+ // assert(offset.type()->tag() == intTag, "invalid type");
+
assert(cmp.type()->tag() == type->tag(), "invalid type");
assert(val.type()->tag() == type->tag(), "invalid type");
@@ -735,8 +746,8 @@ void LIRGenerator::do_CompareAndSwap(Intrinsic* x, ValueType* type) {
cmp.load_item_force(FrameMap::rax_opr);
val.load_item();
} else if (type == longType) {
- cmp.load_item_force(FrameMap::rax_rdx_long_opr);
- val.load_item_force(FrameMap::rbx_rcx_long_opr);
+ cmp.load_item_force(FrameMap::long0_opr);
+ val.load_item_force(FrameMap::long1_opr);
} else {
ShouldNotReachHere();
}
@@ -833,12 +844,33 @@ void LIRGenerator::do_ArrayCopy(Intrinsic* x) {
// operands for arraycopy must use fixed registers, otherwise
// LinearScan will fail allocation (because arraycopy always needs a
// call)
+
+#ifndef _LP64
src.load_item_force (FrameMap::rcx_oop_opr);
src_pos.load_item_force (FrameMap::rdx_opr);
dst.load_item_force (FrameMap::rax_oop_opr);
dst_pos.load_item_force (FrameMap::rbx_opr);
length.load_item_force (FrameMap::rdi_opr);
LIR_Opr tmp = (FrameMap::rsi_opr);
+#else
+
+ // The java calling convention will give us enough registers
+ // so that on the stub side the args will be perfect already.
+ // On the other slow/special case side we call C and the arg
+ // positions are not similar enough to pick one as the best.
+ // Also because the java calling convention is a "shifted" version
+ // of the C convention we can process the java args trivially into C
+ // args without worry of overwriting during the xfer
+
+ src.load_item_force (FrameMap::as_oop_opr(j_rarg0));
+ src_pos.load_item_force (FrameMap::as_opr(j_rarg1));
+ dst.load_item_force (FrameMap::as_oop_opr(j_rarg2));
+ dst_pos.load_item_force (FrameMap::as_opr(j_rarg3));
+ length.load_item_force (FrameMap::as_opr(j_rarg4));
+
+ LIR_Opr tmp = FrameMap::as_opr(j_rarg5);
+#endif // LP64
+
set_no_result(x);
int flags;
@@ -857,7 +889,7 @@ LIR_Opr fixed_register_for(BasicType type) {
case T_FLOAT: return FrameMap::fpu0_float_opr;
case T_DOUBLE: return FrameMap::fpu0_double_opr;
case T_INT: return FrameMap::rax_opr;
- case T_LONG: return FrameMap::rax_rdx_long_opr;
+ case T_LONG: return FrameMap::long0_opr;
default: ShouldNotReachHere(); return LIR_OprFact::illegalOpr;
}
}
@@ -1161,9 +1193,13 @@ void LIRGenerator::do_If(If* x) {
LIR_Opr LIRGenerator::getThreadPointer() {
+#ifdef _LP64
+ return FrameMap::as_pointer_opr(r15_thread);
+#else
LIR_Opr result = new_register(T_INT);
__ get_thread(result);
return result;
+#endif //
}
void LIRGenerator::trace_block_entry(BlockBegin* block) {
diff --git a/hotspot/src/cpu/x86/vm/c1_LinearScan_x86.hpp b/hotspot/src/cpu/x86/vm/c1_LinearScan_x86.hpp
index cdfa446daa2..73510cd5525 100644
--- a/hotspot/src/cpu/x86/vm/c1_LinearScan_x86.hpp
+++ b/hotspot/src/cpu/x86/vm/c1_LinearScan_x86.hpp
@@ -23,18 +23,29 @@
*/
inline bool LinearScan::is_processed_reg_num(int reg_num) {
+#ifndef _LP64
// rsp and rbp (numbers 6 ancd 7) are ignored
assert(FrameMap::rsp_opr->cpu_regnr() == 6, "wrong assumption below");
assert(FrameMap::rbp_opr->cpu_regnr() == 7, "wrong assumption below");
assert(reg_num >= 0, "invalid reg_num");
return reg_num < 6 || reg_num > 7;
+#else
+ // rsp and rbp, r10, r15 (numbers 6 ancd 7) are ignored
+ assert(FrameMap::r10_opr->cpu_regnr() == 12, "wrong assumption below");
+ assert(FrameMap::r15_opr->cpu_regnr() == 13, "wrong assumption below");
+ assert(FrameMap::rsp_opr->cpu_regnrLo() == 14, "wrong assumption below");
+ assert(FrameMap::rbp_opr->cpu_regnrLo() == 15, "wrong assumption below");
+ assert(reg_num >= 0, "invalid reg_num");
+
+ return reg_num < 12 || reg_num > 15;
+#endif // _LP64
}
inline int LinearScan::num_physical_regs(BasicType type) {
// Intel requires two cpu registers for long,
// but requires only one fpu register for double
- if (type == T_LONG) {
+ if (LP64_ONLY(false &&) type == T_LONG) {
return 2;
}
return 1;
diff --git a/hotspot/src/cpu/x86/vm/c1_MacroAssembler_x86.cpp b/hotspot/src/cpu/x86/vm/c1_MacroAssembler_x86.cpp
index 27024aa8a4b..8af0ceeb89a 100644
--- a/hotspot/src/cpu/x86/vm/c1_MacroAssembler_x86.cpp
+++ b/hotspot/src/cpu/x86/vm/c1_MacroAssembler_x86.cpp
@@ -26,18 +26,17 @@
#include "incls/_c1_MacroAssembler_x86.cpp.incl"
int C1_MacroAssembler::lock_object(Register hdr, Register obj, Register disp_hdr, Register scratch, Label& slow_case) {
- const int aligned_mask = 3;
+ const int aligned_mask = BytesPerWord -1;
const int hdr_offset = oopDesc::mark_offset_in_bytes();
assert(hdr == rax, "hdr must be rax, for the cmpxchg instruction");
assert(hdr != obj && hdr != disp_hdr && obj != disp_hdr, "registers must be different");
- assert(BytesPerWord == 4, "adjust aligned_mask and code");
Label done;
int null_check_offset = -1;
verify_oop(obj);
// save object being locked into the BasicObjectLock
- movl(Address(disp_hdr, BasicObjectLock::obj_offset_in_bytes()), obj);
+ movptr(Address(disp_hdr, BasicObjectLock::obj_offset_in_bytes()), obj);
if (UseBiasedLocking) {
assert(scratch != noreg, "should have scratch register at this point");
@@ -47,16 +46,16 @@ int C1_MacroAssembler::lock_object(Register hdr, Register obj, Register disp_hdr
}
// Load object header
- movl(hdr, Address(obj, hdr_offset));
+ movptr(hdr, Address(obj, hdr_offset));
// and mark it as unlocked
- orl(hdr, markOopDesc::unlocked_value);
+ orptr(hdr, markOopDesc::unlocked_value);
// save unlocked object header into the displaced header location on the stack
- movl(Address(disp_hdr, 0), hdr);
+ movptr(Address(disp_hdr, 0), hdr);
// test if object header is still the same (i.e. unlocked), and if so, store the
// displaced header address in the object header - if it is not the same, get the
// object header instead
if (os::is_MP()) MacroAssembler::lock(); // must be immediately before cmpxchg!
- cmpxchg(disp_hdr, Address(obj, hdr_offset));
+ cmpxchgptr(disp_hdr, Address(obj, hdr_offset));
// if the object header was the same, we're done
if (PrintBiasedLockingStatistics) {
cond_inc32(Assembler::equal,
@@ -76,11 +75,11 @@ int C1_MacroAssembler::lock_object(Register hdr, Register obj, Register disp_hdr
//
// assuming both the stack pointer and page_size have their least
// significant 2 bits cleared and page_size is a power of 2
- subl(hdr, rsp);
- andl(hdr, aligned_mask - os::vm_page_size());
+ subptr(hdr, rsp);
+ andptr(hdr, aligned_mask - os::vm_page_size());
// for recursive locking, the result is zero => save it in the displaced header
// location (NULL in the displaced hdr location indicates recursive locking)
- movl(Address(disp_hdr, 0), hdr);
+ movptr(Address(disp_hdr, 0), hdr);
// otherwise we don't care about the result and handle locking via runtime call
jcc(Assembler::notZero, slow_case);
// done
@@ -90,35 +89,34 @@ int C1_MacroAssembler::lock_object(Register hdr, Register obj, Register disp_hdr
void C1_MacroAssembler::unlock_object(Register hdr, Register obj, Register disp_hdr, Label& slow_case) {
- const int aligned_mask = 3;
+ const int aligned_mask = BytesPerWord -1;
const int hdr_offset = oopDesc::mark_offset_in_bytes();
assert(disp_hdr == rax, "disp_hdr must be rax, for the cmpxchg instruction");
assert(hdr != obj && hdr != disp_hdr && obj != disp_hdr, "registers must be different");
- assert(BytesPerWord == 4, "adjust aligned_mask and code");
Label done;
if (UseBiasedLocking) {
// load object
- movl(obj, Address(disp_hdr, BasicObjectLock::obj_offset_in_bytes()));
+ movptr(obj, Address(disp_hdr, BasicObjectLock::obj_offset_in_bytes()));
biased_locking_exit(obj, hdr, done);
}
// load displaced header
- movl(hdr, Address(disp_hdr, 0));
+ movptr(hdr, Address(disp_hdr, 0));
// if the loaded hdr is NULL we had recursive locking
- testl(hdr, hdr);
+ testptr(hdr, hdr);
// if we had recursive locking, we are done
jcc(Assembler::zero, done);
if (!UseBiasedLocking) {
// load object
- movl(obj, Address(disp_hdr, BasicObjectLock::obj_offset_in_bytes()));
+ movptr(obj, Address(disp_hdr, BasicObjectLock::obj_offset_in_bytes()));
}
verify_oop(obj);
// test if object header is pointing to the displaced header, and if so, restore
// the displaced header in the object - if the object header is not pointing to
// the displaced header, get the object header instead
if (os::is_MP()) MacroAssembler::lock(); // must be immediately before cmpxchg!
- cmpxchg(hdr, Address(obj, hdr_offset));
+ cmpxchgptr(hdr, Address(obj, hdr_offset));
// if the object header was not pointing to the displaced header,
// we do unlocking via runtime call
jcc(Assembler::notEqual, slow_case);
@@ -141,13 +139,14 @@ void C1_MacroAssembler::initialize_header(Register obj, Register klass, Register
assert_different_registers(obj, klass, len);
if (UseBiasedLocking && !len->is_valid()) {
assert_different_registers(obj, klass, len, t1, t2);
- movl(t1, Address(klass, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
- movl(Address(obj, oopDesc::mark_offset_in_bytes()), t1);
+ movptr(t1, Address(klass, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
+ movptr(Address(obj, oopDesc::mark_offset_in_bytes()), t1);
} else {
- movl(Address(obj, oopDesc::mark_offset_in_bytes ()), (int)markOopDesc::prototype());
+ // This assumes that all prototype bits fit in an int32_t
+ movptr(Address(obj, oopDesc::mark_offset_in_bytes ()), (int32_t)(intptr_t)markOopDesc::prototype());
}
- movl(Address(obj, oopDesc::klass_offset_in_bytes()), klass);
+ movptr(Address(obj, oopDesc::klass_offset_in_bytes()), klass);
if (len->is_valid()) {
movl(Address(obj, arrayOopDesc::length_offset_in_bytes()), len);
}
@@ -160,25 +159,27 @@ void C1_MacroAssembler::initialize_body(Register obj, Register len_in_bytes, int
assert(obj != len_in_bytes && obj != t1 && t1 != len_in_bytes, "registers must be different");
assert((hdr_size_in_bytes & (BytesPerWord - 1)) == 0, "header size is not a multiple of BytesPerWord");
Register index = len_in_bytes;
- subl(index, hdr_size_in_bytes);
+ // index is positive and ptr sized
+ subptr(index, hdr_size_in_bytes);
jcc(Assembler::zero, done);
// initialize topmost word, divide index by 2, check if odd and test if zero
// note: for the remaining code to work, index must be a multiple of BytesPerWord
#ifdef ASSERT
{ Label L;
- testl(index, BytesPerWord - 1);
+ testptr(index, BytesPerWord - 1);
jcc(Assembler::zero, L);
stop("index is not a multiple of BytesPerWord");
bind(L);
}
#endif
- xorl(t1, t1); // use _zero reg to clear memory (shorter code)
+ xorptr(t1, t1); // use _zero reg to clear memory (shorter code)
if (UseIncDec) {
- shrl(index, 3); // divide by 8 and set carry flag if bit 2 was set
+ shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
} else {
- shrl(index, 2); // use 2 instructions to avoid partial flag stall
- shrl(index, 1);
+ shrptr(index, 2); // use 2 instructions to avoid partial flag stall
+ shrptr(index, 1);
}
+#ifndef _LP64
// index could have been not a multiple of 8 (i.e., bit 2 was set)
{ Label even;
// note: if index was a multiple of 8, than it cannot
@@ -186,16 +187,17 @@ void C1_MacroAssembler::initialize_body(Register obj, Register len_in_bytes, int
// => if it is even, we don't need to check for 0 again
jcc(Assembler::carryClear, even);
// clear topmost word (no jump needed if conditional assignment would work here)
- movl(Address(obj, index, Address::times_8, hdr_size_in_bytes - 0*BytesPerWord), t1);
+ movptr(Address(obj, index, Address::times_8, hdr_size_in_bytes - 0*BytesPerWord), t1);
// index could be 0 now, need to check again
jcc(Assembler::zero, done);
bind(even);
}
+#endif // !_LP64
// initialize remaining object fields: rdx is a multiple of 2 now
{ Label loop;
bind(loop);
- movl(Address(obj, index, Address::times_8, hdr_size_in_bytes - 1*BytesPerWord), t1);
- movl(Address(obj, index, Address::times_8, hdr_size_in_bytes - 2*BytesPerWord), t1);
+ movptr(Address(obj, index, Address::times_8, hdr_size_in_bytes - 1*BytesPerWord), t1);
+ NOT_LP64(movptr(Address(obj, index, Address::times_8, hdr_size_in_bytes - 2*BytesPerWord), t1);)
decrement(index);
jcc(Assembler::notZero, loop);
}
@@ -227,30 +229,30 @@ void C1_MacroAssembler::initialize_object(Register obj, Register klass, Register
const Register index = t2;
const int threshold = 6 * BytesPerWord; // approximate break even point for code size (see comments below)
if (var_size_in_bytes != noreg) {
- movl(index, var_size_in_bytes);
+ mov(index, var_size_in_bytes);
initialize_body(obj, index, hdr_size_in_bytes, t1_zero);
} else if (con_size_in_bytes <= threshold) {
// use explicit null stores
// code size = 2 + 3*n bytes (n = number of fields to clear)
- xorl(t1_zero, t1_zero); // use t1_zero reg to clear memory (shorter code)
+ xorptr(t1_zero, t1_zero); // use t1_zero reg to clear memory (shorter code)
for (int i = hdr_size_in_bytes; i < con_size_in_bytes; i += BytesPerWord)
- movl(Address(obj, i), t1_zero);
+ movptr(Address(obj, i), t1_zero);
} else if (con_size_in_bytes > hdr_size_in_bytes) {
// use loop to null out the fields
// code size = 16 bytes for even n (n = number of fields to clear)
// initialize last object field first if odd number of fields
- xorl(t1_zero, t1_zero); // use t1_zero reg to clear memory (shorter code)
- movl(index, (con_size_in_bytes - hdr_size_in_bytes) >> 3);
+ xorptr(t1_zero, t1_zero); // use t1_zero reg to clear memory (shorter code)
+ movptr(index, (con_size_in_bytes - hdr_size_in_bytes) >> 3);
// initialize last object field if constant size is odd
if (((con_size_in_bytes - hdr_size_in_bytes) & 4) != 0)
- movl(Address(obj, con_size_in_bytes - (1*BytesPerWord)), t1_zero);
+ movptr(Address(obj, con_size_in_bytes - (1*BytesPerWord)), t1_zero);
// initialize remaining object fields: rdx is a multiple of 2
{ Label loop;
bind(loop);
- movl(Address(obj, index, Address::times_8,
- hdr_size_in_bytes - (1*BytesPerWord)), t1_zero);
- movl(Address(obj, index, Address::times_8,
- hdr_size_in_bytes - (2*BytesPerWord)), t1_zero);
+ movptr(Address(obj, index, Address::times_8, hdr_size_in_bytes - (1*BytesPerWord)),
+ t1_zero);
+ NOT_LP64(movptr(Address(obj, index, Address::times_8, hdr_size_in_bytes - (2*BytesPerWord)),
+ t1_zero);)
decrement(index);
jcc(Assembler::notZero, loop);
}
@@ -269,17 +271,17 @@ void C1_MacroAssembler::allocate_array(Register obj, Register len, Register t1,
assert_different_registers(obj, len, t1, t2, klass);
// determine alignment mask
- assert(BytesPerWord == 4, "must be a multiple of 2 for masking code to work");
+ assert(!(BytesPerWord & 1), "must be a multiple of 2 for masking code to work");
// check for negative or excessive length
- cmpl(len, max_array_allocation_length);
+ cmpptr(len, (int32_t)max_array_allocation_length);
jcc(Assembler::above, slow_case);
const Register arr_size = t2; // okay to be the same
// align object end
- movl(arr_size, header_size * BytesPerWord + MinObjAlignmentInBytesMask);
- leal(arr_size, Address(arr_size, len, f));
- andl(arr_size, ~MinObjAlignmentInBytesMask);
+ movptr(arr_size, (int32_t)header_size * BytesPerWord + MinObjAlignmentInBytesMask);
+ lea(arr_size, Address(arr_size, len, f));
+ andptr(arr_size, ~MinObjAlignmentInBytesMask);
try_allocate(obj, arr_size, 0, t1, t2, slow_case);
@@ -305,12 +307,13 @@ void C1_MacroAssembler::inline_cache_check(Register receiver, Register iCache) {
// check against inline cache
assert(!MacroAssembler::needs_explicit_null_check(oopDesc::klass_offset_in_bytes()), "must add explicit null check");
int start_offset = offset();
- cmpl(iCache, Address(receiver, oopDesc::klass_offset_in_bytes()));
+ cmpptr(iCache, Address(receiver, oopDesc::klass_offset_in_bytes()));
// if icache check fails, then jump to runtime routine
// Note: RECEIVER must still contain the receiver!
jump_cc(Assembler::notEqual,
RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
- assert(offset() - start_offset == 9, "check alignment in emit_method_entry");
+ const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
+ assert(offset() - start_offset == ic_cmp_size, "check alignment in emit_method_entry");
}
@@ -364,7 +367,7 @@ void C1_MacroAssembler::verify_stack_oop(int stack_offset) {
void C1_MacroAssembler::verify_not_null_oop(Register r) {
if (!VerifyOops) return;
Label not_null;
- testl(r, r);
+ testptr(r, r);
jcc(Assembler::notZero, not_null);
stop("non-null oop required");
bind(not_null);
@@ -373,12 +376,12 @@ void C1_MacroAssembler::verify_not_null_oop(Register r) {
void C1_MacroAssembler::invalidate_registers(bool inv_rax, bool inv_rbx, bool inv_rcx, bool inv_rdx, bool inv_rsi, bool inv_rdi) {
#ifdef ASSERT
- if (inv_rax) movl(rax, 0xDEAD);
- if (inv_rbx) movl(rbx, 0xDEAD);
- if (inv_rcx) movl(rcx, 0xDEAD);
- if (inv_rdx) movl(rdx, 0xDEAD);
- if (inv_rsi) movl(rsi, 0xDEAD);
- if (inv_rdi) movl(rdi, 0xDEAD);
+ if (inv_rax) movptr(rax, 0xDEAD);
+ if (inv_rbx) movptr(rbx, 0xDEAD);
+ if (inv_rcx) movptr(rcx, 0xDEAD);
+ if (inv_rdx) movptr(rdx, 0xDEAD);
+ if (inv_rsi) movptr(rsi, 0xDEAD);
+ if (inv_rdi) movptr(rdi, 0xDEAD);
#endif
}
diff --git a/hotspot/src/cpu/x86/vm/c1_MacroAssembler_x86.hpp b/hotspot/src/cpu/x86/vm/c1_MacroAssembler_x86.hpp
index 62f6d4c14a8..d0b4230ad52 100644
--- a/hotspot/src/cpu/x86/vm/c1_MacroAssembler_x86.hpp
+++ b/hotspot/src/cpu/x86/vm/c1_MacroAssembler_x86.hpp
@@ -94,16 +94,17 @@
// Note: NEVER push values directly, but only through following push_xxx functions;
// This helps us to track the rsp changes compared to the entry rsp (->_rsp_offset)
- void push_jint (jint i) { _rsp_offset++; pushl(i); }
+ void push_jint (jint i) { _rsp_offset++; push(i); }
void push_oop (jobject o) { _rsp_offset++; pushoop(o); }
- void push_addr (Address a) { _rsp_offset++; pushl(a); }
- void push_reg (Register r) { _rsp_offset++; pushl(r); }
- void pop (Register r) { _rsp_offset--; popl (r); assert(_rsp_offset >= 0, "stack offset underflow"); }
+ // Seems to always be in wordSize
+ void push_addr (Address a) { _rsp_offset++; pushptr(a); }
+ void push_reg (Register r) { _rsp_offset++; push(r); }
+ void pop_reg (Register r) { _rsp_offset--; pop(r); assert(_rsp_offset >= 0, "stack offset underflow"); }
void dec_stack (int nof_words) {
_rsp_offset -= nof_words;
assert(_rsp_offset >= 0, "stack offset underflow");
- addl(rsp, wordSize * nof_words);
+ addptr(rsp, wordSize * nof_words);
}
void dec_stack_after_call (int nof_words) {
diff --git a/hotspot/src/cpu/x86/vm/c1_Runtime1_x86.cpp b/hotspot/src/cpu/x86/vm/c1_Runtime1_x86.cpp
index be73c79365b..01a232149c7 100644
--- a/hotspot/src/cpu/x86/vm/c1_Runtime1_x86.cpp
+++ b/hotspot/src/cpu/x86/vm/c1_Runtime1_x86.cpp
@@ -30,52 +30,58 @@
int StubAssembler::call_RT(Register oop_result1, Register oop_result2, address entry, int args_size) {
// setup registers
- const Register thread = rdi; // is callee-saved register (Visual C++ calling conventions)
+ const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread); // is callee-saved register (Visual C++ calling conventions)
assert(!(oop_result1->is_valid() || oop_result2->is_valid()) || oop_result1 != oop_result2, "registers must be different");
assert(oop_result1 != thread && oop_result2 != thread, "registers must be different");
assert(args_size >= 0, "illegal args_size");
+#ifdef _LP64
+ mov(c_rarg0, thread);
+ set_num_rt_args(0); // Nothing on stack
+#else
set_num_rt_args(1 + args_size);
// push java thread (becomes first argument of C function)
get_thread(thread);
- pushl(thread);
+ push(thread);
+#endif // _LP64
set_last_Java_frame(thread, noreg, rbp, NULL);
+
// do the call
call(RuntimeAddress(entry));
int call_offset = offset();
// verify callee-saved register
#ifdef ASSERT
guarantee(thread != rax, "change this code");
- pushl(rax);
+ push(rax);
{ Label L;
get_thread(rax);
- cmpl(thread, rax);
+ cmpptr(thread, rax);
jcc(Assembler::equal, L);
int3();
stop("StubAssembler::call_RT: rdi not callee saved?");
bind(L);
}
- popl(rax);
+ pop(rax);
#endif
reset_last_Java_frame(thread, true, false);
// discard thread and arguments
- addl(rsp, (1 + args_size)*BytesPerWord);
+ NOT_LP64(addptr(rsp, num_rt_args()*BytesPerWord));
// check for pending exceptions
{ Label L;
- cmpl(Address(thread, Thread::pending_exception_offset()), NULL_WORD);
+ cmpptr(Address(thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
jcc(Assembler::equal, L);
// exception pending => remove activation and forward to exception handler
- movl(rax, Address(thread, Thread::pending_exception_offset()));
+ movptr(rax, Address(thread, Thread::pending_exception_offset()));
// make sure that the vm_results are cleared
if (oop_result1->is_valid()) {
- movl(Address(thread, JavaThread::vm_result_offset()), NULL_WORD);
+ movptr(Address(thread, JavaThread::vm_result_offset()), (int32_t)NULL_WORD);
}
if (oop_result2->is_valid()) {
- movl(Address(thread, JavaThread::vm_result_2_offset()), NULL_WORD);
+ movptr(Address(thread, JavaThread::vm_result_2_offset()), (int32_t)NULL_WORD);
}
if (frame_size() == no_frame_size) {
leave();
@@ -89,13 +95,13 @@ int StubAssembler::call_RT(Register oop_result1, Register oop_result2, address e
}
// get oop results if there are any and reset the values in the thread
if (oop_result1->is_valid()) {
- movl(oop_result1, Address(thread, JavaThread::vm_result_offset()));
- movl(Address(thread, JavaThread::vm_result_offset()), NULL_WORD);
+ movptr(oop_result1, Address(thread, JavaThread::vm_result_offset()));
+ movptr(Address(thread, JavaThread::vm_result_offset()), (int32_t)NULL_WORD);
verify_oop(oop_result1);
}
if (oop_result2->is_valid()) {
- movl(oop_result2, Address(thread, JavaThread::vm_result_2_offset()));
- movl(Address(thread, JavaThread::vm_result_2_offset()), NULL_WORD);
+ movptr(oop_result2, Address(thread, JavaThread::vm_result_2_offset()));
+ movptr(Address(thread, JavaThread::vm_result_2_offset()), (int32_t)NULL_WORD);
verify_oop(oop_result2);
}
return call_offset;
@@ -103,22 +109,58 @@ int StubAssembler::call_RT(Register oop_result1, Register oop_result2, address e
int StubAssembler::call_RT(Register oop_result1, Register oop_result2, address entry, Register arg1) {
- pushl(arg1);
+#ifdef _LP64
+ mov(c_rarg1, arg1);
+#else
+ push(arg1);
+#endif // _LP64
return call_RT(oop_result1, oop_result2, entry, 1);
}
int StubAssembler::call_RT(Register oop_result1, Register oop_result2, address entry, Register arg1, Register arg2) {
- pushl(arg2);
- pushl(arg1);
+#ifdef _LP64
+ if (c_rarg1 == arg2) {
+ if (c_rarg2 == arg1) {
+ xchgq(arg1, arg2);
+ } else {
+ mov(c_rarg2, arg2);
+ mov(c_rarg1, arg1);
+ }
+ } else {
+ mov(c_rarg1, arg1);
+ mov(c_rarg2, arg2);
+ }
+#else
+ push(arg2);
+ push(arg1);
+#endif // _LP64
return call_RT(oop_result1, oop_result2, entry, 2);
}
int StubAssembler::call_RT(Register oop_result1, Register oop_result2, address entry, Register arg1, Register arg2, Register arg3) {
- pushl(arg3);
- pushl(arg2);
- pushl(arg1);
+#ifdef _LP64
+ // if there is any conflict use the stack
+ if (arg1 == c_rarg2 || arg1 == c_rarg3 ||
+ arg2 == c_rarg1 || arg1 == c_rarg3 ||
+ arg3 == c_rarg1 || arg1 == c_rarg2) {
+ push(arg3);
+ push(arg2);
+ push(arg1);
+ pop(c_rarg1);
+ pop(c_rarg2);
+ pop(c_rarg3);
+ } else {
+ mov(c_rarg1, arg1);
+ mov(c_rarg2, arg2);
+ mov(c_rarg3, arg3);
+ }
+#else
+ push(arg3);
+ push(arg2);
+ push(arg1);
+#endif // _LP64
return call_RT(oop_result1, oop_result2, entry, 3);
}
@@ -154,7 +196,7 @@ void StubFrame::load_argument(int offset_in_words, Register reg) {
// + 3: argument with offset 1
// + 4: ...
- __ movl(reg, Address(rbp, (offset_in_words + 2) * BytesPerWord));
+ __ movptr(reg, Address(rbp, (offset_in_words + 2) * BytesPerWord));
}
@@ -170,8 +212,8 @@ StubFrame::~StubFrame() {
#define __ sasm->
-const int float_regs_as_doubles_size_in_words = 16;
-const int xmm_regs_as_doubles_size_in_words = 16;
+const int float_regs_as_doubles_size_in_slots = pd_nof_fpu_regs_frame_map * 2;
+const int xmm_regs_as_doubles_size_in_slots = FrameMap::nof_xmm_regs * 2;
// Stack layout for saving/restoring all the registers needed during a runtime
// call (this includes deoptimization)
@@ -180,29 +222,61 @@ const int xmm_regs_as_doubles_size_in_words = 16;
// but the code in save_live_registers will take the argument count into
// account.
//
+#ifdef _LP64
+ #define SLOT2(x) x,
+ #define SLOT_PER_WORD 2
+#else
+ #define SLOT2(x)
+ #define SLOT_PER_WORD 1
+#endif // _LP64
+
enum reg_save_layout {
- dummy1,
- dummy2,
+ // 64bit needs to keep stack 16 byte aligned. So we add some alignment dummies to make that
+ // happen and will assert if the stack size we create is misaligned
+#ifdef _LP64
+ align_dummy_0, align_dummy_1,
+#endif // _LP64
+ dummy1, SLOT2(dummy1H) // 0, 4
+ dummy2, SLOT2(dummy2H) // 8, 12
// Two temps to be used as needed by users of save/restore callee registers
- temp_2_off,
- temp_1_off,
- xmm_regs_as_doubles_off,
- float_regs_as_doubles_off = xmm_regs_as_doubles_off + xmm_regs_as_doubles_size_in_words,
- fpu_state_off = float_regs_as_doubles_off + float_regs_as_doubles_size_in_words,
- fpu_state_end_off = fpu_state_off + FPUStateSizeInWords,
- marker = fpu_state_end_off,
- extra_space_offset,
+ temp_2_off, SLOT2(temp_2H_off) // 16, 20
+ temp_1_off, SLOT2(temp_1H_off) // 24, 28
+ xmm_regs_as_doubles_off, // 32
+ float_regs_as_doubles_off = xmm_regs_as_doubles_off + xmm_regs_as_doubles_size_in_slots, // 160
+ fpu_state_off = float_regs_as_doubles_off + float_regs_as_doubles_size_in_slots, // 224
+ // fpu_state_end_off is exclusive
+ fpu_state_end_off = fpu_state_off + (FPUStateSizeInWords / SLOT_PER_WORD), // 352
+ marker = fpu_state_end_off, SLOT2(markerH) // 352, 356
+ extra_space_offset, // 360
+#ifdef _LP64
+ r15_off = extra_space_offset, r15H_off, // 360, 364
+ r14_off, r14H_off, // 368, 372
+ r13_off, r13H_off, // 376, 380
+ r12_off, r12H_off, // 384, 388
+ r11_off, r11H_off, // 392, 396
+ r10_off, r10H_off, // 400, 404
+ r9_off, r9H_off, // 408, 412
+ r8_off, r8H_off, // 416, 420
+ rdi_off, rdiH_off, // 424, 428
+#else
rdi_off = extra_space_offset,
- rsi_off,
- rbp_off,
- rsp_off,
- rbx_off,
- rdx_off,
- rcx_off,
- rax_off,
- saved_rbp_off,
- return_off,
- reg_save_frame_size, // As noted: neglects any parameters to runtime
+#endif // _LP64
+ rsi_off, SLOT2(rsiH_off) // 432, 436
+ rbp_off, SLOT2(rbpH_off) // 440, 444
+ rsp_off, SLOT2(rspH_off) // 448, 452
+ rbx_off, SLOT2(rbxH_off) // 456, 460
+ rdx_off, SLOT2(rdxH_off) // 464, 468
+ rcx_off, SLOT2(rcxH_off) // 472, 476
+ rax_off, SLOT2(raxH_off) // 480, 484
+ saved_rbp_off, SLOT2(saved_rbpH_off) // 488, 492
+ return_off, SLOT2(returnH_off) // 496, 500
+ reg_save_frame_size, // As noted: neglects any parameters to runtime // 504
+
+#ifdef _WIN64
+ c_rarg0_off = rcx_off,
+#else
+ c_rarg0_off = rdi_off,
+#endif // WIN64
// equates
@@ -229,18 +303,49 @@ enum reg_save_layout {
static OopMap* generate_oop_map(StubAssembler* sasm, int num_rt_args,
bool save_fpu_registers = true) {
- int frame_size = reg_save_frame_size + num_rt_args; // args + thread
- sasm->set_frame_size(frame_size);
+
+ // In 64bit all the args are in regs so there are no additional stack slots
+ LP64_ONLY(num_rt_args = 0);
+ LP64_ONLY(assert((reg_save_frame_size * VMRegImpl::stack_slot_size) % 16 == 0, "must be 16 byte aligned");)
+ int frame_size_in_slots = reg_save_frame_size + num_rt_args; // args + thread
+ sasm->set_frame_size(frame_size_in_slots / VMRegImpl::slots_per_word );
// record saved value locations in an OopMap
// locations are offsets from sp after runtime call; num_rt_args is number of arguments in call, including thread
- OopMap* map = new OopMap(frame_size, 0);
+ OopMap* map = new OopMap(frame_size_in_slots, 0);
map->set_callee_saved(VMRegImpl::stack2reg(rax_off + num_rt_args), rax->as_VMReg());
map->set_callee_saved(VMRegImpl::stack2reg(rcx_off + num_rt_args), rcx->as_VMReg());
map->set_callee_saved(VMRegImpl::stack2reg(rdx_off + num_rt_args), rdx->as_VMReg());
map->set_callee_saved(VMRegImpl::stack2reg(rbx_off + num_rt_args), rbx->as_VMReg());
map->set_callee_saved(VMRegImpl::stack2reg(rsi_off + num_rt_args), rsi->as_VMReg());
map->set_callee_saved(VMRegImpl::stack2reg(rdi_off + num_rt_args), rdi->as_VMReg());
+#ifdef _LP64
+ map->set_callee_saved(VMRegImpl::stack2reg(r8_off + num_rt_args), r8->as_VMReg());
+ map->set_callee_saved(VMRegImpl::stack2reg(r9_off + num_rt_args), r9->as_VMReg());
+ map->set_callee_saved(VMRegImpl::stack2reg(r10_off + num_rt_args), r10->as_VMReg());
+ map->set_callee_saved(VMRegImpl::stack2reg(r11_off + num_rt_args), r11->as_VMReg());
+ map->set_callee_saved(VMRegImpl::stack2reg(r12_off + num_rt_args), r12->as_VMReg());
+ map->set_callee_saved(VMRegImpl::stack2reg(r13_off + num_rt_args), r13->as_VMReg());
+ map->set_callee_saved(VMRegImpl::stack2reg(r14_off + num_rt_args), r14->as_VMReg());
+ map->set_callee_saved(VMRegImpl::stack2reg(r15_off + num_rt_args), r15->as_VMReg());
+
+ // This is stupid but needed.
+ map->set_callee_saved(VMRegImpl::stack2reg(raxH_off + num_rt_args), rax->as_VMReg()->next());
+ map->set_callee_saved(VMRegImpl::stack2reg(rcxH_off + num_rt_args), rcx->as_VMReg()->next());
+ map->set_callee_saved(VMRegImpl::stack2reg(rdxH_off + num_rt_args), rdx->as_VMReg()->next());
+ map->set_callee_saved(VMRegImpl::stack2reg(rbxH_off + num_rt_args), rbx->as_VMReg()->next());
+ map->set_callee_saved(VMRegImpl::stack2reg(rsiH_off + num_rt_args), rsi->as_VMReg()->next());
+ map->set_callee_saved(VMRegImpl::stack2reg(rdiH_off + num_rt_args), rdi->as_VMReg()->next());
+
+ map->set_callee_saved(VMRegImpl::stack2reg(r8H_off + num_rt_args), r8->as_VMReg()->next());
+ map->set_callee_saved(VMRegImpl::stack2reg(r9H_off + num_rt_args), r9->as_VMReg()->next());
+ map->set_callee_saved(VMRegImpl::stack2reg(r10H_off + num_rt_args), r10->as_VMReg()->next());
+ map->set_callee_saved(VMRegImpl::stack2reg(r11H_off + num_rt_args), r11->as_VMReg()->next());
+ map->set_callee_saved(VMRegImpl::stack2reg(r12H_off + num_rt_args), r12->as_VMReg()->next());
+ map->set_callee_saved(VMRegImpl::stack2reg(r13H_off + num_rt_args), r13->as_VMReg()->next());
+ map->set_callee_saved(VMRegImpl::stack2reg(r14H_off + num_rt_args), r14->as_VMReg()->next());
+ map->set_callee_saved(VMRegImpl::stack2reg(r15H_off + num_rt_args), r15->as_VMReg()->next());
+#endif // _LP64
if (save_fpu_registers) {
if (UseSSE < 2) {
@@ -288,30 +393,31 @@ static OopMap* save_live_registers(StubAssembler* sasm, int num_rt_args,
bool save_fpu_registers = true) {
__ block_comment("save_live_registers");
- int frame_size = reg_save_frame_size + num_rt_args; // args + thread
+ // 64bit passes the args in regs to the c++ runtime
+ int frame_size_in_slots = reg_save_frame_size NOT_LP64(+ num_rt_args); // args + thread
// frame_size = round_to(frame_size, 4);
- sasm->set_frame_size(frame_size);
+ sasm->set_frame_size(frame_size_in_slots / VMRegImpl::slots_per_word );
- __ pushad(); // integer registers
+ __ pusha(); // integer registers
// assert(float_regs_as_doubles_off % 2 == 0, "misaligned offset");
// assert(xmm_regs_as_doubles_off % 2 == 0, "misaligned offset");
- __ subl(rsp, extra_space_offset * wordSize);
+ __ subptr(rsp, extra_space_offset * VMRegImpl::stack_slot_size);
#ifdef ASSERT
- __ movl(Address(rsp, marker * wordSize), 0xfeedbeef);
+ __ movptr(Address(rsp, marker * VMRegImpl::stack_slot_size), (int32_t)0xfeedbeef);
#endif
if (save_fpu_registers) {
if (UseSSE < 2) {
// save FPU stack
- __ fnsave(Address(rsp, fpu_state_off * wordSize));
+ __ fnsave(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size));
__ fwait();
#ifdef ASSERT
Label ok;
- __ cmpw(Address(rsp, fpu_state_off * wordSize), StubRoutines::fpu_cntrl_wrd_std());
+ __ cmpw(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size), StubRoutines::fpu_cntrl_wrd_std());
__ jccb(Assembler::equal, ok);
__ stop("corrupted control word detected");
__ bind(ok);
@@ -321,18 +427,18 @@ static OopMap* save_live_registers(StubAssembler* sasm, int num_rt_args,
// since fstp_d can cause FPU stack underflow exceptions. Write it
// into the on stack copy and then reload that to make sure that the
// current and future values are correct.
- __ movw(Address(rsp, fpu_state_off * wordSize), StubRoutines::fpu_cntrl_wrd_std());
- __ frstor(Address(rsp, fpu_state_off * wordSize));
+ __ movw(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size), StubRoutines::fpu_cntrl_wrd_std());
+ __ frstor(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size));
// Save the FPU registers in de-opt-able form
- __ fstp_d(Address(rsp, float_regs_as_doubles_off * BytesPerWord + 0));
- __ fstp_d(Address(rsp, float_regs_as_doubles_off * BytesPerWord + 8));
- __ fstp_d(Address(rsp, float_regs_as_doubles_off * BytesPerWord + 16));
- __ fstp_d(Address(rsp, float_regs_as_doubles_off * BytesPerWord + 24));
- __ fstp_d(Address(rsp, float_regs_as_doubles_off * BytesPerWord + 32));
- __ fstp_d(Address(rsp, float_regs_as_doubles_off * BytesPerWord + 40));
- __ fstp_d(Address(rsp, float_regs_as_doubles_off * BytesPerWord + 48));
- __ fstp_d(Address(rsp, float_regs_as_doubles_off * BytesPerWord + 56));
+ __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 0));
+ __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 8));
+ __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 16));
+ __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 24));
+ __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 32));
+ __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 40));
+ __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 48));
+ __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 56));
}
if (UseSSE >= 2) {
@@ -341,24 +447,34 @@ static OopMap* save_live_registers(StubAssembler* sasm, int num_rt_args,
// so always save them as doubles.
// note that float values are _not_ converted automatically, so for float values
// the second word contains only garbage data.
- __ movdbl(Address(rsp, xmm_regs_as_doubles_off * wordSize + 0), xmm0);
- __ movdbl(Address(rsp, xmm_regs_as_doubles_off * wordSize + 8), xmm1);
- __ movdbl(Address(rsp, xmm_regs_as_doubles_off * wordSize + 16), xmm2);
- __ movdbl(Address(rsp, xmm_regs_as_doubles_off * wordSize + 24), xmm3);
- __ movdbl(Address(rsp, xmm_regs_as_doubles_off * wordSize + 32), xmm4);
- __ movdbl(Address(rsp, xmm_regs_as_doubles_off * wordSize + 40), xmm5);
- __ movdbl(Address(rsp, xmm_regs_as_doubles_off * wordSize + 48), xmm6);
- __ movdbl(Address(rsp, xmm_regs_as_doubles_off * wordSize + 56), xmm7);
+ __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 0), xmm0);
+ __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 8), xmm1);
+ __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 16), xmm2);
+ __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 24), xmm3);
+ __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 32), xmm4);
+ __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 40), xmm5);
+ __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 48), xmm6);
+ __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 56), xmm7);
+#ifdef _LP64
+ __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 64), xmm8);
+ __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 72), xmm9);
+ __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 80), xmm10);
+ __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 88), xmm11);
+ __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 96), xmm12);
+ __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 104), xmm13);
+ __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 112), xmm14);
+ __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 120), xmm15);
+#endif // _LP64
} else if (UseSSE == 1) {
// save XMM registers as float because double not supported without SSE2
- __ movflt(Address(rsp, xmm_regs_as_doubles_off * wordSize + 0), xmm0);
- __ movflt(Address(rsp, xmm_regs_as_doubles_off * wordSize + 8), xmm1);
- __ movflt(Address(rsp, xmm_regs_as_doubles_off * wordSize + 16), xmm2);
- __ movflt(Address(rsp, xmm_regs_as_doubles_off * wordSize + 24), xmm3);
- __ movflt(Address(rsp, xmm_regs_as_doubles_off * wordSize + 32), xmm4);
- __ movflt(Address(rsp, xmm_regs_as_doubles_off * wordSize + 40), xmm5);
- __ movflt(Address(rsp, xmm_regs_as_doubles_off * wordSize + 48), xmm6);
- __ movflt(Address(rsp, xmm_regs_as_doubles_off * wordSize + 56), xmm7);
+ __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 0), xmm0);
+ __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 8), xmm1);
+ __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 16), xmm2);
+ __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 24), xmm3);
+ __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 32), xmm4);
+ __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 40), xmm5);
+ __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 48), xmm6);
+ __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 56), xmm7);
}
}
@@ -373,28 +489,38 @@ static void restore_fpu(StubAssembler* sasm, bool restore_fpu_registers = true)
if (restore_fpu_registers) {
if (UseSSE >= 2) {
// restore XMM registers
- __ movdbl(xmm0, Address(rsp, xmm_regs_as_doubles_off * wordSize + 0));
- __ movdbl(xmm1, Address(rsp, xmm_regs_as_doubles_off * wordSize + 8));
- __ movdbl(xmm2, Address(rsp, xmm_regs_as_doubles_off * wordSize + 16));
- __ movdbl(xmm3, Address(rsp, xmm_regs_as_doubles_off * wordSize + 24));
- __ movdbl(xmm4, Address(rsp, xmm_regs_as_doubles_off * wordSize + 32));
- __ movdbl(xmm5, Address(rsp, xmm_regs_as_doubles_off * wordSize + 40));
- __ movdbl(xmm6, Address(rsp, xmm_regs_as_doubles_off * wordSize + 48));
- __ movdbl(xmm7, Address(rsp, xmm_regs_as_doubles_off * wordSize + 56));
+ __ movdbl(xmm0, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 0));
+ __ movdbl(xmm1, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 8));
+ __ movdbl(xmm2, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 16));
+ __ movdbl(xmm3, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 24));
+ __ movdbl(xmm4, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 32));
+ __ movdbl(xmm5, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 40));
+ __ movdbl(xmm6, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 48));
+ __ movdbl(xmm7, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 56));
+#ifdef _LP64
+ __ movdbl(xmm8, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 64));
+ __ movdbl(xmm9, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 72));
+ __ movdbl(xmm10, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 80));
+ __ movdbl(xmm11, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 88));
+ __ movdbl(xmm12, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 96));
+ __ movdbl(xmm13, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 104));
+ __ movdbl(xmm14, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 112));
+ __ movdbl(xmm15, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 120));
+#endif // _LP64
} else if (UseSSE == 1) {
// restore XMM registers
- __ movflt(xmm0, Address(rsp, xmm_regs_as_doubles_off * wordSize + 0));
- __ movflt(xmm1, Address(rsp, xmm_regs_as_doubles_off * wordSize + 8));
- __ movflt(xmm2, Address(rsp, xmm_regs_as_doubles_off * wordSize + 16));
- __ movflt(xmm3, Address(rsp, xmm_regs_as_doubles_off * wordSize + 24));
- __ movflt(xmm4, Address(rsp, xmm_regs_as_doubles_off * wordSize + 32));
- __ movflt(xmm5, Address(rsp, xmm_regs_as_doubles_off * wordSize + 40));
- __ movflt(xmm6, Address(rsp, xmm_regs_as_doubles_off * wordSize + 48));
- __ movflt(xmm7, Address(rsp, xmm_regs_as_doubles_off * wordSize + 56));
+ __ movflt(xmm0, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 0));
+ __ movflt(xmm1, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 8));
+ __ movflt(xmm2, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 16));
+ __ movflt(xmm3, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 24));
+ __ movflt(xmm4, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 32));
+ __ movflt(xmm5, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 40));
+ __ movflt(xmm6, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 48));
+ __ movflt(xmm7, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 56));
}
if (UseSSE < 2) {
- __ frstor(Address(rsp, fpu_state_off * wordSize));
+ __ frstor(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size));
} else {
// check that FPU stack is really empty
__ verify_FPU(0, "restore_live_registers");
@@ -408,14 +534,14 @@ static void restore_fpu(StubAssembler* sasm, bool restore_fpu_registers = true)
#ifdef ASSERT
{
Label ok;
- __ cmpl(Address(rsp, marker * wordSize), 0xfeedbeef);
+ __ cmpptr(Address(rsp, marker * VMRegImpl::stack_slot_size), (int32_t)0xfeedbeef);
__ jcc(Assembler::equal, ok);
__ stop("bad offsets in frame");
__ bind(ok);
}
-#endif
+#endif // ASSERT
- __ addl(rsp, extra_space_offset * wordSize);
+ __ addptr(rsp, extra_space_offset * VMRegImpl::stack_slot_size);
}
@@ -423,7 +549,7 @@ static void restore_live_registers(StubAssembler* sasm, bool restore_fpu_registe
__ block_comment("restore_live_registers");
restore_fpu(sasm, restore_fpu_registers);
- __ popad();
+ __ popa();
}
@@ -432,14 +558,35 @@ static void restore_live_registers_except_rax(StubAssembler* sasm, bool restore_
restore_fpu(sasm, restore_fpu_registers);
- __ popl(rdi);
- __ popl(rsi);
- __ popl(rbp);
- __ popl(rbx); // skip this value
- __ popl(rbx);
- __ popl(rdx);
- __ popl(rcx);
- __ addl(rsp, 4);
+#ifdef _LP64
+ __ movptr(r15, Address(rsp, 0));
+ __ movptr(r14, Address(rsp, wordSize));
+ __ movptr(r13, Address(rsp, 2 * wordSize));
+ __ movptr(r12, Address(rsp, 3 * wordSize));
+ __ movptr(r11, Address(rsp, 4 * wordSize));
+ __ movptr(r10, Address(rsp, 5 * wordSize));
+ __ movptr(r9, Address(rsp, 6 * wordSize));
+ __ movptr(r8, Address(rsp, 7 * wordSize));
+ __ movptr(rdi, Address(rsp, 8 * wordSize));
+ __ movptr(rsi, Address(rsp, 9 * wordSize));
+ __ movptr(rbp, Address(rsp, 10 * wordSize));
+ // skip rsp
+ __ movptr(rbx, Address(rsp, 12 * wordSize));
+ __ movptr(rdx, Address(rsp, 13 * wordSize));
+ __ movptr(rcx, Address(rsp, 14 * wordSize));
+
+ __ addptr(rsp, 16 * wordSize);
+#else
+
+ __ pop(rdi);
+ __ pop(rsi);
+ __ pop(rbp);
+ __ pop(rbx); // skip this value
+ __ pop(rbx);
+ __ pop(rdx);
+ __ pop(rcx);
+ __ addptr(rsp, BytesPerWord);
+#endif // _LP64
}
@@ -465,10 +612,13 @@ OopMapSet* Runtime1::generate_exception_throw(StubAssembler* sasm, address targe
// load argument for exception that is passed as an argument into the stub
if (has_argument) {
- __ movl(temp_reg, Address(rbp, 2*BytesPerWord));
- __ pushl(temp_reg);
+#ifdef _LP64
+ __ movptr(c_rarg1, Address(rbp, 2*BytesPerWord));
+#else
+ __ movptr(temp_reg, Address(rbp, 2*BytesPerWord));
+ __ push(temp_reg);
+#endif // _LP64
}
-
int call_offset = __ call_RT(noreg, noreg, target, num_rt_args - 1);
OopMapSet* oop_maps = new OopMapSet();
@@ -486,7 +636,7 @@ void Runtime1::generate_handle_exception(StubAssembler *sasm, OopMapSet* oop_map
const Register exception_pc = rdx;
// other registers used in this stub
const Register real_return_addr = rbx;
- const Register thread = rdi;
+ const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread);
__ block_comment("generate_handle_exception");
@@ -503,19 +653,19 @@ void Runtime1::generate_handle_exception(StubAssembler *sasm, OopMapSet* oop_map
__ verify_not_null_oop(exception_oop);
// load address of JavaThread object for thread-local data
- __ get_thread(thread);
+ NOT_LP64(__ get_thread(thread);)
#ifdef ASSERT
// check that fields in JavaThread for exception oop and issuing pc are
// empty before writing to them
Label oop_empty;
- __ cmpl(Address(thread, JavaThread::exception_oop_offset()), 0);
+ __ cmpptr(Address(thread, JavaThread::exception_oop_offset()), (int32_t) NULL_WORD);
__ jcc(Assembler::equal, oop_empty);
__ stop("exception oop already set");
__ bind(oop_empty);
Label pc_empty;
- __ cmpl(Address(thread, JavaThread::exception_pc_offset()), 0);
+ __ cmpptr(Address(thread, JavaThread::exception_pc_offset()), 0);
__ jcc(Assembler::equal, pc_empty);
__ stop("exception pc already set");
__ bind(pc_empty);
@@ -523,15 +673,15 @@ void Runtime1::generate_handle_exception(StubAssembler *sasm, OopMapSet* oop_map
// save exception oop and issuing pc into JavaThread
// (exception handler will load it from here)
- __ movl(Address(thread, JavaThread::exception_oop_offset()), exception_oop);
- __ movl(Address(thread, JavaThread::exception_pc_offset()), exception_pc);
+ __ movptr(Address(thread, JavaThread::exception_oop_offset()), exception_oop);
+ __ movptr(Address(thread, JavaThread::exception_pc_offset()), exception_pc);
// save real return address (pc that called this stub)
- __ movl(real_return_addr, Address(rbp, 1*BytesPerWord));
- __ movl(Address(rsp, temp_1_off * BytesPerWord), real_return_addr);
+ __ movptr(real_return_addr, Address(rbp, 1*BytesPerWord));
+ __ movptr(Address(rsp, temp_1_off * VMRegImpl::stack_slot_size), real_return_addr);
// patch throwing pc into return address (has bci & oop map)
- __ movl(Address(rbp, 1*BytesPerWord), exception_pc);
+ __ movptr(Address(rbp, 1*BytesPerWord), exception_pc);
// compute the exception handler.
// the exception oop and the throwing pc are read from the fields in JavaThread
@@ -548,12 +698,12 @@ void Runtime1::generate_handle_exception(StubAssembler *sasm, OopMapSet* oop_map
// Do we have an exception handler in the nmethod?
Label no_handler;
Label done;
- __ testl(rax, rax);
+ __ testptr(rax, rax);
__ jcc(Assembler::zero, no_handler);
// exception handler found
// patch the return address -> the stub will directly return to the exception handler
- __ movl(Address(rbp, 1*BytesPerWord), rax);
+ __ movptr(Address(rbp, 1*BytesPerWord), rax);
// restore registers
restore_live_registers(sasm, save_fpu_registers);
@@ -568,18 +718,18 @@ void Runtime1::generate_handle_exception(StubAssembler *sasm, OopMapSet* oop_map
// there is no need to restore the registers
// restore the real return address that was saved before the RT-call
- __ movl(real_return_addr, Address(rsp, temp_1_off * BytesPerWord));
- __ movl(Address(rbp, 1*BytesPerWord), real_return_addr);
+ __ movptr(real_return_addr, Address(rsp, temp_1_off * VMRegImpl::stack_slot_size));
+ __ movptr(Address(rbp, 1*BytesPerWord), real_return_addr);
// load address of JavaThread object for thread-local data
- __ get_thread(thread);
+ NOT_LP64(__ get_thread(thread);)
// restore exception oop into rax, (convention for unwind code)
- __ movl(exception_oop, Address(thread, JavaThread::exception_oop_offset()));
+ __ movptr(exception_oop, Address(thread, JavaThread::exception_oop_offset()));
// clear exception fields in JavaThread because they are no longer needed
// (fields must be cleared because they are processed by GC otherwise)
- __ movl(Address(thread, JavaThread::exception_oop_offset()), NULL_WORD);
- __ movl(Address(thread, JavaThread::exception_pc_offset()), NULL_WORD);
+ __ movptr(Address(thread, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD);
+ __ movptr(Address(thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD);
// pop the stub frame off
__ leave();
@@ -595,22 +745,22 @@ void Runtime1::generate_unwind_exception(StubAssembler *sasm) {
// other registers used in this stub
const Register exception_pc = rdx;
const Register handler_addr = rbx;
- const Register thread = rdi;
+ const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread);
// verify that only rax, is valid at this time
__ invalidate_registers(false, true, true, true, true, true);
#ifdef ASSERT
// check that fields in JavaThread for exception oop and issuing pc are empty
- __ get_thread(thread);
+ NOT_LP64(__ get_thread(thread);)
Label oop_empty;
- __ cmpl(Address(thread, JavaThread::exception_oop_offset()), 0);
+ __ cmpptr(Address(thread, JavaThread::exception_oop_offset()), 0);
__ jcc(Assembler::equal, oop_empty);
__ stop("exception oop must be empty");
__ bind(oop_empty);
Label pc_empty;
- __ cmpl(Address(thread, JavaThread::exception_pc_offset()), 0);
+ __ cmpptr(Address(thread, JavaThread::exception_pc_offset()), 0);
__ jcc(Assembler::equal, pc_empty);
__ stop("exception pc must be empty");
__ bind(pc_empty);
@@ -622,12 +772,12 @@ void Runtime1::generate_unwind_exception(StubAssembler *sasm) {
// leave activation of nmethod
__ leave();
// store return address (is on top of stack after leave)
- __ movl(exception_pc, Address(rsp, 0));
+ __ movptr(exception_pc, Address(rsp, 0));
__ verify_oop(exception_oop);
// save exception oop from rax, to stack before call
- __ pushl(exception_oop);
+ __ push(exception_oop);
// search the exception handler address of the caller (using the return address)
__ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::exception_handler_for_return_address), exception_pc);
@@ -637,17 +787,17 @@ void Runtime1::generate_unwind_exception(StubAssembler *sasm) {
__ invalidate_registers(false, true, true, true, true, true);
// move result of call into correct register
- __ movl(handler_addr, rax);
+ __ movptr(handler_addr, rax);
// restore exception oop in rax, (required convention of exception handler)
- __ popl(exception_oop);
+ __ pop(exception_oop);
__ verify_oop(exception_oop);
// get throwing pc (= return address).
// rdx has been destroyed by the call, so it must be set again
// the pop is also necessary to simulate the effect of a ret(0)
- __ popl(exception_pc);
+ __ pop(exception_pc);
// verify that that there is really a valid exception in rax,
__ verify_not_null_oop(exception_oop);
@@ -677,12 +827,18 @@ OopMapSet* Runtime1::generate_patching(StubAssembler* sasm, address target) {
OopMap* oop_map = save_live_registers(sasm, num_rt_args);
- __ pushl(rax); // push dummy
+#ifdef _LP64
+ const Register thread = r15_thread;
+ // No need to worry about dummy
+ __ mov(c_rarg0, thread);
+#else
+ __ push(rax); // push dummy
const Register thread = rdi; // is callee-saved register (Visual C++ calling conventions)
// push java thread (becomes first argument of C function)
__ get_thread(thread);
- __ pushl(thread);
+ __ push(thread);
+#endif // _LP64
__ set_last_Java_frame(thread, noreg, rbp, NULL);
// do the call
__ call(RuntimeAddress(target));
@@ -691,27 +847,29 @@ OopMapSet* Runtime1::generate_patching(StubAssembler* sasm, address target) {
// verify callee-saved register
#ifdef ASSERT
guarantee(thread != rax, "change this code");
- __ pushl(rax);
+ __ push(rax);
{ Label L;
__ get_thread(rax);
- __ cmpl(thread, rax);
+ __ cmpptr(thread, rax);
__ jcc(Assembler::equal, L);
- __ stop("StubAssembler::call_RT: rdi not callee saved?");
+ __ stop("StubAssembler::call_RT: rdi/r15 not callee saved?");
__ bind(L);
}
- __ popl(rax);
+ __ pop(rax);
#endif
__ reset_last_Java_frame(thread, true, false);
- __ popl(rcx); // discard thread arg
- __ popl(rcx); // discard dummy
+#ifndef _LP64
+ __ pop(rcx); // discard thread arg
+ __ pop(rcx); // discard dummy
+#endif // _LP64
// check for pending exceptions
{ Label L;
- __ cmpl(Address(thread, Thread::pending_exception_offset()), NULL_WORD);
+ __ cmpptr(Address(thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
__ jcc(Assembler::equal, L);
// exception pending => remove activation and forward to exception handler
- __ testl(rax, rax); // have we deoptimized?
+ __ testptr(rax, rax); // have we deoptimized?
__ jump_cc(Assembler::equal,
RuntimeAddress(Runtime1::entry_for(Runtime1::forward_exception_id)));
@@ -719,38 +877,38 @@ OopMapSet* Runtime1::generate_patching(StubAssembler* sasm, address target) {
// JavaThread, so copy and clear pending exception.
// load and clear pending exception
- __ movl(rax, Address(thread, Thread::pending_exception_offset()));
- __ movl(Address(thread, Thread::pending_exception_offset()), NULL_WORD);
+ __ movptr(rax, Address(thread, Thread::pending_exception_offset()));
+ __ movptr(Address(thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
// check that there is really a valid exception
__ verify_not_null_oop(rax);
// load throwing pc: this is the return address of the stub
- __ movl(rdx, Address(rsp, return_off * BytesPerWord));
+ __ movptr(rdx, Address(rsp, return_off * VMRegImpl::stack_slot_size));
#ifdef ASSERT
// check that fields in JavaThread for exception oop and issuing pc are empty
Label oop_empty;
- __ cmpoop(Address(thread, JavaThread::exception_oop_offset()), 0);
+ __ cmpptr(Address(thread, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD);
__ jcc(Assembler::equal, oop_empty);
__ stop("exception oop must be empty");
__ bind(oop_empty);
Label pc_empty;
- __ cmpl(Address(thread, JavaThread::exception_pc_offset()), 0);
+ __ cmpptr(Address(thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD);
__ jcc(Assembler::equal, pc_empty);
__ stop("exception pc must be empty");
__ bind(pc_empty);
#endif
// store exception oop and throwing pc to JavaThread
- __ movl(Address(thread, JavaThread::exception_oop_offset()), rax);
- __ movl(Address(thread, JavaThread::exception_pc_offset()), rdx);
+ __ movptr(Address(thread, JavaThread::exception_oop_offset()), rax);
+ __ movptr(Address(thread, JavaThread::exception_pc_offset()), rdx);
restore_live_registers(sasm);
__ leave();
- __ addl(rsp, 4); // remove return address from stack
+ __ addptr(rsp, BytesPerWord); // remove return address from stack
// Forward the exception directly to deopt blob. We can blow no
// registers and must leave throwing pc on the stack. A patch may
@@ -767,7 +925,7 @@ OopMapSet* Runtime1::generate_patching(StubAssembler* sasm, address target) {
Label reexecuteEntry, cont;
- __ testl(rax, rax); // have we deoptimized?
+ __ testptr(rax, rax); // have we deoptimized?
__ jcc(Assembler::equal, cont); // no
// Will reexecute. Proper return address is already on the stack we just restore
@@ -806,21 +964,21 @@ OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
// dispatch to the handler if found. Otherwise unwind and
// dispatch to the callers exception handler.
- const Register thread = rdi;
+ const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread);
const Register exception_oop = rax;
const Register exception_pc = rdx;
// load pending exception oop into rax,
- __ movl(exception_oop, Address(thread, Thread::pending_exception_offset()));
+ __ movptr(exception_oop, Address(thread, Thread::pending_exception_offset()));
// clear pending exception
- __ movl(Address(thread, Thread::pending_exception_offset()), NULL_WORD);
+ __ movptr(Address(thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
// load issuing PC (the return address for this stub) into rdx
- __ movl(exception_pc, Address(rbp, 1*BytesPerWord));
+ __ movptr(exception_pc, Address(rbp, 1*BytesPerWord));
// make sure that the vm_results are cleared (may be unnecessary)
- __ movl(Address(thread, JavaThread::vm_result_offset()), NULL_WORD);
- __ movl(Address(thread, JavaThread::vm_result_2_offset()), NULL_WORD);
+ __ movptr(Address(thread, JavaThread::vm_result_offset()), (int32_t)NULL_WORD);
+ __ movptr(Address(thread, JavaThread::vm_result_2_offset()), (int32_t)NULL_WORD);
// verify that that there is really a valid exception in rax,
__ verify_not_null_oop(exception_oop);
@@ -857,8 +1015,8 @@ OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
Register t2 = rsi;
assert_different_registers(klass, obj, obj_size, t1, t2);
- __ pushl(rdi);
- __ pushl(rbx);
+ __ push(rdi);
+ __ push(rbx);
if (id == fast_new_instance_init_check_id) {
// make sure the klass is initialized
@@ -889,28 +1047,28 @@ OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
__ bind(retry_tlab);
- // get the instance size
+ // get the instance size (size is postive so movl is fine for 64bit)
__ movl(obj_size, Address(klass, klassOopDesc::header_size() * HeapWordSize + Klass::layout_helper_offset_in_bytes()));
__ tlab_allocate(obj, obj_size, 0, t1, t2, slow_path);
__ initialize_object(obj, klass, obj_size, 0, t1, t2);
__ verify_oop(obj);
- __ popl(rbx);
- __ popl(rdi);
+ __ pop(rbx);
+ __ pop(rdi);
__ ret(0);
__ bind(try_eden);
- // get the instance size
+ // get the instance size (size is postive so movl is fine for 64bit)
__ movl(obj_size, Address(klass, klassOopDesc::header_size() * HeapWordSize + Klass::layout_helper_offset_in_bytes()));
__ eden_allocate(obj, obj_size, 0, t1, slow_path);
__ initialize_object(obj, klass, obj_size, 0, t1, t2);
__ verify_oop(obj);
- __ popl(rbx);
- __ popl(rdi);
+ __ pop(rbx);
+ __ pop(rdi);
__ ret(0);
__ bind(slow_path);
- __ popl(rbx);
- __ popl(rdi);
+ __ pop(rbx);
+ __ pop(rdi);
}
__ enter();
@@ -996,15 +1154,17 @@ OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
__ bind(retry_tlab);
// get the allocation size: round_up(hdr + length << (layout_helper & 0x1F))
+ // since size is postive movl does right thing on 64bit
__ movl(t1, Address(klass, klassOopDesc::header_size() * HeapWordSize + Klass::layout_helper_offset_in_bytes()));
+ // since size is postive movl does right thing on 64bit
__ movl(arr_size, length);
assert(t1 == rcx, "fixed register usage");
- __ shll(arr_size /* by t1=rcx, mod 32 */);
- __ shrl(t1, Klass::_lh_header_size_shift);
- __ andl(t1, Klass::_lh_header_size_mask);
- __ addl(arr_size, t1);
- __ addl(arr_size, MinObjAlignmentInBytesMask); // align up
- __ andl(arr_size, ~MinObjAlignmentInBytesMask);
+ __ shlptr(arr_size /* by t1=rcx, mod 32 */);
+ __ shrptr(t1, Klass::_lh_header_size_shift);
+ __ andptr(t1, Klass::_lh_header_size_mask);
+ __ addptr(arr_size, t1);
+ __ addptr(arr_size, MinObjAlignmentInBytesMask); // align up
+ __ andptr(arr_size, ~MinObjAlignmentInBytesMask);
__ tlab_allocate(obj, arr_size, 0, t1, t2, slow_path); // preserves arr_size
@@ -1012,24 +1172,26 @@ OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
__ movb(t1, Address(klass, klassOopDesc::header_size() * HeapWordSize + Klass::layout_helper_offset_in_bytes() + (Klass::_lh_header_size_shift / BitsPerByte)));
assert(Klass::_lh_header_size_shift % BitsPerByte == 0, "bytewise");
assert(Klass::_lh_header_size_mask <= 0xFF, "bytewise");
- __ andl(t1, Klass::_lh_header_size_mask);
- __ subl(arr_size, t1); // body length
- __ addl(t1, obj); // body start
+ __ andptr(t1, Klass::_lh_header_size_mask);
+ __ subptr(arr_size, t1); // body length
+ __ addptr(t1, obj); // body start
__ initialize_body(t1, arr_size, 0, t2);
__ verify_oop(obj);
__ ret(0);
__ bind(try_eden);
// get the allocation size: round_up(hdr + length << (layout_helper & 0x1F))
+ // since size is postive movl does right thing on 64bit
__ movl(t1, Address(klass, klassOopDesc::header_size() * HeapWordSize + Klass::layout_helper_offset_in_bytes()));
+ // since size is postive movl does right thing on 64bit
__ movl(arr_size, length);
assert(t1 == rcx, "fixed register usage");
- __ shll(arr_size /* by t1=rcx, mod 32 */);
- __ shrl(t1, Klass::_lh_header_size_shift);
- __ andl(t1, Klass::_lh_header_size_mask);
- __ addl(arr_size, t1);
- __ addl(arr_size, MinObjAlignmentInBytesMask); // align up
- __ andl(arr_size, ~MinObjAlignmentInBytesMask);
+ __ shlptr(arr_size /* by t1=rcx, mod 32 */);
+ __ shrptr(t1, Klass::_lh_header_size_shift);
+ __ andptr(t1, Klass::_lh_header_size_mask);
+ __ addptr(arr_size, t1);
+ __ addptr(arr_size, MinObjAlignmentInBytesMask); // align up
+ __ andptr(arr_size, ~MinObjAlignmentInBytesMask);
__ eden_allocate(obj, arr_size, 0, t1, slow_path); // preserves arr_size
@@ -1037,9 +1199,9 @@ OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
__ movb(t1, Address(klass, klassOopDesc::header_size() * HeapWordSize + Klass::layout_helper_offset_in_bytes() + (Klass::_lh_header_size_shift / BitsPerByte)));
assert(Klass::_lh_header_size_shift % BitsPerByte == 0, "bytewise");
assert(Klass::_lh_header_size_mask <= 0xFF, "bytewise");
- __ andl(t1, Klass::_lh_header_size_mask);
- __ subl(arr_size, t1); // body length
- __ addl(t1, obj); // body start
+ __ andptr(t1, Klass::_lh_header_size_mask);
+ __ subptr(arr_size, t1); // body length
+ __ addptr(t1, obj); // body start
__ initialize_body(t1, arr_size, 0, t2);
__ verify_oop(obj);
__ ret(0);
@@ -1089,15 +1251,23 @@ OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
{
__ set_info("register_finalizer", dont_gc_arguments);
+ // This is called via call_runtime so the arguments
+ // will be place in C abi locations
+
+#ifdef _LP64
+ __ verify_oop(c_rarg0);
+ __ mov(rax, c_rarg0);
+#else
// The object is passed on the stack and we haven't pushed a
// frame yet so it's one work away from top of stack.
- __ movl(rax, Address(rsp, 1 * BytesPerWord));
+ __ movptr(rax, Address(rsp, 1 * BytesPerWord));
__ verify_oop(rax);
+#endif // _LP64
// load the klass and check the has finalizer flag
Label register_finalizer;
Register t = rsi;
- __ movl(t, Address(rax, oopDesc::klass_offset_in_bytes()));
+ __ movptr(t, Address(rax, oopDesc::klass_offset_in_bytes()));
__ movl(t, Address(t, Klass::access_flags_offset_in_bytes() + sizeof(oopDesc)));
__ testl(t, JVM_ACC_HAS_FINALIZER);
__ jcc(Assembler::notZero, register_finalizer);
@@ -1185,46 +1355,49 @@ OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
case slow_subtype_check_id:
{
enum layout {
- rax_off,
- rcx_off,
- rsi_off,
- rdi_off,
- saved_rbp_off,
- return_off,
- sub_off,
- super_off,
+ rax_off, SLOT2(raxH_off)
+ rcx_off, SLOT2(rcxH_off)
+ rsi_off, SLOT2(rsiH_off)
+ rdi_off, SLOT2(rdiH_off)
+ // saved_rbp_off, SLOT2(saved_rbpH_off)
+ return_off, SLOT2(returnH_off)
+ sub_off, SLOT2(subH_off)
+ super_off, SLOT2(superH_off)
framesize
};
__ set_info("slow_subtype_check", dont_gc_arguments);
- __ pushl(rdi);
- __ pushl(rsi);
- __ pushl(rcx);
- __ pushl(rax);
- __ movl(rsi, Address(rsp, (super_off - 1) * BytesPerWord)); // super
- __ movl(rax, Address(rsp, (sub_off - 1) * BytesPerWord)); // sub
+ __ push(rdi);
+ __ push(rsi);
+ __ push(rcx);
+ __ push(rax);
- __ movl(rdi,Address(rsi,sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes()));
- __ movl(rcx,Address(rdi,arrayOopDesc::length_offset_in_bytes()));
- __ addl(rdi,arrayOopDesc::base_offset_in_bytes(T_OBJECT));
+ // This is called by pushing args and not with C abi
+ __ movptr(rsi, Address(rsp, (super_off) * VMRegImpl::stack_slot_size)); // super
+ __ movptr(rax, Address(rsp, (sub_off ) * VMRegImpl::stack_slot_size)); // sub
+
+ __ movptr(rdi,Address(rsi,sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes()));
+ // since size is postive movl does right thing on 64bit
+ __ movl(rcx, Address(rdi, arrayOopDesc::length_offset_in_bytes()));
+ __ addptr(rdi, arrayOopDesc::base_offset_in_bytes(T_OBJECT));
Label miss;
__ repne_scan();
__ jcc(Assembler::notEqual, miss);
- __ movl(Address(rsi,sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes()), rax);
- __ movl(Address(rsp, (super_off - 1) * BytesPerWord), 1); // result
- __ popl(rax);
- __ popl(rcx);
- __ popl(rsi);
- __ popl(rdi);
+ __ movptr(Address(rsi,sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes()), rax);
+ __ movptr(Address(rsp, (super_off) * VMRegImpl::stack_slot_size), 1); // result
+ __ pop(rax);
+ __ pop(rcx);
+ __ pop(rsi);
+ __ pop(rdi);
__ ret(0);
__ bind(miss);
- __ movl(Address(rsp, (super_off - 1) * BytesPerWord), 0); // result
- __ popl(rax);
- __ popl(rcx);
- __ popl(rsi);
- __ popl(rdi);
+ __ movptr(Address(rsp, (super_off) * VMRegImpl::stack_slot_size), 0); // result
+ __ pop(rax);
+ __ pop(rcx);
+ __ pop(rsi);
+ __ pop(rdi);
__ ret(0);
}
break;
@@ -1237,6 +1410,8 @@ OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
StubFrame f(sasm, "monitorenter", dont_gc_arguments);
OopMap* map = save_live_registers(sasm, 3, save_fpu_registers);
+ // Called with store_parameter and not C abi
+
f.load_argument(1, rax); // rax,: object
f.load_argument(0, rbx); // rbx,: lock address
@@ -1256,6 +1431,8 @@ OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
StubFrame f(sasm, "monitorexit", dont_gc_arguments);
OopMap* map = save_live_registers(sasm, 2, save_fpu_registers);
+ // Called with store_parameter and not C abi
+
f.load_argument(0, rax); // rax,: lock address
// note: really a leaf routine but must setup last java sp
@@ -1304,9 +1481,9 @@ OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
// the live registers get saved.
save_live_registers(sasm, 1);
- __ pushl(rax);
+ __ NOT_LP64(push(rax)) LP64_ONLY(mov(c_rarg0, rax));
__ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_object_alloc)));
- __ popl(rax);
+ NOT_LP64(__ pop(rax));
restore_live_registers(sasm);
}
@@ -1316,18 +1493,19 @@ OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
{
// rax, and rdx are destroyed, but should be free since the result is returned there
// preserve rsi,ecx
- __ pushl(rsi);
- __ pushl(rcx);
+ __ push(rsi);
+ __ push(rcx);
+ LP64_ONLY(__ push(rdx);)
// check for NaN
Label return0, do_return, return_min_jlong, do_convert;
- Address value_high_word(rsp, 8);
- Address value_low_word(rsp, 4);
- Address result_high_word(rsp, 16);
- Address result_low_word(rsp, 12);
+ Address value_high_word(rsp, wordSize + 4);
+ Address value_low_word(rsp, wordSize);
+ Address result_high_word(rsp, 3*wordSize + 4);
+ Address result_low_word(rsp, 3*wordSize);
- __ subl(rsp, 20);
+ __ subptr(rsp, 32); // more than enough on 32bit
__ fst_d(value_low_word);
__ movl(rax, value_high_word);
__ andl(rax, 0x7ff00000);
@@ -1340,7 +1518,7 @@ OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
__ bind(do_convert);
__ fnstcw(Address(rsp, 0));
- __ movzxw(rax, Address(rsp, 0));
+ __ movzwl(rax, Address(rsp, 0));
__ orl(rax, 0xc00);
__ movw(Address(rsp, 2), rax);
__ fldcw(Address(rsp, 2));
@@ -1348,9 +1526,11 @@ OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
__ fistp_d(result_low_word);
__ fldcw(Address(rsp, 0));
__ fwait();
- __ movl(rax, result_low_word);
+ // This gets the entire long in rax on 64bit
+ __ movptr(rax, result_low_word);
+ // testing of high bits
__ movl(rdx, result_high_word);
- __ movl(rcx, rax);
+ __ mov(rcx, rax);
// What the heck is the point of the next instruction???
__ xorl(rcx, 0x0);
__ movl(rsi, 0x80000000);
@@ -1360,34 +1540,52 @@ OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
__ fldz();
__ fcomp_d(value_low_word);
__ fnstsw_ax();
+#ifdef _LP64
+ __ testl(rax, 0x4100); // ZF & CF == 0
+ __ jcc(Assembler::equal, return_min_jlong);
+#else
__ sahf();
__ jcc(Assembler::above, return_min_jlong);
+#endif // _LP64
// return max_jlong
+#ifndef _LP64
__ movl(rdx, 0x7fffffff);
__ movl(rax, 0xffffffff);
+#else
+ __ mov64(rax, CONST64(0x7fffffffffffffff));
+#endif // _LP64
__ jmp(do_return);
__ bind(return_min_jlong);
+#ifndef _LP64
__ movl(rdx, 0x80000000);
__ xorl(rax, rax);
+#else
+ __ mov64(rax, CONST64(0x8000000000000000));
+#endif // _LP64
__ jmp(do_return);
__ bind(return0);
__ fpop();
- __ xorl(rdx,rdx);
- __ xorl(rax,rax);
+#ifndef _LP64
+ __ xorptr(rdx,rdx);
+ __ xorptr(rax,rax);
+#else
+ __ xorptr(rax, rax);
+#endif // _LP64
__ bind(do_return);
- __ addl(rsp, 20);
- __ popl(rcx);
- __ popl(rsi);
+ __ addptr(rsp, 32);
+ LP64_ONLY(__ pop(rdx);)
+ __ pop(rcx);
+ __ pop(rsi);
__ ret(0);
}
break;
default:
{ StubFrame f(sasm, "unimplemented entry", dont_gc_arguments);
- __ movl(rax, (int)id);
+ __ movptr(rax, (int)id);
__ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, unimplemented_entry), rax);
__ should_not_reach_here();
}
diff --git a/hotspot/src/cpu/x86/vm/cppInterpreter_x86.cpp b/hotspot/src/cpu/x86/vm/cppInterpreter_x86.cpp
index 89c497de7a4..a829cb3132b 100644
--- a/hotspot/src/cpu/x86/vm/cppInterpreter_x86.cpp
+++ b/hotspot/src/cpu/x86/vm/cppInterpreter_x86.cpp
@@ -44,6 +44,14 @@ extern "C" void RecursiveInterpreterActivation(interpreterState istate )
Label fast_accessor_slow_entry_path; // fast accessor methods need to be able to jmp to unsynchronized
// c++ interpreter entry point this holds that entry point label.
+// default registers for state and sender_sp
+// state and sender_sp are the same on 32bit because we have no choice.
+// state could be rsi on 64bit but it is an arg reg and not callee save
+// so r13 is better choice.
+
+const Register state = NOT_LP64(rsi) LP64_ONLY(r13);
+const Register sender_sp_on_entry = NOT_LP64(rsi) LP64_ONLY(r13);
+
// NEEDED for JVMTI?
// address AbstractInterpreter::_remove_activation_preserving_args_entry;
@@ -88,7 +96,6 @@ bool CppInterpreter::contains(address pc) {
address CppInterpreterGenerator::generate_result_handler_for(BasicType type) {
- const Register state = rsi; // current activation object, valid on entry
address entry = __ pc();
switch (type) {
case T_BOOLEAN: __ c2bool(rax); break;
@@ -98,19 +105,22 @@ address CppInterpreterGenerator::generate_result_handler_for(BasicType type) {
case T_VOID : // fall thru
case T_LONG : // fall thru
case T_INT : /* nothing to do */ break;
+
case T_DOUBLE :
case T_FLOAT :
- { const Register t = InterpreterRuntime::SignatureHandlerGenerator::temp();
- __ popl(t); // remove return address first
- __ pop_dtos_to_rsp();
+ {
+ const Register t = InterpreterRuntime::SignatureHandlerGenerator::temp();
+ __ pop(t); // remove return address first
// Must return a result for interpreter or compiler. In SSE
// mode, results are returned in xmm0 and the FPU stack must
// be empty.
if (type == T_FLOAT && UseSSE >= 1) {
+#ifndef _LP64
// Load ST0
__ fld_d(Address(rsp, 0));
// Store as float and empty fpu stack
__ fstp_s(Address(rsp, 0));
+#endif // !_LP64
// and reload
__ movflt(xmm0, Address(rsp, 0));
} else if (type == T_DOUBLE && UseSSE >= 2 ) {
@@ -120,13 +130,13 @@ address CppInterpreterGenerator::generate_result_handler_for(BasicType type) {
__ fld_d(Address(rsp, 0));
}
// and pop the temp
- __ addl(rsp, 2 * wordSize);
- __ pushl(t); // restore return address
+ __ addptr(rsp, 2 * wordSize);
+ __ push(t); // restore return address
}
break;
case T_OBJECT :
// retrieve result from frame
- __ movl(rax, STATE(_oop_temp));
+ __ movptr(rax, STATE(_oop_temp));
// and verify it
__ verify_oop(rax);
break;
@@ -146,7 +156,7 @@ address CppInterpreterGenerator::generate_tosca_to_stack_converter(BasicType typ
address entry = __ pc();
const Register t = InterpreterRuntime::SignatureHandlerGenerator::temp();
- __ popl(t); // remove return address first
+ __ pop(t); // remove return address first
switch (type) {
case T_VOID:
break;
@@ -154,53 +164,53 @@ address CppInterpreterGenerator::generate_tosca_to_stack_converter(BasicType typ
#ifdef EXTEND
__ c2bool(rax);
#endif
- __ pushl(rax);
+ __ push(rax);
break;
case T_CHAR :
#ifdef EXTEND
__ andl(rax, 0xFFFF);
#endif
- __ pushl(rax);
+ __ push(rax);
break;
case T_BYTE :
#ifdef EXTEND
__ sign_extend_byte (rax);
#endif
- __ pushl(rax);
+ __ push(rax);
break;
case T_SHORT :
#ifdef EXTEND
__ sign_extend_short(rax);
#endif
- __ pushl(rax);
+ __ push(rax);
break;
case T_LONG :
- __ pushl(rdx);
- __ pushl(rax);
+ __ push(rdx); // pushes useless junk on 64bit
+ __ push(rax);
break;
case T_INT :
- __ pushl(rax);
+ __ push(rax);
break;
case T_FLOAT :
- // Result is in ST(0)
+ // Result is in ST(0)/xmm0
+ __ subptr(rsp, wordSize);
if ( UseSSE < 1) {
- __ push(ftos); // and save it
+ __ fstp_s(Address(rsp, 0));
} else {
- __ subl(rsp, wordSize);
__ movflt(Address(rsp, 0), xmm0);
}
break;
case T_DOUBLE :
+ __ subptr(rsp, 2*wordSize);
if ( UseSSE < 2 ) {
- __ push(dtos); // put ST0 on java stack
+ __ fstp_d(Address(rsp, 0));
} else {
- __ subl(rsp, 2*wordSize);
__ movdbl(Address(rsp, 0), xmm0);
}
break;
case T_OBJECT :
__ verify_oop(rax); // verify it
- __ pushl(rax);
+ __ push(rax);
break;
default : ShouldNotReachHere();
}
@@ -212,7 +222,7 @@ address CppInterpreterGenerator::generate_stack_to_stack_converter(BasicType typ
// A result is in the java expression stack of the interpreted method that has just
// returned. Place this result on the java expression stack of the caller.
//
- // The current interpreter activation in rsi is for the method just returning its
+ // The current interpreter activation in rsi/r13 is for the method just returning its
// result. So we know that the result of this method is on the top of the current
// execution stack (which is pre-pushed) and will be return to the top of the caller
// stack. The top of the callers stack is the bottom of the locals of the current
@@ -222,20 +232,19 @@ address CppInterpreterGenerator::generate_stack_to_stack_converter(BasicType typ
// of the calling activation. This enable this routine to leave the return address
// to the frame manager on the stack and do a vanilla return.
//
- // On entry: rsi - interpreter state of activation returning a (potential) result
- // On Return: rsi - unchanged
+ // On entry: rsi/r13 - interpreter state of activation returning a (potential) result
+ // On Return: rsi/r13 - unchanged
// rax - new stack top for caller activation (i.e. activation in _prev_link)
//
// Can destroy rdx, rcx.
//
address entry = __ pc();
- const Register state = rsi; // current activation object, valid on entry
const Register t = InterpreterRuntime::SignatureHandlerGenerator::temp();
switch (type) {
case T_VOID:
- __ movl(rax, STATE(_locals)); // pop parameters get new stack value
- __ addl(rax, wordSize); // account for prepush before we return
+ __ movptr(rax, STATE(_locals)); // pop parameters get new stack value
+ __ addptr(rax, wordSize); // account for prepush before we return
break;
case T_FLOAT :
case T_BOOLEAN:
@@ -244,10 +253,10 @@ address CppInterpreterGenerator::generate_stack_to_stack_converter(BasicType typ
case T_SHORT :
case T_INT :
// 1 word result
- __ movl(rdx, STATE(_stack));
- __ movl(rax, STATE(_locals)); // address for result
+ __ movptr(rdx, STATE(_stack));
+ __ movptr(rax, STATE(_locals)); // address for result
__ movl(rdx, Address(rdx, wordSize)); // get result
- __ movl(Address(rax, 0), rdx); // and store it
+ __ movptr(Address(rax, 0), rdx); // and store it
break;
case T_LONG :
case T_DOUBLE :
@@ -256,20 +265,20 @@ address CppInterpreterGenerator::generate_stack_to_stack_converter(BasicType typ
// except we allocated one extra word for this intepretState so we won't overwrite it
// when we return a two word result.
- __ movl(rax, STATE(_locals)); // address for result
- __ movl(rcx, STATE(_stack));
- __ subl(rax, wordSize); // need addition word besides locals[0]
- __ movl(rdx, Address(rcx, 2*wordSize)); // get result word
- __ movl(Address(rax, wordSize), rdx); // and store it
- __ movl(rdx, Address(rcx, wordSize)); // get result word
- __ movl(Address(rax, 0), rdx); // and store it
+ __ movptr(rax, STATE(_locals)); // address for result
+ __ movptr(rcx, STATE(_stack));
+ __ subptr(rax, wordSize); // need addition word besides locals[0]
+ __ movptr(rdx, Address(rcx, 2*wordSize)); // get result word (junk in 64bit)
+ __ movptr(Address(rax, wordSize), rdx); // and store it
+ __ movptr(rdx, Address(rcx, wordSize)); // get result word
+ __ movptr(Address(rax, 0), rdx); // and store it
break;
case T_OBJECT :
- __ movl(rdx, STATE(_stack));
- __ movl(rax, STATE(_locals)); // address for result
- __ movl(rdx, Address(rdx, wordSize)); // get result
+ __ movptr(rdx, STATE(_stack));
+ __ movptr(rax, STATE(_locals)); // address for result
+ __ movptr(rdx, Address(rdx, wordSize)); // get result
__ verify_oop(rdx); // verify it
- __ movl(Address(rax, 0), rdx); // and store it
+ __ movptr(Address(rax, 0), rdx); // and store it
break;
default : ShouldNotReachHere();
}
@@ -285,12 +294,11 @@ address CppInterpreterGenerator::generate_stack_to_native_abi_converter(BasicTyp
// frame manager execept in this situation the caller is native code (c1/c2/call_stub)
// and so rather than return result onto caller's java expression stack we return the
// result in the expected location based on the native abi.
- // On entry: rsi - interpreter state of activation returning a (potential) result
- // On Return: rsi - unchanged
+ // On entry: rsi/r13 - interpreter state of activation returning a (potential) result
+ // On Return: rsi/r13 - unchanged
// Other registers changed [rax/rdx/ST(0) as needed for the result returned]
address entry = __ pc();
- const Register state = rsi; // current activation object, valid on entry
switch (type) {
case T_VOID:
break;
@@ -299,17 +307,16 @@ address CppInterpreterGenerator::generate_stack_to_native_abi_converter(BasicTyp
case T_BYTE :
case T_SHORT :
case T_INT :
- __ movl(rdx, STATE(_stack)); // get top of stack
+ __ movptr(rdx, STATE(_stack)); // get top of stack
__ movl(rax, Address(rdx, wordSize)); // get result word 1
break;
case T_LONG :
- __ movl(rdx, STATE(_stack)); // get top of stack
- __ movl(rax, Address(rdx, wordSize)); // get result low word
- __ movl(rdx, Address(rdx, 2*wordSize)); // get result high word
- break;
+ __ movptr(rdx, STATE(_stack)); // get top of stack
+ __ movptr(rax, Address(rdx, wordSize)); // get result low word
+ NOT_LP64(__ movl(rdx, Address(rdx, 2*wordSize));) // get result high word
break;
case T_FLOAT :
- __ movl(rdx, STATE(_stack)); // get top of stack
+ __ movptr(rdx, STATE(_stack)); // get top of stack
if ( UseSSE >= 1) {
__ movflt(xmm0, Address(rdx, wordSize));
} else {
@@ -317,7 +324,7 @@ address CppInterpreterGenerator::generate_stack_to_native_abi_converter(BasicTyp
}
break;
case T_DOUBLE :
- __ movl(rdx, STATE(_stack)); // get top of stack
+ __ movptr(rdx, STATE(_stack)); // get top of stack
if ( UseSSE > 1) {
__ movdbl(xmm0, Address(rdx, wordSize));
} else {
@@ -325,8 +332,8 @@ address CppInterpreterGenerator::generate_stack_to_native_abi_converter(BasicTyp
}
break;
case T_OBJECT :
- __ movl(rdx, STATE(_stack)); // get top of stack
- __ movl(rax, Address(rdx, wordSize)); // get result word 1
+ __ movptr(rdx, STATE(_stack)); // get top of stack
+ __ movptr(rax, Address(rdx, wordSize)); // get result word 1
__ verify_oop(rax); // verify it
break;
default : ShouldNotReachHere();
@@ -408,54 +415,58 @@ void CppInterpreterGenerator::generate_compute_interpreter_state(const Register
if (!native) {
#ifdef PRODUCT
- __ subl(rsp, 2*wordSize);
+ __ subptr(rsp, 2*wordSize);
#else /* PRODUCT */
- __ pushl((int)NULL);
- __ pushl(state); // make it look like a real argument
+ __ push((int32_t)NULL_WORD);
+ __ push(state); // make it look like a real argument
#endif /* PRODUCT */
}
// Now that we are assure of space for stack result, setup typical linkage
- __ pushl(rax);
+ __ push(rax);
__ enter();
- __ movl(rax, state); // save current state
+ __ mov(rax, state); // save current state
- __ leal(rsp, Address(rsp, -(int)sizeof(BytecodeInterpreter)));
- __ movl(state, rsp);
+ __ lea(rsp, Address(rsp, -(int)sizeof(BytecodeInterpreter)));
+ __ mov(state, rsp);
- // rsi == state/locals rax == prevstate
+ // rsi/r13 == state/locals rax == prevstate
// initialize the "shadow" frame so that use since C++ interpreter not directly
// recursive. Simpler to recurse but we can't trim expression stack as we call
// new methods.
- __ movl(STATE(_locals), locals); // state->_locals = locals()
- __ movl(STATE(_self_link), state); // point to self
- __ movl(STATE(_prev_link), rax); // state->_link = state on entry (NULL or previous state)
- __ movl(STATE(_sender_sp), sender_sp); // state->_sender_sp = sender_sp
+ __ movptr(STATE(_locals), locals); // state->_locals = locals()
+ __ movptr(STATE(_self_link), state); // point to self
+ __ movptr(STATE(_prev_link), rax); // state->_link = state on entry (NULL or previous state)
+ __ movptr(STATE(_sender_sp), sender_sp); // state->_sender_sp = sender_sp
+#ifdef _LP64
+ __ movptr(STATE(_thread), r15_thread); // state->_bcp = codes()
+#else
__ get_thread(rax); // get vm's javathread*
- __ movl(STATE(_thread), rax); // state->_bcp = codes()
- __ movl(rdx, Address(rbx, methodOopDesc::const_offset())); // get constantMethodOop
- __ leal(rdx, Address(rdx, constMethodOopDesc::codes_offset())); // get code base
+ __ movptr(STATE(_thread), rax); // state->_bcp = codes()
+#endif // _LP64
+ __ movptr(rdx, Address(rbx, methodOopDesc::const_offset())); // get constantMethodOop
+ __ lea(rdx, Address(rdx, constMethodOopDesc::codes_offset())); // get code base
if (native) {
- __ movl(STATE(_bcp), (intptr_t)NULL); // state->_bcp = NULL
+ __ movptr(STATE(_bcp), (int32_t)NULL_WORD); // state->_bcp = NULL
} else {
- __ movl(STATE(_bcp), rdx); // state->_bcp = codes()
+ __ movptr(STATE(_bcp), rdx); // state->_bcp = codes()
}
- __ xorl(rdx, rdx);
- __ movl(STATE(_oop_temp), rdx); // state->_oop_temp = NULL (only really needed for native)
- __ movl(STATE(_mdx), rdx); // state->_mdx = NULL
- __ movl(rdx, Address(rbx, methodOopDesc::constants_offset()));
- __ movl(rdx, Address(rdx, constantPoolOopDesc::cache_offset_in_bytes()));
- __ movl(STATE(_constants), rdx); // state->_constants = constants()
+ __ xorptr(rdx, rdx);
+ __ movptr(STATE(_oop_temp), rdx); // state->_oop_temp = NULL (only really needed for native)
+ __ movptr(STATE(_mdx), rdx); // state->_mdx = NULL
+ __ movptr(rdx, Address(rbx, methodOopDesc::constants_offset()));
+ __ movptr(rdx, Address(rdx, constantPoolOopDesc::cache_offset_in_bytes()));
+ __ movptr(STATE(_constants), rdx); // state->_constants = constants()
- __ movl(STATE(_method), rbx); // state->_method = method()
- __ movl(STATE(_msg), (int) BytecodeInterpreter::method_entry); // state->_msg = initial method entry
- __ movl(STATE(_result._to_call._callee), (int) NULL); // state->_result._to_call._callee_callee = NULL
+ __ movptr(STATE(_method), rbx); // state->_method = method()
+ __ movl(STATE(_msg), (int32_t) BytecodeInterpreter::method_entry); // state->_msg = initial method entry
+ __ movptr(STATE(_result._to_call._callee), (int32_t) NULL_WORD); // state->_result._to_call._callee_callee = NULL
- __ movl(STATE(_monitor_base), rsp); // set monitor block bottom (grows down) this would point to entry [0]
+ __ movptr(STATE(_monitor_base), rsp); // set monitor block bottom (grows down) this would point to entry [0]
// entries run from -1..x where &monitor[x] ==
{
@@ -479,36 +490,44 @@ void CppInterpreterGenerator::generate_compute_interpreter_state(const Register
const int mirror_offset = klassOopDesc::klass_part_offset_in_bytes() + Klass::java_mirror_offset_in_bytes();
__ movl(rax, access_flags);
__ testl(rax, JVM_ACC_STATIC);
- __ movl(rax, Address(locals, 0)); // get receiver (assume this is frequent case)
+ __ movptr(rax, Address(locals, 0)); // get receiver (assume this is frequent case)
__ jcc(Assembler::zero, done);
- __ movl(rax, Address(rbx, methodOopDesc::constants_offset()));
- __ movl(rax, Address(rax, constantPoolOopDesc::pool_holder_offset_in_bytes()));
- __ movl(rax, Address(rax, mirror_offset));
+ __ movptr(rax, Address(rbx, methodOopDesc::constants_offset()));
+ __ movptr(rax, Address(rax, constantPoolOopDesc::pool_holder_offset_in_bytes()));
+ __ movptr(rax, Address(rax, mirror_offset));
__ bind(done);
// add space for monitor & lock
- __ subl(rsp, entry_size); // add space for a monitor entry
- __ movl(Address(rsp, BasicObjectLock::obj_offset_in_bytes()), rax); // store object
+ __ subptr(rsp, entry_size); // add space for a monitor entry
+ __ movptr(Address(rsp, BasicObjectLock::obj_offset_in_bytes()), rax); // store object
__ bind(not_synced);
}
- __ movl(STATE(_stack_base), rsp); // set expression stack base ( == &monitors[-count])
+ __ movptr(STATE(_stack_base), rsp); // set expression stack base ( == &monitors[-count])
if (native) {
- __ movl(STATE(_stack), rsp); // set current expression stack tos
- __ movl(STATE(_stack_limit), rsp);
+ __ movptr(STATE(_stack), rsp); // set current expression stack tos
+ __ movptr(STATE(_stack_limit), rsp);
} else {
- __ subl(rsp, wordSize); // pre-push stack
- __ movl(STATE(_stack), rsp); // set current expression stack tos
+ __ subptr(rsp, wordSize); // pre-push stack
+ __ movptr(STATE(_stack), rsp); // set current expression stack tos
// compute full expression stack limit
const Address size_of_stack (rbx, methodOopDesc::max_stack_offset());
__ load_unsigned_word(rdx, size_of_stack); // get size of expression stack in words
- __ negl(rdx); // so we can subtract in next step
+ __ negptr(rdx); // so we can subtract in next step
// Allocate expression stack
- __ leal(rsp, Address(rsp, rdx, Address::times_4));
- __ movl(STATE(_stack_limit), rsp);
+ __ lea(rsp, Address(rsp, rdx, Address::times_ptr));
+ __ movptr(STATE(_stack_limit), rsp);
}
+#ifdef _LP64
+ // Make sure stack is properly aligned and sized for the abi
+ __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
+ __ andptr(rsp, -16); // must be 16 byte boundry (see amd64 ABI)
+#endif // _LP64
+
+
+
}
// Helpers for commoning out cases in the various type of method entries.
@@ -528,7 +547,7 @@ void InterpreterGenerator::generate_counter_incr(Label* overflow, Label* profile
const Address backedge_counter (rbx, methodOopDesc::backedge_counter_offset() + InvocationCounter::counter_offset());
if (ProfileInterpreter) { // %%% Merge this into methodDataOop
- __ increment(Address(rbx,methodOopDesc::interpreter_invocation_counter_offset()));
+ __ incrementl(Address(rbx,methodOopDesc::interpreter_invocation_counter_offset()));
}
// Update standard invocation counters
__ movl(rax, backedge_counter); // load backedge counter
@@ -552,7 +571,7 @@ void InterpreterGenerator::generate_counter_incr(Label* overflow, Label* profile
void InterpreterGenerator::generate_counter_overflow(Label* do_continue) {
// C++ interpreter on entry
- // rsi - new interpreter state pointer
+ // rsi/r13 - new interpreter state pointer
// rbp - interpreter frame pointer
// rbx - method
@@ -563,7 +582,7 @@ void InterpreterGenerator::generate_counter_overflow(Label* do_continue) {
// rsp - sender_sp
// C++ interpreter only
- // rsi - previous interpreter state pointer
+ // rsi/r13 - previous interpreter state pointer
const Address size_of_parameters(rbx, methodOopDesc::size_of_parameters_offset());
@@ -571,16 +590,14 @@ void InterpreterGenerator::generate_counter_overflow(Label* do_continue) {
// indicating if the counter overflow occurs at a backwards branch (non-NULL bcp).
// The call returns the address of the verified entry point for the method or NULL
// if the compilation did not complete (either went background or bailed out).
- __ movl(rax, (int)false);
+ __ movptr(rax, (int32_t)false);
__ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::frequency_counter_overflow), rax);
// for c++ interpreter can rsi really be munged?
- __ leal(rsi, Address(rbp, -sizeof(BytecodeInterpreter))); // restore state
- __ movl(rbx, Address(rsi, byte_offset_of(BytecodeInterpreter, _method))); // restore method
- __ movl(rdi, Address(rsi, byte_offset_of(BytecodeInterpreter, _locals))); // get locals pointer
+ __ lea(state, Address(rbp, -sizeof(BytecodeInterpreter))); // restore state
+ __ movptr(rbx, Address(state, byte_offset_of(BytecodeInterpreter, _method))); // restore method
+ __ movptr(rdi, Address(state, byte_offset_of(BytecodeInterpreter, _locals))); // get locals pointer
- // Preserve invariant that rsi/rdi contain bcp/locals of sender frame
- // and jump to the interpreted entry.
__ jmp(*do_continue, relocInfo::none);
}
@@ -597,7 +614,7 @@ void InterpreterGenerator::generate_stack_overflow_check(void) {
// rbx,: methodOop
// C++ Interpreter
- // rsi: previous interpreter frame state object
+ // rsi/r13: previous interpreter frame state object
// rdi: &locals[0]
// rcx: # of locals
// rdx: number of additional locals this frame needs (what we must check)
@@ -628,11 +645,11 @@ void InterpreterGenerator::generate_stack_overflow_check(void) {
// save rsi == caller's bytecode ptr (c++ previous interp. state)
// QQQ problem here?? rsi overload????
- __ pushl(rsi);
+ __ push(state);
- const Register thread = rsi;
+ const Register thread = LP64_ONLY(r15_thread) NOT_LP64(rsi);
- __ get_thread(thread);
+ NOT_LP64(__ get_thread(thread));
const Address stack_base(thread, Thread::stack_base_offset());
const Address stack_size(thread, Thread::stack_size_offset());
@@ -643,26 +660,26 @@ void InterpreterGenerator::generate_stack_overflow_check(void) {
// Any additional monitors need a check when moving the expression stack
const one_monitor = frame::interpreter_frame_monitor_size() * wordSize;
__ load_unsigned_word(rax, size_of_stack); // get size of expression stack in words
- __ leal(rax, Address(noreg, rax, Interpreter::stackElementScale(), one_monitor));
- __ leal(rax, Address(rax, rdx, Interpreter::stackElementScale(), overhead_size));
+ __ lea(rax, Address(noreg, rax, Interpreter::stackElementScale(), one_monitor));
+ __ lea(rax, Address(rax, rdx, Interpreter::stackElementScale(), overhead_size));
#ifdef ASSERT
Label stack_base_okay, stack_size_okay;
// verify that thread stack base is non-zero
- __ cmpl(stack_base, 0);
+ __ cmpptr(stack_base, (int32_t)0);
__ jcc(Assembler::notEqual, stack_base_okay);
__ stop("stack base is zero");
__ bind(stack_base_okay);
// verify that thread stack size is non-zero
- __ cmpl(stack_size, 0);
+ __ cmpptr(stack_size, (int32_t)0);
__ jcc(Assembler::notEqual, stack_size_okay);
__ stop("stack size is zero");
__ bind(stack_size_okay);
#endif
// Add stack base to locals and subtract stack size
- __ addl(rax, stack_base);
- __ subl(rax, stack_size);
+ __ addptr(rax, stack_base);
+ __ subptr(rax, stack_size);
// We should have a magic number here for the size of the c++ interpreter frame.
// We can't actually tell this ahead of time. The debug version size is around 3k
@@ -674,20 +691,20 @@ void InterpreterGenerator::generate_stack_overflow_check(void) {
(StackRedPages+StackYellowPages);
// Only need this if we are stack banging which is temporary while
// we're debugging.
- __ addl(rax, slop + 2*max_pages * page_size);
+ __ addptr(rax, slop + 2*max_pages * page_size);
// check against the current stack bottom
- __ cmpl(rsp, rax);
+ __ cmpptr(rsp, rax);
__ jcc(Assembler::above, after_frame_check_pop);
- __ popl(rsi); // get saved bcp / (c++ prev state ).
+ __ pop(state); // get c++ prev state.
// throw exception return address becomes throwing pc
__ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::throw_StackOverflowError));
// all done with frame size check
__ bind(after_frame_check_pop);
- __ popl(rsi);
+ __ pop(state);
__ bind(after_frame_check);
}
@@ -696,17 +713,18 @@ void InterpreterGenerator::generate_stack_overflow_check(void) {
// rbx - methodOop
//
void InterpreterGenerator::lock_method(void) {
- // assumes state == rsi == pointer to current interpreterState
- // minimally destroys rax, rdx, rdi
+ // assumes state == rsi/r13 == pointer to current interpreterState
+ // minimally destroys rax, rdx|c_rarg1, rdi
//
// synchronize method
- const Register state = rsi;
const int entry_size = frame::interpreter_frame_monitor_size() * wordSize;
const Address access_flags (rbx, methodOopDesc::access_flags_offset());
+ const Register monitor = NOT_LP64(rdx) LP64_ONLY(c_rarg1);
+
// find initial monitor i.e. monitors[-1]
- __ movl(rdx, STATE(_monitor_base)); // get monitor bottom limit
- __ subl(rdx, entry_size); // point to initial monitor
+ __ movptr(monitor, STATE(_monitor_base)); // get monitor bottom limit
+ __ subptr(monitor, entry_size); // point to initial monitor
#ifdef ASSERT
{ Label L;
@@ -721,35 +739,34 @@ void InterpreterGenerator::lock_method(void) {
{ Label done;
const int mirror_offset = klassOopDesc::klass_part_offset_in_bytes() + Klass::java_mirror_offset_in_bytes();
__ movl(rax, access_flags);
- __ movl(rdi, STATE(_locals)); // prepare to get receiver (assume common case)
+ __ movptr(rdi, STATE(_locals)); // prepare to get receiver (assume common case)
__ testl(rax, JVM_ACC_STATIC);
- __ movl(rax, Address(rdi, 0)); // get receiver (assume this is frequent case)
+ __ movptr(rax, Address(rdi, 0)); // get receiver (assume this is frequent case)
__ jcc(Assembler::zero, done);
- __ movl(rax, Address(rbx, methodOopDesc::constants_offset()));
- __ movl(rax, Address(rax, constantPoolOopDesc::pool_holder_offset_in_bytes()));
- __ movl(rax, Address(rax, mirror_offset));
+ __ movptr(rax, Address(rbx, methodOopDesc::constants_offset()));
+ __ movptr(rax, Address(rax, constantPoolOopDesc::pool_holder_offset_in_bytes()));
+ __ movptr(rax, Address(rax, mirror_offset));
__ bind(done);
}
#ifdef ASSERT
{ Label L;
- __ cmpl(rax, Address(rdx, BasicObjectLock::obj_offset_in_bytes())); // correct object?
+ __ cmpptr(rax, Address(monitor, BasicObjectLock::obj_offset_in_bytes())); // correct object?
__ jcc(Assembler::equal, L);
__ stop("wrong synchronization lobject");
__ bind(L);
}
#endif // ASSERT
- // can destroy rax, rdx, rcx, and (via call_VM) rdi!
- __ lock_object(rdx);
+ // can destroy rax, rdx|c_rarg1, rcx, and (via call_VM) rdi!
+ __ lock_object(monitor);
}
// Call an accessor method (assuming it is resolved, otherwise drop into vanilla (slow path) entry
address InterpreterGenerator::generate_accessor_entry(void) {
- // rbx,: methodOop
- // rcx: receiver (preserve for slow entry into asm interpreter)
+ // rbx: methodOop
- // rsi: senderSP must preserved for slow path, set SP to it on fast path
+ // rsi/r13: senderSP must preserved for slow path, set SP to it on fast path
Label xreturn_path;
@@ -772,21 +789,21 @@ address InterpreterGenerator::generate_accessor_entry(void) {
// these conditions first and use slow path if necessary.
// rbx,: method
// rcx: receiver
- __ movl(rax, Address(rsp, wordSize));
+ __ movptr(rax, Address(rsp, wordSize));
// check if local 0 != NULL and read field
- __ testl(rax, rax);
+ __ testptr(rax, rax);
__ jcc(Assembler::zero, slow_path);
- __ movl(rdi, Address(rbx, methodOopDesc::constants_offset()));
+ __ movptr(rdi, Address(rbx, methodOopDesc::constants_offset()));
// read first instruction word and extract bytecode @ 1 and index @ 2
- __ movl(rdx, Address(rbx, methodOopDesc::const_offset()));
+ __ movptr(rdx, Address(rbx, methodOopDesc::const_offset()));
__ movl(rdx, Address(rdx, constMethodOopDesc::codes_offset()));
// Shift codes right to get the index on the right.
// The bytecode fetched looks like Manage a renewable lease. The lease can be renewed indefinitely
+ * but if the lease runs to its current expiry date without being renewed
+ * then the expiry callback is invoked. If the lease has already expired
+ * when renewal is attempted then the lease method returns zero. Renew the lease for the given time. The new time can be shorter
+ * than the previous one, in which case the lease will expire earlier
+ * than it would have. Calling this method after the lease has expired will return zero
+ * immediately and have no other effect. Cancel the lease without calling the expiry callback. A task that is repeatedly run by an Executor. The task will be
+ * repeated as long as the {@link #isSuspended()} method returns true. Once
+ * that method returns false, the task is no longer executed until someone
+ * calls {@link #resume()}. Base class for custom implementations of the {@link MBeanServer}
+ * interface. The commonest use of this class is as the {@linkplain
+ * JMXNamespace#getSourceServer() source server} for a {@link
+ * JMXNamespace}, although this class can be used anywhere an {@code
+ * MBeanServer} instance is required. Note that the usual ways to
+ * obtain an {@code MBeanServer} instance are either to use {@link
+ * java.lang.management.ManagementFactory#getPlatformMBeanServer()
+ * ManagementFactory.getPlatformMBeanServer()} or to use the {@code
+ * newMBeanServer} or {@code createMBeanServer} methods from {@link
+ * javax.management.MBeanServerFactory MBeanServerFactory}. {@code
+ * MBeanServerSupport} is for certain cases where those are not
+ * appropriate. There are two main use cases for this class: special-purpose MBeanServer implementations,
+ * and namespaces containing Virtual MBeans. The next
+ * sections explain these use cases. In the simplest case, a subclass needs to implement only two methods: Subclasses can create such {@link DynamicMBean} MBeans on the fly - for
+ * instance, using the class {@link javax.management.StandardMBean}, just for
+ * the duration of an MBeanServer method call. In some cases
+ * the general-purpose {@code MBeanServer} that you get from
+ * {@link javax.management.MBeanServerFactory MBeanServerFactory} is not
+ * appropriate. You might need different security checks, or you might
+ * want a mock {@code MBeanServer} suitable for use in tests, or you might
+ * want a simplified and optimized {@code MBeanServer} for a special purpose. As an example of a special-purpose {@code MBeanServer}, the class {@link
+ * javax.management.QueryNotificationFilter QueryNotificationFilter} constructs
+ * an {@code MBeanServer} instance every time it filters a notification,
+ * with just one MBean that represents the notification. Although it could
+ * use {@code MBeanServerFactory.newMBeanServer}, a special-purpose {@code
+ * MBeanServer} will be quicker to create, use less memory, and have simpler
+ * methods that execute faster. Here is an example of a special-purpose {@code MBeanServer}
+ * implementation that contains exactly one MBean, which is specified at the
+ * time of creation. Using this class, you could make an {@code MBeanServer} that contains
+ * a {@link javax.management.timer.Timer Timer} MBean like this: When {@code getDynamicMBeanFor} always returns the same object for the
+ * same name, as here, notifications work in the expected way: if the object
+ * is a {@link NotificationEmitter} then listeners can be added using
+ * {@link MBeanServer#addNotificationListener(ObjectName, NotificationListener,
+ * NotificationFilter, Object) MBeanServer.addNotificationListener}. If
+ * {@code getDynamicMBeanFor} does not always return the same object for the
+ * same name, more work is needed to make notifications work, as described
+ * below. Virtual MBeans are MBeans that do not exist as Java objects,
+ * except transiently while they are being accessed. This is useful when
+ * there might be very many of them, or when keeping track of their creation
+ * and deletion might be expensive or hard. For example, you might have one
+ * MBean per system process. With an ordinary {@code MBeanServer}, you would
+ * have to list the system processes in order to create an MBean object for
+ * each one, and you would have to track the arrival and departure of system
+ * processes in order to create or delete the corresponding MBeans. With
+ * Virtual MBeans, you only need the MBean for a given process at the exact
+ * point where it is referenced with a call such as
+ * {@link MBeanServer#getAttribute MBeanServer.getAttribute}. Here is an example of an {@code MBeanServer} implementation that has
+ * one MBean for every system property. The system property {@code "java.home"}
+ * is represented by the MBean called {@code
+ * com.example:type=Property,name="java.home"}, with an attribute called
+ * {@code Value} that is the value of the property. Because the {@code getDynamicMBeanFor} method
+ * returns a different object every time it is called, the default handling
+ * of notifications will not work, as explained below.
+ * In this case it does not matter, because the object returned by {@code
+ * getDynamicMBeanFor} is not a {@code NotificationEmitter}, so {@link
+ * MBeanServer#addNotificationListener(ObjectName, NotificationListener,
+ * NotificationFilter, Object) MBeanServer.addNotificationListener} will
+ * always fail. But if we wanted to extend {@code PropsMBS} so that the MBean
+ * for property {@code "foo"} emitted a notification every time that property
+ * changed, we would need to do it as shown below. (Because there is no API to
+ * be informed when a property changes, this code assumes that some other code
+ * calls the {@code propertyChanged} method every time a property changes.) MBean creation through {@code MBeanServer.createMBean} is disabled
+ * by default. Subclasses which need to support MBean creation
+ * through {@code createMBean} need to implement a single method {@link
+ * #createMBean(String, ObjectName, ObjectName, Object[], String[],
+ * boolean)}. Similarly MBean registration and unregistration through {@code
+ * registerMBean} and {@code unregisterMBean} are disabled by default.
+ * Subclasses which need to support MBean registration and
+ * unregistration will need to implement {@link #registerMBean registerMBean}
+ * and {@link #unregisterMBean unregisterMBean}. By default {@link MBeanServer#addNotificationListener(ObjectName,
+ * NotificationListener, NotificationFilter, Object) addNotificationListener}
+ * is accepted for an MBean {@code name} if {@link #getDynamicMBeanFor
+ * getDynamicMBeanFor} The simplest way for a subclass that defines Virtual MBeans
+ * to support notifications is to create a private {@link VirtualEventManager}
+ * and override the method {@link
+ * #getNotificationEmitterFor getNotificationEmitterFor} as follows: A notification {@code n} can then be sent from the Virtual MBean
+ * called {@code name} by calling {@link VirtualEventManager#publish
+ * vem.publish} Make a new {@code MBeanServerSupport} instance. Returns a dynamically created handle that makes it possible to
+ * access the named MBean for the duration of a method call. An easy way to create such a {@link DynamicMBean} handle is, for
+ * instance, to create a temporary MXBean instance and to wrap it in
+ * an instance of
+ * {@link javax.management.StandardMBean}.
+ * This handle should remain valid for the duration of the call
+ * but can then be discarded. Subclasses should implement this method to return
+ * the names of all MBeans handled by this object instance. The object returned by getNames() should be safely {@linkplain
+ * Set#iterator iterable} even in the presence of other threads that may
+ * cause the set of names to change. Typically this means one of the
+ * following: List names matching the given pattern.
+ * The default implementation of this method calls {@link #getNames()}
+ * and returns the subset of those names matching {@code pattern}. Returns a {@link NotificationEmitter} which can be used to
+ * subscribe or unsubscribe for notifications with the named
+ * mbean. The default implementation of this method calls {@link
+ * #getDynamicMBeanFor getDynamicMBeanFor(name)} and returns that object
+ * if it is a {@code NotificationEmitter}, otherwise null. See above for further discussion of notification
+ * handling. Creates a new MBean in the MBean name space.
+ * This operation is not supported in this base class implementation.
+ *
+ *
+ * Special-purpose MBeanServer implementations
+ *
+ *
+ * public class SingletonMBeanServer extends MBeanServerSupport {
+ * private final ObjectName objectName;
+ * private final DynamicMBean mbean;
+ *
+ * public SingletonMBeanServer(ObjectName objectName, DynamicMBean mbean) {
+ * this.objectName = objectName;
+ * this.mbean = mbean;
+ * }
+ *
+ * @Override
+ * protected {@code Set
+ *
+ *
+ * Timer timer = new Timer();
+ * DynamicMBean mbean = new {@link javax.management.StandardMBean
+ * StandardMBean}(timer, TimerMBean.class);
+ * ObjectName name = new ObjectName("com.example:type=Timer");
+ * MBeanServer timerMBS = new SingletonMBeanServer(name, mbean);
+ *
+ *
+ * Namespaces containing Virtual MBeans
+ *
+ *
+ * public interface PropertyMBean {
+ * public String getValue();
+ * }
+ *
+ * public class PropsMBS extends MBeanServerSupport {
+ * private static ObjectName newObjectName(String name) {
+ * try {
+ * return new ObjectName(name);
+ * } catch (MalformedObjectNameException e) {
+ * throw new AssertionError(e);
+ * }
+ * }
+ *
+ * public static class PropertyImpl implements PropertyMBean {
+ * private final String name;
+ *
+ * public PropertyImpl(String name) {
+ * this.name = name;
+ * }
+ *
+ * public String getValue() {
+ * return System.getProperty(name);
+ * }
+ * }
+ *
+ * @Override
+ * public DynamicMBean {@link #getDynamicMBeanFor
+ * getDynamicMBeanFor}(ObjectName name)
+ * throws InstanceNotFoundException {
+ *
+ * // Check that the name is a legal one for a Property MBean
+ * ObjectName namePattern = newObjectName(
+ * "com.example:type=Property,name=\"*\"");
+ * if (!namePattern.apply(name))
+ * throw new InstanceNotFoundException(name);
+ *
+ * // Extract the name of the property that the MBean corresponds to
+ * String propName = ObjectName.unquote(name.getKeyProperty("name"));
+ * if (System.getProperty(propName) == null)
+ * throw new InstanceNotFoundException(name);
+ *
+ * // Construct and return a transient MBean object
+ * PropertyMBean propMBean = new PropertyImpl(propName);
+ * return new StandardMBean(propMBean, PropertyMBean.class, false);
+ * }
+ *
+ * @Override
+ * protected {@code Set
+ *
+ *
+ * public class PropsMBS {
+ * ...as above...
+ *
+ * private final {@link VirtualEventManager} vem = new VirtualEventManager();
+ *
+ * @Override
+ * public NotificationEmitter {@link #getNotificationEmitterFor
+ * getNotificationEmitterFor}(
+ * ObjectName name) throws InstanceNotFoundException {
+ * getDynamicMBeanFor(name); // check that the name is valid
+ * return vem.{@link VirtualEventManager#getNotificationEmitterFor
+ * getNotificationEmitterFor}(name);
+ * }
+ *
+ * public void propertyChanged(String name, String newValue) {
+ * ObjectName objectName = newObjectName(
+ * "com.example:type=Property,name=" + ObjectName.quote(name));
+ * Notification n = new Notification(
+ * "com.example.property.changed", objectName, 0L,
+ * "Property " + name + " changed");
+ * n.setUserData(newValue);
+ * vem.{@link VirtualEventManager#publish publish}(objectName, n);
+ * }
+ * }
+ *
+ *
+ * MBean creation and deletion
+ *
+ * Notifications
+ *
+ * (name)
returns an object that is a
+ * {@link NotificationEmitter}. That is appropriate if
+ * {@code getDynamicMBeanFor}(name)
always returns the
+ * same object for the same {@code name}. But with
+ * Virtual MBeans, every call to {@code getDynamicMBeanFor} returns a new object,
+ * which is discarded as soon as the MBean request has finished.
+ * So a listener added to that object would be immediately forgotten.
+ * private final VirtualEventManager vem = new VirtualEventManager();
+ *
+ * @Override
+ * public NotificationEmitter getNotificationEmitterFor(
+ * ObjectName name) throws InstanceNotFoundException {
+ * // Check that the name is a valid Virtual MBean.
+ * // This is the easiest way to do that, but not always the
+ * // most efficient:
+ * getDynamicMBeanFor(name);
+ *
+ * // Return an object that supports add/removeNotificationListener
+ * // through the VirtualEventManager.
+ * return vem.getNotificationEmitterFor(name);
+ * }
+ *
+ *
+ * (name, n)
. See the example
+ * above.
+ *
+ *
+ * @return the names of all MBeans handled by this object.
+ */
+ protected abstract Set
Subclasses may redefine this method to provide an implementation.
+ * All the various flavors of {@code MBeanServer.createMBean} methods
+ * will eventually call this method. A subclass that wishes to
+ * support MBean creation through {@code createMBean} thus only
+ * needs to provide an implementation for this one method.
+ *
+ * @param className The class name of the MBean to be instantiated.
+ * @param name The object name of the MBean. May be null.
+ * @param params An array containing the parameters of the
+ * constructor to be invoked.
+ * @param signature An array containing the signature of the
+ * constructor to be invoked.
+ * @param loaderName The object name of the class loader to be used.
+ * @param useCLR This parameter is {@code true} when this method
+ * is called from one of the {@code MBeanServer.createMBean} methods
+ * whose signature does not include the {@code ObjectName} of an
+ * MBean class loader to use for loading the MBean class.
+ *
+ * @return An ObjectInstance
, containing the
+ * ObjectName
and the Java class name of the newly
+ * instantiated MBean. If the contained ObjectName
+ * is n
, the contained Java class name is
+ * {@link javax.management.MBeanServer#getMBeanInfo
+ * getMBeanInfo(n)}.getClassName()
.
+ *
+ * @exception ReflectionException Wraps a
+ * java.lang.ClassNotFoundException
or a
+ * java.lang.Exception
that occurred when trying to
+ * invoke the MBean's constructor.
+ * @exception InstanceAlreadyExistsException The MBean is already
+ * under the control of the MBean server.
+ * @exception MBeanRegistrationException The
+ * preRegister
(MBeanRegistration
+ * interface) method of the MBean has thrown an exception. The
+ * MBean will not be registered.
+ * @exception MBeanException The constructor of the MBean has
+ * thrown an exception
+ * @exception NotCompliantMBeanException This class is not a JMX
+ * compliant MBean
+ * @exception InstanceNotFoundException The specified class loader
+ * is not registered in the MBean server.
+ * @exception RuntimeOperationsException Wraps either:
+ *
java.lang.IllegalArgumentException
: The className
+ * passed in parameter is null, the ObjectName
passed in
+ * parameter contains a pattern or no ObjectName
is specified
+ * for the MBean; orAttempts to determine whether the named MBean should be + * considered as an instance of a given class. The default implementation + * of this method calls {@link #getDynamicMBeanFor getDynamicMBeanFor(name)} + * to get an MBean object. Then its behaviour is the same as the standard + * {@link MBeanServer#isInstanceOf MBeanServer.isInstanceOf} method.
+ * + * {@inheritDoc} + */ + public boolean isInstanceOf(ObjectName name, String className) + throws InstanceNotFoundException { + + final DynamicMBean instance = nonNullMBeanFor(name); + + try { + final String mbeanClassName = instance.getMBeanInfo().getClassName(); + + if (mbeanClassName.equals(className)) + return true; + + final Object resource; + final ClassLoader cl; + if (instance instanceof DynamicWrapperMBean) { + DynamicWrapperMBean d = (DynamicWrapperMBean) instance; + resource = d.getWrappedObject(); + cl = d.getWrappedClassLoader(); + } else { + resource = instance; + cl = instance.getClass().getClassLoader(); + } + + final Class> classNameClass = Class.forName(className, false, cl); + + if (classNameClass.isInstance(resource)) + return true; + + if (classNameClass == NotificationBroadcaster.class || + classNameClass == NotificationEmitter.class) { + try { + getNotificationEmitterFor(name); + return true; + } catch (Exception x) { + LOG.finest("MBean " + name + + " is not a notification emitter. Ignoring: "+x); + return false; + } + } + + final Class> resourceClass = Class.forName(mbeanClassName, false, cl); + return classNameClass.isAssignableFrom(resourceClass); + } catch (Exception x) { + /* Could be SecurityException or ClassNotFoundException */ + LOG.logp(Level.FINEST, + MBeanServerSupport.class.getName(), + "isInstanceOf", "Exception calling isInstanceOf", x); + return false; + } + } + + /** + * {@inheritDoc} + * + *The default implementation of this method returns the string + * "DefaultDomain".
+ */ + public String getDefaultDomain() { + return "DefaultDomain"; + } + + /** + * {@inheritDoc} + * + *The default implementation of this method returns + * {@link #getNames()}.size().
+ */ + public Integer getMBeanCount() { + return getNames().size(); + } + + /** + * {@inheritDoc} + * + *The default implementation of this method first calls {@link #getNames + * getNames()} to get a list of all MBean names, + * and from this set of names, derives the set of domains which contain + * MBeans.
+ */ + public String[] getDomains() { + final SetThe default implementation of this method will first + * call {@link + * #getDynamicMBeanFor getDynamicMBeanFor(name)} to obtain a handle + * to the named MBean, + * and then call {@link DynamicMBean#getAttribute getAttribute} + * on that {@link DynamicMBean} handle.
+ * + * @throws RuntimeOperationsException {@inheritDoc} + */ + public Object getAttribute(ObjectName name, String attribute) + throws MBeanException, AttributeNotFoundException, + InstanceNotFoundException, ReflectionException { + final DynamicMBean mbean = nonNullMBeanFor(name); + return mbean.getAttribute(attribute); + } + + /** + * {@inheritDoc} + * + *The default implementation of this method will first + * call {@link #getDynamicMBeanFor getDynamicMBeanFor(name)} + * to obtain a handle to the named MBean, + * and then call {@link DynamicMBean#setAttribute setAttribute} + * on that {@link DynamicMBean} handle.
+ * + * @throws RuntimeOperationsException {@inheritDoc} + */ + public void setAttribute(ObjectName name, Attribute attribute) + throws InstanceNotFoundException, AttributeNotFoundException, + InvalidAttributeValueException, MBeanException, + ReflectionException { + final DynamicMBean mbean = nonNullMBeanFor(name); + mbean.setAttribute(attribute); + } + + /** + * {@inheritDoc} + * + *The default implementation of this method will first + * call {@link #getDynamicMBeanFor getDynamicMBeanFor(name)} to obtain a + * handle to the named MBean, + * and then call {@link DynamicMBean#getAttributes getAttributes} + * on that {@link DynamicMBean} handle.
+ * + * @throws RuntimeOperationsException {@inheritDoc} + */ + public AttributeList getAttributes(ObjectName name, + String[] attributes) throws InstanceNotFoundException, + ReflectionException { + final DynamicMBean mbean = nonNullMBeanFor(name); + return mbean.getAttributes(attributes); + } + + /** + * {@inheritDoc} + * + *The default implementation of this method will first + * call {@link #getDynamicMBeanFor getDynamicMBeanFor(name)} to obtain a + * handle to the named MBean, + * and then call {@link DynamicMBean#setAttributes setAttributes} + * on that {@link DynamicMBean} handle.
+ * + * @throws RuntimeOperationsException {@inheritDoc} + */ + public AttributeList setAttributes(ObjectName name, AttributeList attributes) + throws InstanceNotFoundException, ReflectionException { + final DynamicMBean mbean = nonNullMBeanFor(name); + return mbean.setAttributes(attributes); + } + + /** + * {@inheritDoc} + * + *The default implementation of this method will first + * call {@link #getDynamicMBeanFor getDynamicMBeanFor(name)} to obtain a + * handle to the named MBean, + * and then call {@link DynamicMBean#invoke invoke} + * on that {@link DynamicMBean} handle.
+ */ + public Object invoke(ObjectName name, String operationName, + Object[] params, String[] signature) + throws InstanceNotFoundException, MBeanException, + ReflectionException { + final DynamicMBean mbean = nonNullMBeanFor(name); + return mbean.invoke(operationName, params, signature); + } + + /** + * {@inheritDoc} + * + *The default implementation of this method will first + * call {@link #getDynamicMBeanFor getDynamicMBeanFor(name)} to obtain a + * handle to the named MBean, + * and then call {@link DynamicMBean#getMBeanInfo getMBeanInfo} + * on that {@link DynamicMBean} handle.
+ */ + public MBeanInfo getMBeanInfo(ObjectName name) + throws InstanceNotFoundException, IntrospectionException, + ReflectionException { + final DynamicMBean mbean = nonNullMBeanFor(name); + return mbean.getMBeanInfo(); + } + + /** + * {@inheritDoc} + * + *The default implementation of this method will call + * {@link #getDynamicMBeanFor getDynamicMBeanFor(name)}.{@link DynamicMBean#getMBeanInfo getMBeanInfo()}.{@link MBeanInfo#getClassName getClassName()} to get the + * class name to combine with {@code name} to produce a new + * {@code ObjectInstance}.
+ */ + public ObjectInstance getObjectInstance(ObjectName name) + throws InstanceNotFoundException { + final DynamicMBean mbean = nonNullMBeanFor(name); + final String className = mbean.getMBeanInfo().getClassName(); + return new ObjectInstance(name, className); + } + + /** + * {@inheritDoc} + * + *The default implementation of this method will first call {@link + * #getDynamicMBeanFor getDynamicMBeanFor(name)} to obtain a handle to the + * named MBean. If {@code getDynamicMBeanFor} returns an object, {@code + * isRegistered} will return true. If {@code getDynamicMBeanFor} returns + * null or throws {@link InstanceNotFoundException}, {@code isRegistered} + * will return false.
+ * + * @throws RuntimeOperationsException {@inheritDoc} + */ + public boolean isRegistered(ObjectName name) { + try { + final DynamicMBean mbean = getDynamicMBeanFor(name); + return mbean!=null; + } catch (InstanceNotFoundException x) { + if (LOG.isLoggable(Level.FINEST)) + LOG.finest("MBean "+name+" is not registered: "+x); + return false; + } + } + + + /** + * {@inheritDoc} + * + *The default implementation of this method will first + * call {@link #queryNames queryNames} + * to get a list of all matching MBeans, and then, for each returned name, + * call {@link #getObjectInstance getObjectInstance(name)}.
+ */ + public SetThe default implementation of this method calls {@link #getMatchingNames + * getMatchingNames(pattern)} to obtain a list of MBeans matching + * the given name pattern. If the {@code query} parameter is null, + * this will be the result. Otherwise, it will evaluate the + * {@code query} parameter for each of the returned names, exactly + * as an {@code MBeanServer} would. This might result in + * {@link #getDynamicMBeanFor getDynamicMBeanFor} being called + * several times for each returned name.
+ */ + public SetAdds a listener to a registered MBean. A notification emitted by + * the MBean will be forwarded to the listener.
+ * + *This implementation calls + * {@link #getNotificationEmitterFor getNotificationEmitterFor} + * and invokes {@code addNotificationListener} on the + * {@link NotificationEmitter} it returns. + * + * @see #getDynamicMBeanFor getDynamicMBeanFor + * @see #getNotificationEmitterFor getNotificationEmitterFor + */ + public void addNotificationListener(ObjectName name, + NotificationListener listener, NotificationFilter filter, + Object handback) throws InstanceNotFoundException { + final NotificationEmitter emitter = + getNonNullNotificationEmitterFor(name); + emitter.addNotificationListener(listener, filter, handback); + } + + /** + * {@inheritDoc} + * + *
This implementation calls + * {@link #getNotificationEmitterFor getNotificationEmitterFor} + * and invokes {@code removeNotificationListener} on the + * {@link NotificationEmitter} it returns. + * @see #getDynamicMBeanFor getDynamicMBeanFor + * @see #getNotificationEmitterFor getNotificationEmitterFor + */ + public void removeNotificationListener(ObjectName name, + NotificationListener listener) + throws InstanceNotFoundException, ListenerNotFoundException { + final NotificationEmitter emitter = + getNonNullNotificationEmitterFor(name); + emitter.removeNotificationListener(listener); + } + + /** + * {@inheritDoc} + * + *
This implementation calls + * {@link #getNotificationEmitterFor getNotificationEmitterFor} + * and invokes {@code removeNotificationListener} on the + * {@link NotificationEmitter} it returns. + * @see #getDynamicMBeanFor getDynamicMBeanFor + * @see #getNotificationEmitterFor getNotificationEmitterFor + */ + public void removeNotificationListener(ObjectName name, + NotificationListener listener, NotificationFilter filter, + Object handback) + throws InstanceNotFoundException, ListenerNotFoundException { + NotificationEmitter emitter = + getNonNullNotificationEmitterFor(name); + emitter.removeNotificationListener(listener); + } + + + /** + *
Adds a listener to a registered MBean.
+ * + *The default implementation of this method first calls + * {@link #getDynamicMBeanFor getDynamicMBeanFor(listenerName)}. + * If that successfully returns an object, call it {@code + * mbean}, then (a) if {@code mbean} is an instance of {@link + * NotificationListener} then this method calls {@link + * #addNotificationListener(ObjectName, NotificationListener, + * NotificationFilter, Object) addNotificationListener(name, mbean, filter, + * handback)}, otherwise (b) this method throws an exception as specified + * for this case.
+ * + *This default implementation is not appropriate for Virtual MBeans, + * although that only matters if the object returned by {@code + * getDynamicMBeanFor} can be an instance of + * {@code NotificationListener}.
+ * + * @throws RuntimeOperationsException {@inheritDoc} + */ + public void addNotificationListener(ObjectName name, ObjectName listenerName, + NotificationFilter filter, Object handback) + throws InstanceNotFoundException { + NotificationListener listener = getListenerMBean(listenerName); + addNotificationListener(name, listener, filter, handback); + } + + /** + * {@inheritDoc} + * + *This operation is not supported in this base class implementation. + * The default implementation of this method always throws + * {@link RuntimeOperationsException} wrapping + * {@link UnsupportedOperationException}.
+ * + * @throws javax.management.RuntimeOperationsException wrapping + * {@link UnsupportedOperationException} + */ + public void removeNotificationListener(ObjectName name, + ObjectName listenerName) + throws InstanceNotFoundException, ListenerNotFoundException { + NotificationListener listener = getListenerMBean(listenerName); + removeNotificationListener(name, listener); + } + + /** + * {@inheritDoc} + * + *This operation is not supported in this base class implementation. + * The default implementation of this method always throws + * {@link RuntimeOperationsException} wrapping + * {@link UnsupportedOperationException}.
+ * + * @throws javax.management.RuntimeOperationsException wrapping + * {@link UnsupportedOperationException} + */ + public void removeNotificationListener(ObjectName name, + ObjectName listenerName, NotificationFilter filter, + Object handback) + throws InstanceNotFoundException, ListenerNotFoundException { + NotificationListener listener = getListenerMBean(listenerName); + removeNotificationListener(name, listener, filter, handback); + } + + private NotificationListener getListenerMBean(ObjectName listenerName) + throws InstanceNotFoundException { + Object mbean = getDynamicMBeanFor(listenerName); + if (mbean instanceof NotificationListener) + return (NotificationListener) mbean; + else { + throw newIllegalArgumentException( + "MBean is not a NotificationListener: " + listenerName); + } + } + + + /** + * {@inheritDoc} + * + *This operation is not supported in this base class implementation. + * The default implementation of this method always throws + * {@link InstanceNotFoundException} wrapping + * {@link UnsupportedOperationException}.
+ * + * @return the default implementation of this method never returns. + * @throws javax.management.RuntimeOperationsException wrapping + * {@link UnsupportedOperationException} + */ + public ClassLoader getClassLoader(ObjectName loaderName) + throws InstanceNotFoundException { + final UnsupportedOperationException failed = + new UnsupportedOperationException("getClassLoader"); + final InstanceNotFoundException x = + new InstanceNotFoundException(String.valueOf(loaderName)); + x.initCause(failed); + throw x; + } + + /** + * {@inheritDoc} + * + *The default implementation of this method calls + * {@link #getDynamicMBeanFor getDynamicMBeanFor(mbeanName)} and applies + * the logic just described to the result.
+ */ + public ClassLoader getClassLoaderFor(ObjectName mbeanName) + throws InstanceNotFoundException { + final DynamicMBean mbean = nonNullMBeanFor(mbeanName); + if (mbean instanceof DynamicWrapperMBean) + return ((DynamicWrapperMBean) mbean).getWrappedClassLoader(); + else + return mbean.getClass().getClassLoader(); + } + + /** + * {@inheritDoc} + * + *The default implementation of this method returns a + * {@link ClassLoaderRepository} containing exactly one loader, + * the {@linkplain Thread#getContextClassLoader() context class loader} + * for the current thread. + * Subclasses can override this method to return a different + * {@code ClassLoaderRepository}.
+ */ + public ClassLoaderRepository getClassLoaderRepository() { + // We return a new ClassLoaderRepository each time this + // method is called. This is by design, because the + // SingletonClassLoaderRepository is a very small object and + // getClassLoaderRepository() will not be called very often + // (the connector server calls it once) - in the context of + // MBeanServerSupport there's a very good chance that this method will + // *never* be called. + ClassLoader ccl = Thread.currentThread().getContextClassLoader(); + return Util.getSingleClassLoaderRepository(ccl); + } + + + /** + * {@inheritDoc} + * + *This operation is not supported in this base class implementation. + * The default implementation of this method always throws + * {@link RuntimeOperationsException} wrapping + * {@link UnsupportedOperationException}.
+ * @throws javax.management.RuntimeOperationsException wrapping + * {@link UnsupportedOperationException} + */ + public ObjectInstance registerMBean(Object object, ObjectName name) + throws InstanceAlreadyExistsException, MBeanRegistrationException, + NotCompliantMBeanException { + throw newUnsupportedException("registerMBean"); + } + + /** + * {@inheritDoc} + * + *This operation is not supported in this base class implementation. + * The default implementation of this method always throws + * {@link RuntimeOperationsException} wrapping + * {@link UnsupportedOperationException}. + * @throws javax.management.RuntimeOperationsException wrapping + * {@link UnsupportedOperationException} + */ + public void unregisterMBean(ObjectName name) + throws InstanceNotFoundException, MBeanRegistrationException { + throw newUnsupportedException("unregisterMBean"); + } + + /** + * Calls {@link #createMBean(String, ObjectName, + * ObjectName, Object[], String[], boolean) + * createMBean(className, name, null, params, signature, true)}; + */ + public final ObjectInstance createMBean(String className, ObjectName name, + Object[] params, String[] signature) + throws ReflectionException, InstanceAlreadyExistsException, + MBeanRegistrationException, MBeanException, + NotCompliantMBeanException { + try { + return safeCreateMBean(className, name, null, params, signature, true); + } catch (InstanceNotFoundException ex) { + // should not happen! + throw new MBeanException(ex, "Unexpected exception: " + ex); + } + } + + /** + * Calls {@link #createMBean(String, ObjectName, + * ObjectName, Object[], String[], boolean) + * createMBean(className,name, loaderName, params, signature, false)}; + */ + public final ObjectInstance createMBean(String className, ObjectName name, + ObjectName loaderName, Object[] params, String[] signature) + throws ReflectionException, InstanceAlreadyExistsException, + MBeanRegistrationException, MBeanException, + NotCompliantMBeanException, InstanceNotFoundException { + return safeCreateMBean(className, name, loaderName, params, signature, false); + } + + /** + * Calls {@link #createMBean(String, ObjectName, + * ObjectName, Object[], String[], boolean) + * createMBean(className, name, null, null, null, true)}; + */ + public final ObjectInstance createMBean(String className, ObjectName name) + throws ReflectionException, InstanceAlreadyExistsException, + MBeanRegistrationException, MBeanException, + NotCompliantMBeanException { + try { + return safeCreateMBean(className, name, null, null, null, true); + } catch (InstanceNotFoundException ex) { + // should not happen! + throw new MBeanException(ex, "Unexpected exception: " + ex); + } + } + + /** + * Calls {@link #createMBean(String, ObjectName, + * ObjectName, Object[], String[], boolean) + * createMBean(className, name, loaderName, null, null, false)}; + */ + public final ObjectInstance createMBean(String className, ObjectName name, + ObjectName loaderName) + throws ReflectionException, InstanceAlreadyExistsException, + MBeanRegistrationException, MBeanException, + NotCompliantMBeanException, InstanceNotFoundException { + return safeCreateMBean(className, name, loaderName, null, null, false); + } + + // make sure all exceptions are correctly wrapped in a JMXException + private ObjectInstance safeCreateMBean(String className, + ObjectName name, ObjectName loaderName, Object[] params, + String[] signature, boolean useRepository) + throws ReflectionException, InstanceAlreadyExistsException, + MBeanRegistrationException, MBeanException, + NotCompliantMBeanException, InstanceNotFoundException { + try { + return createMBean(className, name, loaderName, params, + signature, useRepository); + } catch (ReflectionException x) { throw x; + } catch (InstanceAlreadyExistsException x) { throw x; + } catch (MBeanRegistrationException x) { throw x; + } catch (MBeanException x) { throw x; + } catch (NotCompliantMBeanException x) { throw x; + } catch (InstanceNotFoundException x) { throw x; + } catch (SecurityException x) { throw x; + } catch (JMRuntimeException x) { throw x; + } catch (RuntimeException x) { + throw new RuntimeOperationsException(x, x.toString()); + } catch (Exception x) { + throw new MBeanException(x, x.toString()); + } + } + + + /** + * {@inheritDoc} + * + *
This operation is not supported in this base class implementation. + * The default implementation of this method always throws + * {@link RuntimeOperationsException} wrapping + * {@link UnsupportedOperationException}.
+ * + * @throws javax.management.RuntimeOperationsException wrapping + * {@link UnsupportedOperationException} + */ + public Object instantiate(String className) + throws ReflectionException, MBeanException { + throw new UnsupportedOperationException("Not applicable."); + } + + /** + * {@inheritDoc} + * + *This operation is not supported in this base class implementation. + * The default implementation of this method always throws + * {@link RuntimeOperationsException} wrapping + * {@link UnsupportedOperationException}.
+ * + * @throws javax.management.RuntimeOperationsException wrapping + * {@link UnsupportedOperationException} + */ + public Object instantiate(String className, ObjectName loaderName) + throws ReflectionException, MBeanException, + InstanceNotFoundException { + throw new UnsupportedOperationException("Not applicable."); + } + + /** + * {@inheritDoc} + * + *This operation is not supported in this base class implementation. + * The default implementation of this method always throws + * {@link RuntimeOperationsException} wrapping + * {@link UnsupportedOperationException}.
+ * + * @throws javax.management.RuntimeOperationsException wrapping + * {@link UnsupportedOperationException} + */ + public Object instantiate(String className, Object[] params, + String[] signature) throws ReflectionException, MBeanException { + throw new UnsupportedOperationException("Not applicable."); + } + + /** + * {@inheritDoc} + * + *This operation is not supported in this base class implementation. + * The default implementation of this method always throws + * {@link RuntimeOperationsException} wrapping + * {@link UnsupportedOperationException}.
+ * + * @throws javax.management.RuntimeOperationsException wrapping + * {@link UnsupportedOperationException} + */ + public Object instantiate(String className, ObjectName loaderName, + Object[] params, String[] signature) + throws ReflectionException, MBeanException, + InstanceNotFoundException { + throw new UnsupportedOperationException("Not applicable."); + } + + + /** + * {@inheritDoc} + * + *This operation is not supported in this base class implementation. + * The default implementation of this method always throws + * {@link RuntimeOperationsException} wrapping + * {@link UnsupportedOperationException}.
+ * + * @throws javax.management.RuntimeOperationsException wrapping + * {@link UnsupportedOperationException} + */ + @Deprecated + public ObjectInputStream deserialize(ObjectName name, byte[] data) + throws InstanceNotFoundException, OperationsException { + throw new UnsupportedOperationException("Not applicable."); + } + + /** + * {@inheritDoc} + * + *This operation is not supported in this base class implementation. + * The default implementation of this method always throws + * {@link RuntimeOperationsException} wrapping + * {@link UnsupportedOperationException}.
+ * + * @throws javax.management.RuntimeOperationsException wrapping + * {@link UnsupportedOperationException} + */ + @Deprecated + public ObjectInputStream deserialize(String className, byte[] data) + throws OperationsException, ReflectionException { + throw new UnsupportedOperationException("Not applicable."); + } + + /** + * {@inheritDoc} + * + *This operation is not supported in this base class implementation. + * The default implementation of this method always throws + * {@link RuntimeOperationsException} wrapping + * {@link UnsupportedOperationException}.
+ * + * @throws javax.management.RuntimeOperationsException wrapping + * {@link UnsupportedOperationException} + */ + @Deprecated + public ObjectInputStream deserialize(String className, + ObjectName loaderName, byte[] data) + throws InstanceNotFoundException, OperationsException, + ReflectionException { + throw new UnsupportedOperationException("Not applicable."); + } + + + // Calls getDynamicMBeanFor, and throws an InstanceNotFoundException + // if the returned mbean is null. + // The DynamicMBean returned by this method is thus guaranteed to be + // non null. + // + private DynamicMBean nonNullMBeanFor(ObjectName name) + throws InstanceNotFoundException { + if (name == null) + throw newIllegalArgumentException("Null ObjectName"); + if (name.getDomain().equals("")) { + String defaultDomain = getDefaultDomain(); + try { + // XXX change to ObjectName.switchDomain + // current code DOES NOT PRESERVE the order of keys + name = new ObjectName(defaultDomain, name.getKeyPropertyList()); + } catch (Exception e) { + throw newIllegalArgumentException( + "Illegal default domain: " + defaultDomain); + } + } + final DynamicMBean mbean = getDynamicMBeanFor(name); + if (mbean!=null) return mbean; + throw new InstanceNotFoundException(String.valueOf(name)); + } + + static RuntimeException newUnsupportedException(String operation) { + return new RuntimeOperationsException( + new UnsupportedOperationException( + operation+": Not supported in this namespace")); + } + + static RuntimeException newIllegalArgumentException(String msg) { + return new RuntimeOperationsException( + new IllegalArgumentException(msg)); + } + +} diff --git a/jdk/src/share/classes/com/sun/jmx/interceptor/SingleMBeanForwarder.java b/jdk/src/share/classes/com/sun/jmx/interceptor/SingleMBeanForwarder.java new file mode 100644 index 00000000000..ec53998f51a --- /dev/null +++ b/jdk/src/share/classes/com/sun/jmx/interceptor/SingleMBeanForwarder.java @@ -0,0 +1,414 @@ +/* + * Copyright 2008 Sun Microsystems, Inc. All Rights Reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 only, as + * published by the Free Software Foundation. Sun designates this + * particular file as subject to the "Classpath" exception as provided + * by Sun in the LICENSE file that accompanied this code. + * + * This code is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * version 2 for more details (a copy is included in the LICENSE file that + * accompanied this code). + * + * You should have received a copy of the GNU General Public License version + * 2 along with this work; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, + * CA 95054 USA or visit www.sun.com if you need additional information or + * have any questions. + */ + +package com.sun.jmx.interceptor; + +import com.sun.jmx.mbeanserver.Util; +import java.util.Arrays; +import java.util.Collections; +import java.util.Set; +import java.util.TreeSet; +import javax.management.Attribute; +import javax.management.AttributeList; +import javax.management.AttributeNotFoundException; +import javax.management.DynamicMBean; +import javax.management.InstanceAlreadyExistsException; +import javax.management.InstanceNotFoundException; +import javax.management.IntrospectionException; +import javax.management.InvalidAttributeValueException; +import javax.management.ListenerNotFoundException; +import javax.management.MBeanException; +import javax.management.MBeanInfo; +import javax.management.MBeanRegistrationException; +import javax.management.MBeanServer; +import javax.management.NotCompliantMBeanException; +import javax.management.NotificationEmitter; +import javax.management.NotificationFilter; +import javax.management.NotificationListener; +import javax.management.ObjectInstance; +import javax.management.ObjectName; +import javax.management.QueryExp; +import javax.management.ReflectionException; +import javax.management.remote.IdentityMBeanServerForwarder; + +public class SingleMBeanForwarder extends IdentityMBeanServerForwarder { + + private final ObjectName mbeanName; + private DynamicMBean mbean; + + private MBeanServer mbeanMBS = new MBeanServerSupport() { + + @Override + public DynamicMBean getDynamicMBeanFor(ObjectName name) + throws InstanceNotFoundException { + if (mbeanName.equals(name)) { + return mbean; + } else { + throw new InstanceNotFoundException(name.toString()); + } + } + + @Override + protected Set+ This API is a Sun internal API and is subject to changes without notice. +