8199138: Add RISC-V support to Zero

Reviewed-by: erikj, stuefe
This commit is contained in:
John Paul Adrian Glaubitz 2020-04-07 08:45:01 +02:00
parent b317d0ee39
commit edc4ffe54b
2 changed files with 15 additions and 1 deletions

View file

@ -1851,6 +1851,9 @@ void * os::dll_load(const char *filename, char *ebuf, int ebuflen) {
#ifndef EM_AARCH64
#define EM_AARCH64 183 /* ARM AARCH64 */
#endif
#ifndef EM_RISCV
#define EM_RISCV 243 /* RISC-V */
#endif
static const arch_t arch_array[]={
{EM_386, EM_386, ELFCLASS32, ELFDATA2LSB, (char*)"IA 32"},
@ -1877,6 +1880,7 @@ void * os::dll_load(const char *filename, char *ebuf, int ebuflen) {
{EM_PARISC, EM_PARISC, ELFCLASS32, ELFDATA2MSB, (char*)"PARISC"},
{EM_68K, EM_68K, ELFCLASS32, ELFDATA2MSB, (char*)"M68k"},
{EM_AARCH64, EM_AARCH64, ELFCLASS64, ELFDATA2LSB, (char*)"AARCH64"},
{EM_RISCV, EM_RISCV, ELFCLASS64, ELFDATA2LSB, (char*)"RISC-V"},
};
#if (defined IA32)
@ -1911,9 +1915,11 @@ void * os::dll_load(const char *filename, char *ebuf, int ebuflen) {
static Elf32_Half running_arch_code=EM_68K;
#elif (defined SH)
static Elf32_Half running_arch_code=EM_SH;
#elif (defined RISCV)
static Elf32_Half running_arch_code=EM_RISCV;
#else
#error Method os::dll_load requires that one of following is defined:\
AARCH64, ALPHA, ARM, AMD64, IA32, IA64, M68K, MIPS, MIPSEL, PARISC, __powerpc__, __powerpc64__, S390, SH, __sparc
AARCH64, ALPHA, ARM, AMD64, IA32, IA64, M68K, MIPS, MIPSEL, PARISC, __powerpc__, __powerpc64__, RISCV, S390, SH, __sparc
#endif
// Identify compatibility class for VM's architecture and library's architecture