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8016697: Use stubs to implement safefetch

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Implement Safefetch as stub routines. This reduces compiler and os dependencies.

Reviewed-by: twisti, kvn
This commit is contained in:
Goetz Lindenmaier 2013-06-20 15:02:05 +02:00
parent b5efe058f7
commit ef69ce852c
21 changed files with 231 additions and 304 deletions
Download patch file Download diff file Expand all files Collapse all files

18
hotspot/src/os_cpu/bsd_x86/vm/bsd_x86_32.s
View file

@ -63,24 +63,6 @@ SYMBOL(fixcw):
popl %eax
ret
.globl SYMBOL(SafeFetch32), SYMBOL(Fetch32PFI), SYMBOL(Fetch32Resume)
.globl SYMBOL(SafeFetchN)
## TODO: avoid exposing Fetch32PFI and Fetch32Resume.
## Instead, the signal handler would call a new SafeFetchTriage(FaultingEIP)
## routine to vet the address. If the address is the faulting LD then
## SafeFetchTriage() would return the resume-at EIP, otherwise null.
ELF_TYPE(SafeFetch32,@function)
.p2align 4,,15
SYMBOL(SafeFetch32):
SYMBOL(SafeFetchN):
movl 0x8(%esp), %eax
movl 0x4(%esp), %ecx
SYMBOL(Fetch32PFI):
movl (%ecx), %eax
SYMBOL(Fetch32Resume):
ret
.globl SYMBOL(SpinPause)
ELF_TYPE(SpinPause,@function)
.p2align 4,,15

22
hotspot/src/os_cpu/bsd_x86/vm/bsd_x86_64.s
View file

@ -46,28 +46,6 @@
.text
.globl SYMBOL(SafeFetch32), SYMBOL(Fetch32PFI), SYMBOL(Fetch32Resume)
.p2align 4,,15
ELF_TYPE(SafeFetch32,@function)
// Prototype: int SafeFetch32 (int * Adr, int ErrValue)
SYMBOL(SafeFetch32):
movl %esi, %eax
SYMBOL(Fetch32PFI):
movl (%rdi), %eax
SYMBOL(Fetch32Resume):
ret
.globl SYMBOL(SafeFetchN), SYMBOL(FetchNPFI), SYMBOL(FetchNResume)
.p2align 4,,15
ELF_TYPE(SafeFetchN,@function)
// Prototype: intptr_t SafeFetchN (intptr_t * Adr, intptr_t ErrValue)
SYMBOL(SafeFetchN):
movq %rsi, %rax
SYMBOL(FetchNPFI):
movq (%rdi), %rax
SYMBOL(FetchNResume):
ret
.globl SYMBOL(SpinPause)
.p2align 4,,15
ELF_TYPE(SpinPause,@function)

19
hotspot/src/os_cpu/bsd_x86/vm/os_bsd_x86.cpp
View file

@ -385,13 +385,6 @@ enum {
trap_page_fault = 0xE
};
extern "C" void Fetch32PFI () ;
extern "C" void Fetch32Resume () ;
#ifdef AMD64
extern "C" void FetchNPFI () ;
extern "C" void FetchNResume () ;
#endif // AMD64
extern "C" JNIEXPORT int
JVM_handle_bsd_signal(int sig,
siginfo_t* info,
@ -454,16 +447,10 @@ JVM_handle_bsd_signal(int sig,
if (info != NULL && uc != NULL && thread != NULL) {
pc = (address) os::Bsd::ucontext_get_pc(uc);
if (pc == (address) Fetch32PFI) {
uc->context_pc = intptr_t(Fetch32Resume) ;
return 1 ;
if (StubRoutines::is_safefetch_fault(pc)) {
uc->context_pc = intptr_t(StubRoutines::continuation_for_safefetch_fault(pc));
return 1;
}
#ifdef AMD64
if (pc == (address) FetchNPFI) {
uc->context_pc = intptr_t (FetchNResume) ;
return 1 ;
}
#endif // AMD64
// Handle ALL stack overflow variations here
if (sig == SIGSEGV || sig == SIGBUS) {

36
hotspot/src/os_cpu/linux_sparc/vm/linux_sparc.s
View file

@ -21,42 +21,6 @@
# questions.
#
# Prototype: int SafeFetch32 (int * adr, int ErrValue)
# The "ld" at Fetch32 is potentially faulting instruction.
# If the instruction traps the trap handler will arrange
# for control to resume at Fetch32Resume.
# By convention with the trap handler we ensure there is a non-CTI
# instruction in the trap shadow.
.globl SafeFetch32, Fetch32PFI, Fetch32Resume
.globl SafeFetchN
.align 32
.type SafeFetch32,@function
SafeFetch32:
mov %o0, %g1
mov %o1, %o0
Fetch32PFI:
# <-- Potentially faulting instruction
ld [%g1], %o0
Fetch32Resume:
nop
retl
nop
.globl SafeFetchN, FetchNPFI, FetchNResume
.type SafeFetchN,@function
.align 32
SafeFetchN:
mov %o0, %g1
mov %o1, %o0
FetchNPFI:
ldn [%g1], %o0
FetchNResume:
nop
retl
nop
# Possibilities:
# -- membar
# -- CAS (SP + BIAS, G0, G0)

13
hotspot/src/os_cpu/linux_sparc/vm/os_linux_sparc.cpp
View file

@ -366,18 +366,9 @@ intptr_t* os::Linux::ucontext_get_fp(ucontext_t *uc) {
// Utility functions
extern "C" void Fetch32PFI();
extern "C" void Fetch32Resume();
extern "C" void FetchNPFI();
extern "C" void FetchNResume();
inline static bool checkPrefetch(sigcontext* uc, address pc) {
if (pc == (address) Fetch32PFI) {
set_cont_address(uc, address(Fetch32Resume));
return true;
}
if (pc == (address) FetchNPFI) {
set_cont_address(uc, address(FetchNResume));
if (StubRoutines::is_safefetch_fault(pc)) {
set_cont_address(uc, address(StubRoutines::continuation_for_safefetch_fault(pc)));
return true;
}
return false;

18
hotspot/src/os_cpu/linux_x86/vm/linux_x86_32.s
View file

@ -42,24 +42,6 @@
.text
.globl SafeFetch32, Fetch32PFI, Fetch32Resume
.globl SafeFetchN
## TODO: avoid exposing Fetch32PFI and Fetch32Resume.
## Instead, the signal handler would call a new SafeFetchTriage(FaultingEIP)
## routine to vet the address. If the address is the faulting LD then
## SafeFetchTriage() would return the resume-at EIP, otherwise null.
.type SafeFetch32,@function
.p2align 4,,15
SafeFetch32:
SafeFetchN:
movl 0x8(%esp), %eax
movl 0x4(%esp), %ecx
Fetch32PFI:
movl (%ecx), %eax
Fetch32Resume:
ret
.globl SpinPause
.type SpinPause,@function
.p2align 4,,15

22
hotspot/src/os_cpu/linux_x86/vm/linux_x86_64.s
View file

@ -38,28 +38,6 @@
.text
.globl SafeFetch32, Fetch32PFI, Fetch32Resume
.align 16
.type SafeFetch32,@function
// Prototype: int SafeFetch32 (int * Adr, int ErrValue)
SafeFetch32:
movl %esi, %eax
Fetch32PFI:
movl (%rdi), %eax
Fetch32Resume:
ret
.globl SafeFetchN, FetchNPFI, FetchNResume
.align 16
.type SafeFetchN,@function
// Prototype: intptr_t SafeFetchN (intptr_t * Adr, intptr_t ErrValue)
SafeFetchN:
movq %rsi, %rax
FetchNPFI:
movq (%rdi), %rax
FetchNResume:
ret
.globl SpinPause
.align 16
.type SpinPause,@function

19
hotspot/src/os_cpu/linux_x86/vm/os_linux_x86.cpp
View file

@ -209,13 +209,6 @@ enum {
trap_page_fault = 0xE
};
extern "C" void Fetch32PFI () ;
extern "C" void Fetch32Resume () ;
#ifdef AMD64
extern "C" void FetchNPFI () ;
extern "C" void FetchNResume () ;
#endif // AMD64
extern "C" JNIEXPORT int
JVM_handle_linux_signal(int sig,
siginfo_t* info,
@ -278,16 +271,10 @@ JVM_handle_linux_signal(int sig,
if (info != NULL && uc != NULL && thread != NULL) {
pc = (address) os::Linux::ucontext_get_pc(uc);
if (pc == (address) Fetch32PFI) {
uc->uc_mcontext.gregs[REG_PC] = intptr_t(Fetch32Resume) ;
return 1 ;
if (StubRoutines::is_safefetch_fault(pc)) {
uc->uc_mcontext.gregs[REG_PC] = intptr_t(StubRoutines::continuation_for_safefetch_fault(pc));
return 1;
}
#ifdef AMD64
if (pc == (address) FetchNPFI) {
uc->uc_mcontext.gregs[REG_PC] = intptr_t (FetchNResume) ;
return 1 ;
}
#endif // AMD64
#ifndef AMD64
// Halt if SI_KERNEL before more crashes get misdiagnosed as Java bugs

20
hotspot/src/os_cpu/solaris_sparc/vm/os_solaris_sparc.cpp
View file

@ -303,11 +303,6 @@ bool os::is_allocatable(size_t bytes) {
#endif
}
extern "C" void Fetch32PFI () ;
extern "C" void Fetch32Resume () ;
extern "C" void FetchNPFI () ;
extern "C" void FetchNResume () ;
extern "C" JNIEXPORT int
JVM_handle_solaris_signal(int sig, siginfo_t* info, void* ucVoid,
int abort_if_unrecognized) {
@ -379,17 +374,10 @@ JVM_handle_solaris_signal(int sig, siginfo_t* info, void* ucVoid,
npc = (address) uc->uc_mcontext.gregs[REG_nPC];
// SafeFetch() support
// Implemented with either a fixed set of addresses such
// as Fetch32*, or with Thread._OnTrap.
if (uc->uc_mcontext.gregs[REG_PC] == intptr_t(Fetch32PFI)) {
uc->uc_mcontext.gregs [REG_PC] = intptr_t(Fetch32Resume) ;
uc->uc_mcontext.gregs [REG_nPC] = intptr_t(Fetch32Resume) + 4 ;
return true ;
}
if (uc->uc_mcontext.gregs[REG_PC] == intptr_t(FetchNPFI)) {
uc->uc_mcontext.gregs [REG_PC] = intptr_t(FetchNResume) ;
uc->uc_mcontext.gregs [REG_nPC] = intptr_t(FetchNResume) + 4 ;
return true ;
if (StubRoutines::is_safefetch_fault(pc)) {
uc->uc_mcontext.gregs[REG_PC] = intptr_t(StubRoutines::continuation_for_safefetch_fault(pc));
uc->uc_mcontext.gregs[REG_nPC] = uc->uc_mcontext.gregs[REG_PC] + 4;
return 1;
}
// Handle ALL stack overflow variations here

41
hotspot/src/os_cpu/solaris_sparc/vm/solaris_sparc.s
View file

@ -21,47 +21,6 @@
!! questions.
!!
!! Prototype: int SafeFetch32 (int * adr, int ErrValue)
!! The "ld" at Fetch32 is potentially faulting instruction.
!! If the instruction traps the trap handler will arrange
!! for control to resume at Fetch32Resume.
!! By convention with the trap handler we ensure there is a non-CTI
!! instruction in the trap shadow.
!!
!! The reader might be tempted to move this service to .il.
!! Don't. Sun's CC back-end reads and optimize code emitted
!! by the .il "call", in some cases optimizing the code, completely eliding it,
!! or by moving the code from the "call site".
!! ASM better know we may use G6 for our own purposes
.register %g6, #ignore
.globl SafeFetch32
.align 32
.global Fetch32PFI, Fetch32Resume
SafeFetch32:
mov %o0, %g1
mov %o1, %o0
Fetch32PFI:
ld [%g1], %o0 !! <-- Potentially faulting instruction
Fetch32Resume:
nop
retl
nop
.globl SafeFetchN
.align 32
.globl FetchNPFI, FetchNResume
SafeFetchN:
mov %o0, %g1
mov %o1, %o0
FetchNPFI:
ldn [%g1], %o0
FetchNResume:
nop
retl
nop
!! Possibilities:
!! -- membar
!! -- CAS (SP + BIAS, G0, G0)

20
hotspot/src/os_cpu/solaris_x86/vm/os_solaris_x86.cpp
View file

@ -352,13 +352,6 @@ bool os::is_allocatable(size_t bytes) {
}
extern "C" void Fetch32PFI () ;
extern "C" void Fetch32Resume () ;
#ifdef AMD64
extern "C" void FetchNPFI () ;
extern "C" void FetchNResume () ;
#endif // AMD64
extern "C" JNIEXPORT int
JVM_handle_solaris_signal(int sig, siginfo_t* info, void* ucVoid,
int abort_if_unrecognized) {
@ -436,17 +429,10 @@ JVM_handle_solaris_signal(int sig, siginfo_t* info, void* ucVoid,
// factor me: getPCfromContext
pc = (address) uc->uc_mcontext.gregs[REG_PC];
// SafeFetch32() support
if (pc == (address) Fetch32PFI) {
uc->uc_mcontext.gregs[REG_PC] = intptr_t(Fetch32Resume) ;
return true ;
if (StubRoutines::is_safefetch_fault(pc)) {
uc->uc_mcontext.gregs[REG_PC] = intptr_t(StubRoutines::continuation_for_safefetch_fault(pc));
return true;
}
#ifdef AMD64
if (pc == (address) FetchNPFI) {
uc->uc_mcontext.gregs [REG_PC] = intptr_t(FetchNResume) ;
return true ;
}
#endif // AMD64
// Handle ALL stack overflow variations here
if (sig == SIGSEGV && info->si_code == SEGV_ACCERR) {

14
hotspot/src/os_cpu/solaris_x86/vm/solaris_x86_32.s
View file

@ -54,20 +54,6 @@ fixcw:
popl %eax
ret
.align 16
.globl SafeFetch32
.globl SafeFetchN
.globl Fetch32PFI, Fetch32Resume
SafeFetch32:
SafeFetchN:
movl 0x8(%esp), %eax
movl 0x4(%esp), %ecx
Fetch32PFI:
movl (%ecx), %eax
Fetch32Resume:
ret
.align 16
.globl SpinPause
SpinPause:

52
hotspot/src/os_cpu/solaris_x86/vm/solaris_x86_64.s
View file

@ -21,54 +21,34 @@
/ questions.
/
.globl fs_load
.globl fs_thread
.globl fs_load
.globl fs_thread
// NOTE WELL! The _Copy functions are called directly
// from server-compiler-generated code via CallLeafNoFP,
// which means that they *must* either not use floating
// point or use it in the same manner as does the server
// compiler.
// from server-compiler-generated code via CallLeafNoFP,
// which means that they *must* either not use floating
// point or use it in the same manner as does the server
// compiler.
.globl _Copy_arrayof_conjoint_bytes
.globl _Copy_conjoint_jshorts_atomic
.globl _Copy_arrayof_conjoint_jshorts
.globl _Copy_arrayof_conjoint_jshorts
.globl _Copy_conjoint_jints_atomic
.globl _Copy_arrayof_conjoint_jints
.globl _Copy_conjoint_jlongs_atomic
.globl _Copy_conjoint_jlongs_atomic
.globl _Copy_arrayof_conjoint_jlongs
.section .text,"ax"
.section .text,"ax"
/ Fast thread accessors, used by threadLS_solaris_amd64.cpp
.align 16
.align 16
fs_load:
movq %fs:(%rdi),%rax
ret
.align 16
fs_thread:
movq %fs:0x0,%rax
ret
.globl SafeFetch32, Fetch32PFI, Fetch32Resume
.align 16
// Prototype: int SafeFetch32 (int * Adr, int ErrValue)
SafeFetch32:
movl %esi, %eax
Fetch32PFI:
movl (%rdi), %eax
Fetch32Resume:
movq %fs:(%rdi),%rax
ret
.globl SafeFetchN, FetchNPFI, FetchNResume
.align 16
// Prototype: intptr_t SafeFetchN (intptr_t * Adr, intptr_t ErrValue)
SafeFetchN:
movq %rsi, %rax
FetchNPFI:
movq (%rdi), %rax
FetchNResume:
.align 16
fs_thread:
movq %fs:0x0,%rax
ret
.globl SpinPause
@ -78,7 +58,7 @@ SpinPause:
nop
movq $1, %rax
ret
/ Support for void Copy::arrayof_conjoint_bytes(void* from,
/ void* to,
@ -340,7 +320,7 @@ aci_CopyLeft:
addq $4,%rdx
jg 1b
ret
/ Support for void Copy::arrayof_conjoint_jlongs(jlong* from,
/ jlong* to,
/ size_t count)

18
hotspot/src/os_cpu/windows_x86/vm/os_windows_x86.cpp
View file

@ -518,24 +518,6 @@ void os::print_register_info(outputStream *st, void *context) {
st->cr();
}
extern "C" int SafeFetch32 (int * adr, int Err) {
int rv = Err ;
_try {
rv = *((volatile int *) adr) ;
} __except(EXCEPTION_EXECUTE_HANDLER) {
}
return rv ;
}
extern "C" intptr_t SafeFetchN (intptr_t * adr, intptr_t Err) {
intptr_t rv = Err ;
_try {
rv = *((volatile intptr_t *) adr) ;
} __except(EXCEPTION_EXECUTE_HANDLER) {
}
return rv ;
}
extern "C" int SpinPause () {
#ifdef AMD64
return 0 ;