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6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
Initial checkin of JSDT code Reviewed-by: acorn, sbohne
This commit is contained in:
Keith McGuigan
parent
849e0dfc44
commit
f072bc9d3f
26 changed files with 2935 additions and 26 deletions
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@ -1637,7 +1637,7 @@ static void long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
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}
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} else if (dst.is_single_phys_reg()) {
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if (src.is_adjacent_aligned_on_stack(2)) {
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__ ldd(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
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__ ld_long(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
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} else {
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// dst is a single reg.
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// Remember lo is low address not msb for stack slots
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@ -2501,6 +2501,551 @@ nmethod *SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
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}
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#ifdef HAVE_DTRACE_H
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// ---------------------------------------------------------------------------
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// Generate a dtrace nmethod for a given signature. The method takes arguments
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// in the Java compiled code convention, marshals them to the native
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// abi and then leaves nops at the position you would expect to call a native
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// function. When the probe is enabled the nops are replaced with a trap
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// instruction that dtrace inserts and the trace will cause a notification
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// to dtrace.
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//
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// The probes are only able to take primitive types and java/lang/String as
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// arguments. No other java types are allowed. Strings are converted to utf8
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// strings so that from dtrace point of view java strings are converted to C
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// strings. There is an arbitrary fixed limit on the total space that a method
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// can use for converting the strings. (256 chars per string in the signature).
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// So any java string larger then this is truncated.
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static int fp_offset[ConcreteRegisterImpl::number_of_registers] = { 0 };
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static bool offsets_initialized = false;
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static VMRegPair reg64_to_VMRegPair(Register r) {
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VMRegPair ret;
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if (wordSize == 8) {
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ret.set2(r->as_VMReg());
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} else {
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ret.set_pair(r->successor()->as_VMReg(), r->as_VMReg());
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}
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return ret;
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}
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nmethod *SharedRuntime::generate_dtrace_nmethod(
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MacroAssembler *masm, methodHandle method) {
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// generate_dtrace_nmethod is guarded by a mutex so we are sure to
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// be single threaded in this method.
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assert(AdapterHandlerLibrary_lock->owned_by_self(), "must be");
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// Fill in the signature array, for the calling-convention call.
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int total_args_passed = method->size_of_parameters();
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BasicType* in_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed);
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VMRegPair *in_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed);
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// The signature we are going to use for the trap that dtrace will see
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// java/lang/String is converted. We drop "this" and any other object
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// is converted to NULL. (A one-slot java/lang/Long object reference
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// is converted to a two-slot long, which is why we double the allocation).
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BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed * 2);
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VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed * 2);
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int i=0;
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int total_strings = 0;
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int first_arg_to_pass = 0;
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int total_c_args = 0;
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int box_offset = java_lang_boxing_object::value_offset_in_bytes();
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// Skip the receiver as dtrace doesn't want to see it
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if( !method->is_static() ) {
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in_sig_bt[i++] = T_OBJECT;
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first_arg_to_pass = 1;
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}
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SignatureStream ss(method->signature());
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for ( ; !ss.at_return_type(); ss.next()) {
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BasicType bt = ss.type();
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in_sig_bt[i++] = bt; // Collect remaining bits of signature
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out_sig_bt[total_c_args++] = bt;
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if( bt == T_OBJECT) {
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symbolOop s = ss.as_symbol_or_null();
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if (s == vmSymbols::java_lang_String()) {
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total_strings++;
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out_sig_bt[total_c_args-1] = T_ADDRESS;
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} else if (s == vmSymbols::java_lang_Boolean() ||
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s == vmSymbols::java_lang_Byte()) {
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out_sig_bt[total_c_args-1] = T_BYTE;
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} else if (s == vmSymbols::java_lang_Character() ||
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s == vmSymbols::java_lang_Short()) {
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out_sig_bt[total_c_args-1] = T_SHORT;
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} else if (s == vmSymbols::java_lang_Integer() ||
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s == vmSymbols::java_lang_Float()) {
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out_sig_bt[total_c_args-1] = T_INT;
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} else if (s == vmSymbols::java_lang_Long() ||
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s == vmSymbols::java_lang_Double()) {
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out_sig_bt[total_c_args-1] = T_LONG;
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out_sig_bt[total_c_args++] = T_VOID;
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}
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} else if ( bt == T_LONG || bt == T_DOUBLE ) {
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in_sig_bt[i++] = T_VOID; // Longs & doubles take 2 Java slots
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// We convert double to long
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out_sig_bt[total_c_args-1] = T_LONG;
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out_sig_bt[total_c_args++] = T_VOID;
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} else if ( bt == T_FLOAT) {
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// We convert float to int
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out_sig_bt[total_c_args-1] = T_INT;
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}
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}
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assert(i==total_args_passed, "validly parsed signature");
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// Now get the compiled-Java layout as input arguments
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int comp_args_on_stack;
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comp_args_on_stack = SharedRuntime::java_calling_convention(
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in_sig_bt, in_regs, total_args_passed, false);
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// We have received a description of where all the java arg are located
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// on entry to the wrapper. We need to convert these args to where
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// the a native (non-jni) function would expect them. To figure out
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// where they go we convert the java signature to a C signature and remove
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// T_VOID for any long/double we might have received.
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// Now figure out where the args must be stored and how much stack space
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// they require (neglecting out_preserve_stack_slots but space for storing
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// the 1st six register arguments). It's weird see int_stk_helper.
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//
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int out_arg_slots;
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out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args);
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// Calculate the total number of stack slots we will need.
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// First count the abi requirement plus all of the outgoing args
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int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
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// Plus a temp for possible converion of float/double/long register args
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int conversion_temp = stack_slots;
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stack_slots += 2;
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// Now space for the string(s) we must convert
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int string_locs = stack_slots;
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stack_slots += total_strings *
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(max_dtrace_string_size / VMRegImpl::stack_slot_size);
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// Ok The space we have allocated will look like:
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//
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//
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// FP-> | |
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// |---------------------|
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// | string[n] |
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// |---------------------| <- string_locs[n]
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// | string[n-1] |
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// |---------------------| <- string_locs[n-1]
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// | ... |
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// | ... |
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// |---------------------| <- string_locs[1]
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// | string[0] |
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// |---------------------| <- string_locs[0]
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// | temp |
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// |---------------------| <- conversion_temp
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// | outbound memory |
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// | based arguments |
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// | |
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// |---------------------|
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// | |
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// SP-> | out_preserved_slots |
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//
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//
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// Now compute actual number of stack words we need rounding to make
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// stack properly aligned.
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stack_slots = round_to(stack_slots, 4 * VMRegImpl::slots_per_word);
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int stack_size = stack_slots * VMRegImpl::stack_slot_size;
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intptr_t start = (intptr_t)__ pc();
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// First thing make an ic check to see if we should even be here
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{
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Label L;
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const Register temp_reg = G3_scratch;
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Address ic_miss(temp_reg, SharedRuntime::get_ic_miss_stub());
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__ verify_oop(O0);
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__ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), temp_reg);
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__ cmp(temp_reg, G5_inline_cache_reg);
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__ brx(Assembler::equal, true, Assembler::pt, L);
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__ delayed()->nop();
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__ jump_to(ic_miss, 0);
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__ delayed()->nop();
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__ align(CodeEntryAlignment);
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__ bind(L);
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}
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int vep_offset = ((intptr_t)__ pc()) - start;
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// The instruction at the verified entry point must be 5 bytes or longer
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// because it can be patched on the fly by make_non_entrant. The stack bang
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// instruction fits that requirement.
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// Generate stack overflow check before creating frame
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__ generate_stack_overflow_check(stack_size);
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assert(((intptr_t)__ pc() - start - vep_offset) >= 5,
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"valid size for make_non_entrant");
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// Generate a new frame for the wrapper.
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__ save(SP, -stack_size, SP);
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// Frame is now completed as far a size and linkage.
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int frame_complete = ((intptr_t)__ pc()) - start;
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#ifdef ASSERT
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bool reg_destroyed[RegisterImpl::number_of_registers];
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bool freg_destroyed[FloatRegisterImpl::number_of_registers];
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for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) {
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reg_destroyed[r] = false;
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}
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for ( int f = 0 ; f < FloatRegisterImpl::number_of_registers ; f++ ) {
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freg_destroyed[f] = false;
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}
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#endif /* ASSERT */
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VMRegPair zero;
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zero.set2(G0->as_VMReg());
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int c_arg, j_arg;
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Register conversion_off = noreg;
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for (j_arg = first_arg_to_pass, c_arg = 0 ;
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j_arg < total_args_passed ; j_arg++, c_arg++ ) {
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VMRegPair src = in_regs[j_arg];
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VMRegPair dst = out_regs[c_arg];
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#ifdef ASSERT
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if (src.first()->is_Register()) {
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assert(!reg_destroyed[src.first()->as_Register()->encoding()], "ack!");
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} else if (src.first()->is_FloatRegister()) {
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assert(!freg_destroyed[src.first()->as_FloatRegister()->encoding(
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FloatRegisterImpl::S)], "ack!");
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}
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if (dst.first()->is_Register()) {
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reg_destroyed[dst.first()->as_Register()->encoding()] = true;
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} else if (dst.first()->is_FloatRegister()) {
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freg_destroyed[dst.first()->as_FloatRegister()->encoding(
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FloatRegisterImpl::S)] = true;
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}
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#endif /* ASSERT */
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switch (in_sig_bt[j_arg]) {
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case T_ARRAY:
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case T_OBJECT:
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{
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if (out_sig_bt[c_arg] == T_BYTE || out_sig_bt[c_arg] == T_SHORT ||
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out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) {
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// need to unbox a one-slot value
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Register in_reg = L0;
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Register tmp = L2;
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if ( src.first()->is_reg() ) {
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in_reg = src.first()->as_Register();
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} else {
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assert(Assembler::is_simm13(reg2offset(src.first()) + STACK_BIAS),
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"must be");
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__ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, in_reg);
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}
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// If the final destination is an acceptable register
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if ( dst.first()->is_reg() ) {
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if ( dst.is_single_phys_reg() || out_sig_bt[c_arg] != T_LONG ) {
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tmp = dst.first()->as_Register();
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}
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}
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Label skipUnbox;
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if ( wordSize == 4 && out_sig_bt[c_arg] == T_LONG ) {
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__ mov(G0, tmp->successor());
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}
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__ br_null(in_reg, true, Assembler::pn, skipUnbox);
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__ delayed()->mov(G0, tmp);
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switch (out_sig_bt[c_arg]) {
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case T_BYTE:
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__ ldub(in_reg, box_offset, tmp); break;
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case T_SHORT:
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__ lduh(in_reg, box_offset, tmp); break;
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case T_INT:
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__ ld(in_reg, box_offset, tmp); break;
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case T_LONG:
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__ ld_long(in_reg, box_offset, tmp); break;
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default: ShouldNotReachHere();
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}
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__ bind(skipUnbox);
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// If tmp wasn't final destination copy to final destination
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if (tmp == L2) {
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VMRegPair tmp_as_VM = reg64_to_VMRegPair(L2);
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if (out_sig_bt[c_arg] == T_LONG) {
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long_move(masm, tmp_as_VM, dst);
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} else {
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move32_64(masm, tmp_as_VM, out_regs[c_arg]);
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}
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}
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if (out_sig_bt[c_arg] == T_LONG) {
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assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
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++c_arg; // move over the T_VOID to keep the loop indices in sync
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}
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} else if (out_sig_bt[c_arg] == T_ADDRESS) {
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Register s =
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src.first()->is_reg() ? src.first()->as_Register() : L2;
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Register d =
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dst.first()->is_reg() ? dst.first()->as_Register() : L2;
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// We store the oop now so that the conversion pass can reach
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// while in the inner frame. This will be the only store if
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// the oop is NULL.
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if (s != L2) {
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// src is register
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if (d != L2) {
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// dst is register
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__ mov(s, d);
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} else {
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assert(Assembler::is_simm13(reg2offset(dst.first()) +
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STACK_BIAS), "must be");
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__ st_ptr(s, SP, reg2offset(dst.first()) + STACK_BIAS);
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}
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} else {
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// src not a register
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assert(Assembler::is_simm13(reg2offset(src.first()) +
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STACK_BIAS), "must be");
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__ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, d);
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if (d == L2) {
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assert(Assembler::is_simm13(reg2offset(dst.first()) +
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STACK_BIAS), "must be");
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__ st_ptr(d, SP, reg2offset(dst.first()) + STACK_BIAS);
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}
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}
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} else if (out_sig_bt[c_arg] != T_VOID) {
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// Convert the arg to NULL
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if (dst.first()->is_reg()) {
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__ mov(G0, dst.first()->as_Register());
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} else {
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assert(Assembler::is_simm13(reg2offset(dst.first()) +
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STACK_BIAS), "must be");
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__ st_ptr(G0, SP, reg2offset(dst.first()) + STACK_BIAS);
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}
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}
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}
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break;
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case T_VOID:
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break;
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case T_FLOAT:
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if (src.first()->is_stack()) {
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// Stack to stack/reg is simple
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move32_64(masm, src, dst);
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} else {
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if (dst.first()->is_reg()) {
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// freg -> reg
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int off =
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STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size;
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Register d = dst.first()->as_Register();
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if (Assembler::is_simm13(off)) {
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__ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
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SP, off);
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__ ld(SP, off, d);
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} else {
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if (conversion_off == noreg) {
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__ set(off, L6);
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conversion_off = L6;
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}
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__ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
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SP, conversion_off);
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__ ld(SP, conversion_off , d);
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}
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} else {
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// freg -> mem
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int off = STACK_BIAS + reg2offset(dst.first());
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if (Assembler::is_simm13(off)) {
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__ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
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SP, off);
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} else {
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if (conversion_off == noreg) {
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__ set(off, L6);
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conversion_off = L6;
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}
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__ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
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SP, conversion_off);
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}
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}
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}
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break;
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case T_DOUBLE:
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assert( j_arg + 1 < total_args_passed &&
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in_sig_bt[j_arg + 1] == T_VOID &&
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out_sig_bt[c_arg+1] == T_VOID, "bad arg list");
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if (src.first()->is_stack()) {
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// Stack to stack/reg is simple
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long_move(masm, src, dst);
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} else {
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Register d = dst.first()->is_reg() ? dst.first()->as_Register() : L2;
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// Destination could be an odd reg on 32bit in which case
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// we can't load direct to the destination.
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if (!d->is_even() && wordSize == 4) {
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d = L2;
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}
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int off = STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size;
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if (Assembler::is_simm13(off)) {
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__ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(),
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SP, off);
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__ ld_long(SP, off, d);
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} else {
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if (conversion_off == noreg) {
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__ set(off, L6);
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conversion_off = L6;
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}
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__ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(),
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SP, conversion_off);
|
||||
__ ld_long(SP, conversion_off, d);
|
||||
}
|
||||
if (d == L2) {
|
||||
long_move(masm, reg64_to_VMRegPair(L2), dst);
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
case T_LONG :
|
||||
// 32bit can't do a split move of something like g1 -> O0, O1
|
||||
// so use a memory temp
|
||||
if (src.is_single_phys_reg() && wordSize == 4) {
|
||||
Register tmp = L2;
|
||||
if (dst.first()->is_reg() &&
|
||||
(wordSize == 8 || dst.first()->as_Register()->is_even())) {
|
||||
tmp = dst.first()->as_Register();
|
||||
}
|
||||
|
||||
int off = STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size;
|
||||
if (Assembler::is_simm13(off)) {
|
||||
__ stx(src.first()->as_Register(), SP, off);
|
||||
__ ld_long(SP, off, tmp);
|
||||
} else {
|
||||
if (conversion_off == noreg) {
|
||||
__ set(off, L6);
|
||||
conversion_off = L6;
|
||||
}
|
||||
__ stx(src.first()->as_Register(), SP, conversion_off);
|
||||
__ ld_long(SP, conversion_off, tmp);
|
||||
}
|
||||
|
||||
if (tmp == L2) {
|
||||
long_move(masm, reg64_to_VMRegPair(L2), dst);
|
||||
}
|
||||
} else {
|
||||
long_move(masm, src, dst);
|
||||
}
|
||||
break;
|
||||
|
||||
case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
|
||||
|
||||
default:
|
||||
move32_64(masm, src, dst);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
// If we have any strings we must store any register based arg to the stack
|
||||
// This includes any still live xmm registers too.
|
||||
|
||||
if (total_strings > 0 ) {
|
||||
|
||||
// protect all the arg registers
|
||||
__ save_frame(0);
|
||||
__ mov(G2_thread, L7_thread_cache);
|
||||
const Register L2_string_off = L2;
|
||||
|
||||
// Get first string offset
|
||||
__ set(string_locs * VMRegImpl::stack_slot_size, L2_string_off);
|
||||
|
||||
for (c_arg = 0 ; c_arg < total_c_args ; c_arg++ ) {
|
||||
if (out_sig_bt[c_arg] == T_ADDRESS) {
|
||||
|
||||
VMRegPair dst = out_regs[c_arg];
|
||||
const Register d = dst.first()->is_reg() ?
|
||||
dst.first()->as_Register()->after_save() : noreg;
|
||||
|
||||
// It's a string the oop and it was already copied to the out arg
|
||||
// position
|
||||
if (d != noreg) {
|
||||
__ mov(d, O0);
|
||||
} else {
|
||||
assert(Assembler::is_simm13(reg2offset(dst.first()) + STACK_BIAS),
|
||||
"must be");
|
||||
__ ld_ptr(FP, reg2offset(dst.first()) + STACK_BIAS, O0);
|
||||
}
|
||||
Label skip;
|
||||
|
||||
__ br_null(O0, false, Assembler::pn, skip);
|
||||
__ delayed()->add(FP, L2_string_off, O1);
|
||||
|
||||
if (d != noreg) {
|
||||
__ mov(O1, d);
|
||||
} else {
|
||||
assert(Assembler::is_simm13(reg2offset(dst.first()) + STACK_BIAS),
|
||||
"must be");
|
||||
__ st_ptr(O1, FP, reg2offset(dst.first()) + STACK_BIAS);
|
||||
}
|
||||
|
||||
__ call(CAST_FROM_FN_PTR(address, SharedRuntime::get_utf),
|
||||
relocInfo::runtime_call_type);
|
||||
__ delayed()->add(L2_string_off, max_dtrace_string_size, L2_string_off);
|
||||
|
||||
__ bind(skip);
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
__ mov(L7_thread_cache, G2_thread);
|
||||
__ restore();
|
||||
|
||||
}
|
||||
|
||||
|
||||
// Ok now we are done. Need to place the nop that dtrace wants in order to
|
||||
// patch in the trap
|
||||
|
||||
int patch_offset = ((intptr_t)__ pc()) - start;
|
||||
|
||||
__ nop();
|
||||
|
||||
|
||||
// Return
|
||||
|
||||
__ ret();
|
||||
__ delayed()->restore();
|
||||
|
||||
__ flush();
|
||||
|
||||
nmethod *nm = nmethod::new_dtrace_nmethod(
|
||||
method, masm->code(), vep_offset, patch_offset, frame_complete,
|
||||
stack_slots / VMRegImpl::slots_per_word);
|
||||
return nm;
|
||||
|
||||
}
|
||||
|
||||
#endif // HAVE_DTRACE_H
|
||||
|
||||
// this function returns the adjust size (in number of words) to a c2i adapter
|
||||
// activation for use during deoptimization
|
||||
int Deoptimization::last_frame_adjust(int callee_parameters, int callee_locals) {
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue