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0c4a6e79ef
According to the OpenRISC architecture manual, the dcache and icache may not be present. When these caches are present, the invalidate and flush registers may be absent. The current implementation does not perform checks to verify their presence before utilizing cache registers, or invalidating and flushing cache blocks. Introduce new functions to detect the presence of cache components and related special-purpose registers. There are a few places where a range of addresses have to be flushed or invalidated and the implementation is duplicated. Introduce new utility functions and macros that generalize this implementation and reduce duplication. Signed-off-by: Sahil Siddiq <sahilcdq0@gmail.com> Signed-off-by: Stafford Horne <shorne@gmail.com>
45 lines
931 B
C
45 lines
931 B
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* OpenRISC Linux
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*
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* Linux architectural port borrowing liberally from similar works of
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* others. All original copyrights apply as per the original source
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* declaration.
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*
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* OpenRISC implementation:
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* Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
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* Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
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* et al.
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*/
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#ifndef __ASM_OPENRISC_CPUINFO_H
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#define __ASM_OPENRISC_CPUINFO_H
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#include <asm/spr.h>
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#include <asm/spr_defs.h>
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struct cache_desc {
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u32 size;
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u32 sets;
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u32 block_size;
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u32 ways;
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};
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struct cpuinfo_or1k {
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u32 clock_frequency;
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struct cache_desc icache;
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struct cache_desc dcache;
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u16 coreid;
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};
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extern struct cpuinfo_or1k cpuinfo_or1k[NR_CPUS];
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extern void setup_cpuinfo(void);
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/*
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* Check if the cache component exists.
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*/
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extern bool cpu_cache_is_present(const unsigned int cache_type);
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#endif /* __ASM_OPENRISC_CPUINFO_H */
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