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Drop support for JIT without SSE

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Closes GH-4388.
This commit is contained in:
Nikita Popov 2019-07-10 15:44:02 +02:00
parent cf0e15333e
commit cf7dd00280
1 changed files with 201 additions and 402 deletions
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203
ext/opcache/jit/zend_jit_x86.dasc
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@ -42,7 +42,6 @@
|.define FCARG2d, CARG2d |.define FCARG2d, CARG2d
|.define SPAD, 0x08 // padding for CPU stack alignment |.define SPAD, 0x08 // padding for CPU stack alignment
|.define NR_SPAD, 0x58 // padding for CPU stack alignment |.define NR_SPAD, 0x58 // padding for CPU stack alignment
|.define SSE, 1
|.define T3, [r4+0x50] // Used to store old value of IP |.define T3, [r4+0x50] // Used to store old value of IP
|.define T2, [r4+0x48] // Used to store old value of FP |.define T2, [r4+0x48] // Used to store old value of FP
|.define T1, [r4+0x40] |.define T1, [r4+0x40]
@ -71,7 +70,6 @@
|.define FCARG2d, CARG2d |.define FCARG2d, CARG2d
|.define SPAD, 0x08 // padding for CPU stack alignment |.define SPAD, 0x08 // padding for CPU stack alignment
|.define NR_SPAD, 0x18 // padding for CPU stack alignment |.define NR_SPAD, 0x18 // padding for CPU stack alignment
|.define SSE, 1
|.define T3, [r4+0x10] // Used to store old value of IP (CALL VM only) |.define T3, [r4+0x10] // Used to store old value of IP (CALL VM only)
|.define T2, [r4+0x08] // Used to store old value of FP (CALL VM only) |.define T2, [r4+0x08] // Used to store old value of FP (CALL VM only)
|.define T1, [r4] |.define T1, [r4]
@ -86,7 +84,6 @@
|.define FCARG2d, edx |.define FCARG2d, edx
|.define SPAD, 12 // padding for CPU stack alignment |.define SPAD, 12 // padding for CPU stack alignment
|.define NR_SPAD, 12 // padding for CPU stack alignment |.define NR_SPAD, 12 // padding for CPU stack alignment
|.define SSE, 1
|.define T3, [r4+0x10] // Used to store old value of IP (CALL VM only) |.define T3, [r4+0x10] // Used to store old value of IP (CALL VM only)
|.define T2, [r4+0x08] // Used to store old value of FP (CALL VM only) |.define T2, [r4+0x08] // Used to store old value of FP (CALL VM only)
|.define T1, [r4] |.define T1, [r4]
@ -516,42 +513,6 @@ static void* dasm_labels[zend_lb_MAX];
| SET_Z_TYPE_INFO FP + r0, IS_UNDEF | SET_Z_TYPE_INFO FP + r0, IS_UNDEF
|.endmacro |.endmacro
|.macro FPU_OP, fp_ins, addr
|| if (Z_MODE(addr) == IS_CONST_ZVAL) {
| MEM_OP1 fp_ins, qword, Z_ZV(addr), r0
|| } else if (Z_MODE(addr) == IS_MEM_ZVAL) {
| fp_ins qword [Ra(Z_REG(addr))+Z_OFFSET(addr)]
|| } else {
|| ZEND_ASSERT(0);
|| }
|.endmacro
|.macro FPU_GET_ZVAL_DVAL, addr
| FPU_OP fld, addr
|.endmacro
|.macro FPU_MATH, opcode, addr
|| switch (opcode) {
|| case ZEND_ADD:
| FPU_OP fadd, addr
|| break;
|| case ZEND_SUB:
| FPU_OP fsub, addr
|| break;
|| case ZEND_MUL:
| FPU_OP fmul, addr
|| break;
|| case ZEND_DIV:
| FPU_OP fdiv, addr
|| break;
|| }
|.endmacro
|.macro FPU_SET_ZVAL_DVAL, addr
|| ZEND_ASSERT(Z_MODE(addr) == IS_MEM_ZVAL);
| fstp qword [Ra(Z_REG(res_addr))+Z_OFFSET(res_addr)]
|.endmacro
|.macro SSE_AVX_INS, sse_ins, avx_ins, op1, op2 |.macro SSE_AVX_INS, sse_ins, avx_ins, op1, op2
|| if (zend_jit_x86_flags & ZEND_JIT_CPU_AVX) { || if (zend_jit_x86_flags & ZEND_JIT_CPU_AVX) {
| avx_ins op1, op2 | avx_ins op1, op2
@ -887,44 +848,10 @@ static void* dasm_labels[zend_lb_MAX];
|| } || }
|.endmacro |.endmacro
|.macro FPU_LONG_OP, fp_ins, addr
|| if (Z_MODE(addr) == IS_CONST_ZVAL) {
| MEM_OP1 fp_ins, aword, Z_ZV(addr), r0
|| } else if (Z_MODE(addr) == IS_MEM_ZVAL) {
| fp_ins aword [Ra(Z_REG(addr))+Z_OFFSET(addr)]
|| } else if (Z_MODE(addr) == IS_REG) {
| fp_ins Ra(Z_REG(addr))
|| } else {
|| ZEND_ASSERT(0);
|| }
|.endmacro
|.macro FPU_GET_ZVAL_LVAL, addr
| FPU_LONG_OP fild, addr
|.endmacro
|.macro FPU_MATH_REG, opcode, reg
|| switch (opcode) {
|| case ZEND_ADD:
| fadd reg
|| break;
|| case ZEND_SUB:
| fsub reg
|| break;
|| case ZEND_MUL:
| fmul reg
|| break;
|| case ZEND_DIV:
| fdiv reg
|| break;
|| }
|.endmacro
|.macro ZVAL_COPY_CONST, dst_addr, dst_info, zv, tmp_reg |.macro ZVAL_COPY_CONST, dst_addr, dst_info, zv, tmp_reg
|| if (Z_TYPE_P(zv) > IS_TRUE) { || if (Z_TYPE_P(zv) > IS_TRUE) {
|| if (Z_TYPE_P(zv) == IS_DOUBLE) { || if (Z_TYPE_P(zv) == IS_DOUBLE) {
|| zend_reg dst_reg = (Z_MODE(dst_addr) == IS_REG) ? Z_REG(dst_addr) : ZREG_XMM0; || zend_reg dst_reg = (Z_MODE(dst_addr) == IS_REG) ? Z_REG(dst_addr) : ZREG_XMM0;
| .if X64 or SSE
|| if (Z_DVAL_P(zv) == 0.0 && !is_signed(Z_DVAL_P(zv))) { || if (Z_DVAL_P(zv) == 0.0 && !is_signed(Z_DVAL_P(zv))) {
|| if (zend_jit_x86_flags & ZEND_JIT_CPU_AVX) { || if (zend_jit_x86_flags & ZEND_JIT_CPU_AVX) {
| vxorps xmm(dst_reg-ZREG_XMM0), xmm(dst_reg-ZREG_XMM0), xmm(dst_reg-ZREG_XMM0) | vxorps xmm(dst_reg-ZREG_XMM0), xmm(dst_reg-ZREG_XMM0), xmm(dst_reg-ZREG_XMM0)
@ -940,16 +867,6 @@ static void* dasm_labels[zend_lb_MAX];
| SSE_AVX_INS movsd, vmovsd, xmm(dst_reg-ZREG_XMM0), qword [((uint32_t)(uintptr_t)zv)] | SSE_AVX_INS movsd, vmovsd, xmm(dst_reg-ZREG_XMM0), qword [((uint32_t)(uintptr_t)zv)]
|| } || }
| SSE_SET_ZVAL_DVAL dst_addr, dst_reg | SSE_SET_ZVAL_DVAL dst_addr, dst_reg
| .else
|| if (Z_DVAL_P(zv) == 0.0 && !is_signed(Z_DVAL_P(zv))) {
| fldz
|| } else if (Z_DVAL_P(zv) == 1.0) {
| fld1
|| } else {
| fld qword [zv]
|| }
| FPU_SET_ZVAL_DVAL dst_addr
| .endif
|| } else if (Z_LVAL_P(zv) == 0 && Z_MODE(dst_addr) == IS_REG) { || } else if (Z_LVAL_P(zv) == 0 && Z_MODE(dst_addr) == IS_REG) {
| xor Ra(Z_REG(dst_addr)), Ra(Z_REG(dst_addr)) | xor Ra(Z_REG(dst_addr)), Ra(Z_REG(dst_addr))
|| } else { || } else {
@ -981,7 +898,6 @@ static void* dasm_labels[zend_lb_MAX];
|| if (Z_TYPE_P(zv) == IS_DOUBLE) { || if (Z_TYPE_P(zv) == IS_DOUBLE) {
|| zend_reg dst_reg = (Z_MODE(dst_addr) == IS_REG) ? || zend_reg dst_reg = (Z_MODE(dst_addr) == IS_REG) ?
|| Z_REG(dst_addr) : ((Z_MODE(res_addr) == IS_REG) ? Z_MODE(res_addr) : ZREG_XMM0); || Z_REG(dst_addr) : ((Z_MODE(res_addr) == IS_REG) ? Z_MODE(res_addr) : ZREG_XMM0);
| .if X64 or SSE
|| if (Z_DVAL_P(zv) == 0.0 && !is_signed(Z_DVAL_P(zv))) { || if (Z_DVAL_P(zv) == 0.0 && !is_signed(Z_DVAL_P(zv))) {
|| if (zend_jit_x86_flags & ZEND_JIT_CPU_AVX) { || if (zend_jit_x86_flags & ZEND_JIT_CPU_AVX) {
| vxorps xmm(dst_reg-ZREG_XMM0), xmm(dst_reg-ZREG_XMM0), xmm(dst_reg-ZREG_XMM0) | vxorps xmm(dst_reg-ZREG_XMM0), xmm(dst_reg-ZREG_XMM0), xmm(dst_reg-ZREG_XMM0)
@ -998,24 +914,6 @@ static void* dasm_labels[zend_lb_MAX];
|| } || }
| SSE_SET_ZVAL_DVAL dst_addr, ZREG_XMM0 | SSE_SET_ZVAL_DVAL dst_addr, ZREG_XMM0
| SSE_SET_ZVAL_DVAL res_addr, ZREG_XMM0 | SSE_SET_ZVAL_DVAL res_addr, ZREG_XMM0
| .else
|| if (Z_DVAL_P(zv) == 0.0 && !is_signed(Z_DVAL_P(zv))) {
| fldz
|| } else if (Z_DVAL_P(zv) == 1.0) {
| fld1
|| } else {
| fld qword [zv]
|| }
| FPU_SET_ZVAL_DVAL dst_addr
|| if (Z_DVAL_P(zv) == 0.0 && !is_signed(Z_DVAL_P(zv))) {
| fldz
|| } else if (Z_DVAL_P(zv) == 1.0) {
| fld1
|| } else {
| fld qword [zv]
|| }
| FPU_SET_ZVAL_DVAL res_addr
| .endif
|| } else if (Z_LVAL_P(zv) == 0 && (Z_MODE(dst_addr) == IS_REG || Z_MODE(res_addr) == IS_REG)) { || } else if (Z_LVAL_P(zv) == 0 && (Z_MODE(dst_addr) == IS_REG || Z_MODE(res_addr) == IS_REG)) {
|| if (Z_MODE(dst_addr) == IS_REG) { || if (Z_MODE(dst_addr) == IS_REG) {
| xor Ra(Z_REG(dst_addr)), Ra(Z_REG(dst_addr)) | xor Ra(Z_REG(dst_addr)), Ra(Z_REG(dst_addr))
@ -1087,7 +985,6 @@ static void* dasm_labels[zend_lb_MAX];
| SET_ZVAL_LVAL dst_addr, Ra(tmp_reg2) | SET_ZVAL_LVAL dst_addr, Ra(tmp_reg2)
|| } || }
|| } else if ((src_info & MAY_BE_ANY) == MAY_BE_DOUBLE) { || } else if ((src_info & MAY_BE_ANY) == MAY_BE_DOUBLE) {
| .if X64 or SSE
|| if (Z_MODE(src_addr) == IS_REG) { || if (Z_MODE(src_addr) == IS_REG) {
| SSE_SET_ZVAL_DVAL dst_addr, Z_REG(src_addr) | SSE_SET_ZVAL_DVAL dst_addr, Z_REG(src_addr)
|| } else if (Z_MODE(dst_addr) == IS_REG) { || } else if (Z_MODE(dst_addr) == IS_REG) {
@ -1096,10 +993,6 @@ static void* dasm_labels[zend_lb_MAX];
| SSE_GET_ZVAL_DVAL ZREG_XMM0, src_addr | SSE_GET_ZVAL_DVAL ZREG_XMM0, src_addr
| SSE_SET_ZVAL_DVAL dst_addr, ZREG_XMM0 | SSE_SET_ZVAL_DVAL dst_addr, ZREG_XMM0
|| } || }
| .else
| FPU_GET_ZVAL_DVAL src_addr
| FPU_SET_ZVAL_DVAL dst_addr
| .endif
|| } else if (!(src_info & MAY_BE_DOUBLE)) { || } else if (!(src_info & MAY_BE_DOUBLE)) {
| GET_ZVAL_PTR Ra(tmp_reg2), src_addr | GET_ZVAL_PTR Ra(tmp_reg2), src_addr
| SET_ZVAL_PTR dst_addr, Ra(tmp_reg2) | SET_ZVAL_PTR dst_addr, Ra(tmp_reg2)
@ -1160,7 +1053,6 @@ static void* dasm_labels[zend_lb_MAX];
| SET_ZVAL_LVAL res_addr, Ra(tmp_reg2) | SET_ZVAL_LVAL res_addr, Ra(tmp_reg2)
|| } || }
|| } else if ((src_info & MAY_BE_ANY) == MAY_BE_DOUBLE) { || } else if ((src_info & MAY_BE_ANY) == MAY_BE_DOUBLE) {
| .if X64 or SSE
|| if (Z_MODE(src_addr) == IS_REG) { || if (Z_MODE(src_addr) == IS_REG) {
| SSE_SET_ZVAL_DVAL dst_addr, Z_REG(src_addr) | SSE_SET_ZVAL_DVAL dst_addr, Z_REG(src_addr)
| SSE_SET_ZVAL_DVAL res_addr, Z_REG(src_addr) | SSE_SET_ZVAL_DVAL res_addr, Z_REG(src_addr)
@ -1175,12 +1067,6 @@ static void* dasm_labels[zend_lb_MAX];
| SSE_SET_ZVAL_DVAL dst_addr, ZREG_XMM0 | SSE_SET_ZVAL_DVAL dst_addr, ZREG_XMM0
| SSE_SET_ZVAL_DVAL res_addr, ZREG_XMM0 | SSE_SET_ZVAL_DVAL res_addr, ZREG_XMM0
|| } || }
| .else
| FPU_GET_ZVAL_DVAL src_addr
| FPU_STROE dst_addr
| FPU_GET_ZVAL_DVAL src_addr
| FPU_SET_ZVAL_DVAL res_addr
| .endif
|| } else if (!(src_info & MAY_BE_DOUBLE)) { || } else if (!(src_info & MAY_BE_DOUBLE)) {
| GET_ZVAL_PTR Ra(tmp_reg2), src_addr | GET_ZVAL_PTR Ra(tmp_reg2), src_addr
| SET_ZVAL_PTR dst_addr, Ra(tmp_reg2) | SET_ZVAL_PTR dst_addr, Ra(tmp_reg2)
@ -2490,7 +2376,6 @@ extern char *_tls_end;
static int zend_jit_setup(void) static int zend_jit_setup(void)
{ {
|.if SSE
if (!zend_cpu_supports(ZEND_CPU_FEATURE_SSE2)) { if (!zend_cpu_supports(ZEND_CPU_FEATURE_SSE2)) {
zend_error(E_CORE_ERROR, "CPU doesn't support SSE2"); zend_error(E_CORE_ERROR, "CPU doesn't support SSE2");
return FAILURE; return FAILURE;
@ -2500,7 +2385,6 @@ static int zend_jit_setup(void)
zend_jit_x86_flags |= ZEND_JIT_CPU_AVX; zend_jit_x86_flags |= ZEND_JIT_CPU_AVX;
} }
} }
|.endif
#if ZTS #if ZTS
# ifdef _WIN64 # ifdef _WIN64
@ -2881,11 +2765,7 @@ static int zend_jit_spill_store(dasm_State **Dst, zend_jit_addr src, zend_jit_ad
| SET_ZVAL_TYPE_INFO dst, IS_LONG | SET_ZVAL_TYPE_INFO dst, IS_LONG
} }
} else if ((info & MAY_BE_ANY) == MAY_BE_DOUBLE) { } else if ((info & MAY_BE_ANY) == MAY_BE_DOUBLE) {
| .if SSE
| SSE_SET_ZVAL_DVAL dst, Z_REG(src) | SSE_SET_ZVAL_DVAL dst, Z_REG(src)
| .else
|| ZEND_ASSERT(0);
| .endif
if (set_type) { if (set_type) {
| SET_ZVAL_TYPE_INFO dst, IS_DOUBLE | SET_ZVAL_TYPE_INFO dst, IS_DOUBLE
} }
@ -2903,11 +2783,7 @@ static int zend_jit_load_reg(dasm_State **Dst, zend_jit_addr src, zend_jit_addr
if ((info & MAY_BE_ANY) == MAY_BE_LONG) { if ((info & MAY_BE_ANY) == MAY_BE_LONG) {
| GET_ZVAL_LVAL Z_REG(dst), src | GET_ZVAL_LVAL Z_REG(dst), src
} else if ((info & MAY_BE_ANY) == MAY_BE_DOUBLE) { } else if ((info & MAY_BE_ANY) == MAY_BE_DOUBLE) {
| .if SSE
| SSE_GET_ZVAL_DVAL Z_REG(dst), src | SSE_GET_ZVAL_DVAL Z_REG(dst), src
| .else
|| ZEND_ASSERT(0);
| .endif
} else { } else {
ZEND_ASSERT(0); ZEND_ASSERT(0);
} }
@ -2961,11 +2837,7 @@ static int zend_jit_update_regs(dasm_State **Dst, zend_jit_addr src, zend_jit_ad
if ((info & MAY_BE_ANY) == MAY_BE_LONG) { if ((info & MAY_BE_ANY) == MAY_BE_LONG) {
| mov Ra(Z_REG(dst)), Ra(Z_REG(src)) | mov Ra(Z_REG(dst)), Ra(Z_REG(src))
} else if ((info & MAY_BE_ANY) == MAY_BE_DOUBLE) { } else if ((info & MAY_BE_ANY) == MAY_BE_DOUBLE) {
| .if SSE
| SSE_AVX_INS movsd, vmovaps, xmm(Z_REG(dst)-ZREG_XMM0), xmm(Z_REG(src)-ZREG_XMM0) | SSE_AVX_INS movsd, vmovaps, xmm(Z_REG(dst)-ZREG_XMM0), xmm(Z_REG(src)-ZREG_XMM0)
| .else
|| ZEND_ASSERT(0);
| .endif
} else { } else {
ZEND_ASSERT(0); ZEND_ASSERT(0);
} }
@ -3151,7 +3023,6 @@ static int zend_jit_inc_dec(dasm_State **Dst, const zend_op *opline, zend_op_arr
| ZVAL_COPY_VALUE res_addr, res_use_info, op1_addr, MAY_BE_DOUBLE, ZREG_R0, ZREG_R2 | ZVAL_COPY_VALUE res_addr, res_use_info, op1_addr, MAY_BE_DOUBLE, ZREG_R0, ZREG_R2
} }
} }
|.if SSE
if (Z_MODE(op1_def_addr) == IS_REG) { if (Z_MODE(op1_def_addr) == IS_REG) {
tmp_reg = Z_REG(op1_def_addr); tmp_reg = Z_REG(op1_def_addr);
} else if (Z_MODE(op1_addr) == IS_REG && zend_ssa_is_last_use(op_array, ssa, ssa->ops[opline-op_array->opcodes].op1_use, opline-op_array->opcodes)) { } else if (Z_MODE(op1_addr) == IS_REG && zend_ssa_is_last_use(op_array, ssa, ssa->ops[opline-op_array->opcodes].op1_use, opline-op_array->opcodes)) {
@ -3174,16 +3045,6 @@ static int zend_jit_inc_dec(dasm_State **Dst, const zend_op *opline, zend_op_arr
} }
} }
| SSE_SET_ZVAL_DVAL op1_def_addr, tmp_reg | SSE_SET_ZVAL_DVAL op1_def_addr, tmp_reg
|.else
| FPU_GET_ZVAL_DVAL op1_addr
| fld1
if (opline->opcode == ZEND_PRE_INC || opline->opcode == ZEND_POST_INC) {
| fadd
} else {
| fsub
}
| FPU_SET_ZVAL_DVAL op1_def_addr
|.endif
} }
if ((opline->opcode == ZEND_PRE_INC || opline->opcode == ZEND_PRE_DEC) && if ((opline->opcode == ZEND_PRE_INC || opline->opcode == ZEND_PRE_DEC) &&
opline->result_type != IS_UNUSED) { opline->result_type != IS_UNUSED) {
@ -3262,7 +3123,6 @@ static int zend_jit_math_long_long(dasm_State **Dst,
| jo >1 | jo >1
|.cold_code |.cold_code
|1: |1:
|.if SSE
zend_reg tmp_reg1 = ZREG_XMM0; zend_reg tmp_reg1 = ZREG_XMM0;
zend_reg tmp_reg2 = ZREG_XMM1; zend_reg tmp_reg2 = ZREG_XMM1;
@ -3274,12 +3134,6 @@ static int zend_jit_math_long_long(dasm_State **Dst,
| SSE_MATH_REG opcode, tmp_reg1, tmp_reg2 | SSE_MATH_REG opcode, tmp_reg1, tmp_reg2
} }
| SSE_SET_ZVAL_DVAL res_addr, tmp_reg1 | SSE_SET_ZVAL_DVAL res_addr, tmp_reg1
|.else
| FPU_GET_ZVAL_LVAL op2_addr
| FPU_GET_ZVAL_LVAL op1_addr
| FPU_MATH_REG opcode, st1
| FPU_SET_ZVAL_DVAL res_addr
|.endif
if ((res_use_info & (MAY_BE_ANY|MAY_BE_UNDEF|MAY_BE_REF)) != MAY_BE_DOUBLE) { if ((res_use_info & (MAY_BE_ANY|MAY_BE_UNDEF|MAY_BE_REF)) != MAY_BE_DOUBLE) {
| SET_ZVAL_TYPE_INFO res_addr, IS_DOUBLE | SET_ZVAL_TYPE_INFO res_addr, IS_DOUBLE
} }
@ -3314,7 +3168,6 @@ static int zend_jit_math_long_double(dasm_State **Dst,
zend_jit_addr res_addr, zend_jit_addr res_addr,
uint32_t res_use_info) uint32_t res_use_info)
{ {
|.if SSE
zend_reg result_reg = zend_reg result_reg =
(Z_MODE(res_addr) == IS_REG) ? Z_REG(res_addr) : ZREG_XMM0; (Z_MODE(res_addr) == IS_REG) ? Z_REG(res_addr) : ZREG_XMM0;
@ -3325,11 +3178,6 @@ static int zend_jit_math_long_double(dasm_State **Dst,
| SSE_MATH opcode, result_reg, op2_addr | SSE_MATH opcode, result_reg, op2_addr
} }
| SSE_SET_ZVAL_DVAL res_addr, result_reg | SSE_SET_ZVAL_DVAL res_addr, result_reg
|.else
| FPU_GET_ZVAL_LVAL op1_addr
| FPU_MATH opcode, op2_addr
| FPU_SET_ZVAL_DVAL res_addr
|.endif
if (Z_MODE(res_addr) == IS_MEM_ZVAL) { if (Z_MODE(res_addr) == IS_MEM_ZVAL) {
if ((res_use_info & (MAY_BE_ANY|MAY_BE_UNDEF|MAY_BE_REF)) != MAY_BE_DOUBLE) { if ((res_use_info & (MAY_BE_ANY|MAY_BE_UNDEF|MAY_BE_REF)) != MAY_BE_DOUBLE) {
@ -3350,7 +3198,6 @@ static int zend_jit_math_double_long(dasm_State **Dst,
zend_jit_addr res_addr, zend_jit_addr res_addr,
uint32_t res_use_info) uint32_t res_use_info)
{ {
|.if SSE
zend_reg result_reg; zend_reg result_reg;
if (zend_is_commutative(opcode)) { if (zend_is_commutative(opcode)) {
@ -3396,16 +3243,6 @@ static int zend_jit_math_double_long(dasm_State **Dst,
} }
} }
| SSE_SET_ZVAL_DVAL res_addr, result_reg | SSE_SET_ZVAL_DVAL res_addr, result_reg
|.else
| FPU_GET_ZVAL_LVAL op2_addr
if (zend_is_commutative(opcode)) {
| FPU_MATH opcode, op1_addr
} else {
| FPU_GET_ZVAL_DVAL op1_addr
| FPU_MATH_REG opcode, st1
}
| FPU_SET_ZVAL_DVAL res_addr
|.endif
if (Z_MODE(res_addr) == IS_MEM_ZVAL) { if (Z_MODE(res_addr) == IS_MEM_ZVAL) {
if (Z_MODE(op1_addr) != IS_MEM_ZVAL || Z_REG(op1_addr) != Z_REG(res_addr) || Z_OFFSET(op1_addr) != Z_OFFSET(res_addr)) { if (Z_MODE(op1_addr) != IS_MEM_ZVAL || Z_REG(op1_addr) != Z_REG(res_addr) || Z_OFFSET(op1_addr) != Z_OFFSET(res_addr)) {
@ -3429,8 +3266,6 @@ static int zend_jit_math_double_double(dasm_State **Dst,
uint32_t res_use_info) uint32_t res_use_info)
{ {
zend_bool same_ops = zend_jit_same_addr(op1_addr, op2_addr); zend_bool same_ops = zend_jit_same_addr(op1_addr, op2_addr);
|.if SSE
zend_reg result_reg; zend_reg result_reg;
if (Z_MODE(res_addr) == IS_REG) { if (Z_MODE(res_addr) == IS_REG) {
@ -3482,11 +3317,6 @@ static int zend_jit_math_double_double(dasm_State **Dst,
} }
} }
| SSE_SET_ZVAL_DVAL res_addr, result_reg | SSE_SET_ZVAL_DVAL res_addr, result_reg
|.else
| FPU_GET_ZVAL_DVAL op1_addr
| FPU_MATH opcode, op2_addr
| FPU_SET_ZVAL_DVAL res_addr
|.endif
if (Z_MODE(res_addr) == IS_MEM_ZVAL) { if (Z_MODE(res_addr) == IS_MEM_ZVAL) {
if (Z_MODE(op1_addr) != IS_MEM_ZVAL || Z_REG(op1_addr) != Z_REG(res_addr) || Z_OFFSET(op1_addr) != Z_OFFSET(res_addr)) { if (Z_MODE(op1_addr) != IS_MEM_ZVAL || Z_REG(op1_addr) != Z_REG(res_addr) || Z_OFFSET(op1_addr) != Z_OFFSET(res_addr)) {
@ -5800,46 +5630,28 @@ static int zend_jit_cmp_double_common(dasm_State **Dst, const zend_op *opline, i
static int zend_jit_cmp_long_double(dasm_State **Dst, const zend_op *opline, int b, zend_op_array *op_array, zend_ssa *ssa, zend_jit_addr op1_addr, zend_jit_addr op2_addr) static int zend_jit_cmp_long_double(dasm_State **Dst, const zend_op *opline, int b, zend_op_array *op_array, zend_ssa *ssa, zend_jit_addr op1_addr, zend_jit_addr op2_addr)
{ {
|.if SSE
zend_reg tmp_reg = ZREG_XMM0; zend_reg tmp_reg = ZREG_XMM0;
| SSE_GET_ZVAL_LVAL tmp_reg, op1_addr | SSE_GET_ZVAL_LVAL tmp_reg, op1_addr
| SSE_AVX_OP ucomisd, vucomisd, tmp_reg, op2_addr | SSE_AVX_OP ucomisd, vucomisd, tmp_reg, op2_addr
|.else
| FPU_GET_ZVAL_DVAL op2_addr
| FPU_GET_ZVAL_LVAL op1_addr
| fucomip st1
| fstp st0
|.endif
return zend_jit_cmp_double_common(Dst, opline, b, op_array, ssa, 0); return zend_jit_cmp_double_common(Dst, opline, b, op_array, ssa, 0);
} }
static int zend_jit_cmp_double_long(dasm_State **Dst, const zend_op *opline, int b, zend_op_array *op_array, zend_ssa *ssa, zend_jit_addr op1_addr, zend_jit_addr op2_addr) static int zend_jit_cmp_double_long(dasm_State **Dst, const zend_op *opline, int b, zend_op_array *op_array, zend_ssa *ssa, zend_jit_addr op1_addr, zend_jit_addr op2_addr)
{ {
zend_bool swap = 0;
|.if SSE
zend_reg tmp_reg = ZREG_XMM0; zend_reg tmp_reg = ZREG_XMM0;
| SSE_GET_ZVAL_LVAL tmp_reg, op2_addr | SSE_GET_ZVAL_LVAL tmp_reg, op2_addr
| SSE_AVX_OP ucomisd, vucomisd, tmp_reg, op1_addr | SSE_AVX_OP ucomisd, vucomisd, tmp_reg, op1_addr
swap = 1;
|.else
| FPU_GET_ZVAL_LVAL op2_addr
| FPU_GET_ZVAL_DVAL op1_addr
| fucomip st1
| fstp st0
|.endif
return zend_jit_cmp_double_common(Dst, opline, b, op_array, ssa, swap); return zend_jit_cmp_double_common(Dst, opline, b, op_array, ssa, /* swap */ 1);
} }
static int zend_jit_cmp_double_double(dasm_State **Dst, const zend_op *opline, int b, zend_op_array *op_array, zend_ssa *ssa, zend_jit_addr op1_addr, zend_jit_addr op2_addr) static int zend_jit_cmp_double_double(dasm_State **Dst, const zend_op *opline, int b, zend_op_array *op_array, zend_ssa *ssa, zend_jit_addr op1_addr, zend_jit_addr op2_addr)
{ {
zend_bool swap = 0; zend_bool swap = 0;
|.if SSE
if (Z_MODE(op1_addr) == IS_REG) { if (Z_MODE(op1_addr) == IS_REG) {
| SSE_AVX_OP ucomisd, vucomisd, Z_REG(op1_addr), op2_addr | SSE_AVX_OP ucomisd, vucomisd, Z_REG(op1_addr), op2_addr
} else if (Z_MODE(op2_addr) == IS_REG) { } else if (Z_MODE(op2_addr) == IS_REG) {
@ -5851,12 +5663,6 @@ static int zend_jit_cmp_double_double(dasm_State **Dst, const zend_op *opline, i
| SSE_GET_ZVAL_DVAL tmp_reg, op1_addr | SSE_GET_ZVAL_DVAL tmp_reg, op1_addr
| SSE_AVX_OP ucomisd, vucomisd, tmp_reg, op2_addr | SSE_AVX_OP ucomisd, vucomisd, tmp_reg, op2_addr
} }
|.else
| FPU_GET_ZVAL_DVAL op2_addr
| FPU_GET_ZVAL_DVAL op1_addr
| fucomip st1
| fstp st0
|.endif
return zend_jit_cmp_double_common(Dst, opline, b, op_array, ssa, swap); return zend_jit_cmp_double_common(Dst, opline, b, op_array, ssa, swap);
} }
@ -6790,19 +6596,12 @@ static int zend_jit_bool_jmpznz(dasm_State **Dst, const zend_op *opline, int b,
} }
if ((op1_info & MAY_BE_ANY) == MAY_BE_DOUBLE) { if ((op1_info & MAY_BE_ANY) == MAY_BE_DOUBLE) {
|.if SSE
if (zend_jit_x86_flags & ZEND_JIT_CPU_AVX) { if (zend_jit_x86_flags & ZEND_JIT_CPU_AVX) {
| vxorps xmm0, xmm0, xmm0 | vxorps xmm0, xmm0, xmm0
} else { } else {
| xorps xmm0, xmm0 | xorps xmm0, xmm0
} }
| SSE_AVX_OP ucomisd, vucomisd, ZREG_XMM0, op1_addr | SSE_AVX_OP ucomisd, vucomisd, ZREG_XMM0, op1_addr
|.else
| FPU_GET_ZVAL_DVAL op1_addr
| fldz
| fucomip st1
| fstp st0
|.endif
if (set_bool) { if (set_bool) {
if (false_label != (uint32_t)-1) { // JMPZ_EX if (false_label != (uint32_t)-1) { // JMPZ_EX