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Implement optimized send
This commit is contained in:
Takashi Kokubun
parent
2603d7a0b7
commit
2cc4f506ba
Notes:
git
2023-03-06 07:29:57 +00:00
9 changed files with 247 additions and 73 deletions
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@ -1,5 +1,8 @@
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# frozen_string_literal: true
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module RubyVM::MJIT
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# 8-bit memory access
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class BytePtr < Data.define(:reg, :disp); end
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# 32-bit memory access
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class DwordPtr < Data.define(:reg, :disp); end
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@ -66,7 +69,7 @@ module RubyVM::MJIT
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def add(dst, src)
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case [dst, src]
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# ADD r/m64, imm8 (Mod 00: [reg])
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in [[Symbol => dst_reg], Integer => src_imm] if r64?(dst_reg) && imm8?(src_imm)
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in [Array[Symbol => dst_reg], Integer => src_imm] if r64?(dst_reg) && imm8?(src_imm)
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# REX.W + 83 /0 ib
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# MI: Operand 1: ModRM:r/m (r, w), Operand 2: imm8/16/32
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insn(
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@ -132,7 +135,7 @@ module RubyVM::MJIT
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imm: imm32(src_imm),
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)
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# AND r64, r/m64 (Mod 01: [reg]+disp8)
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in [Symbol => dst_reg, [Symbol => src_reg, Integer => src_disp]] if r64?(dst_reg) && r64?(src_reg) && imm8?(src_disp)
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in [Symbol => dst_reg, Array[Symbol => src_reg, Integer => src_disp]] if r64?(dst_reg) && r64?(src_reg) && imm8?(src_disp)
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# REX.W + 23 /r
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# RM: Operand 1: ModRM:reg (r, w), Operand 2: ModRM:r/m (r)
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insn(
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@ -274,7 +277,7 @@ module RubyVM::MJIT
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mod_rm: ModRM[mod: Mod11, reg: dst_reg, rm: src_reg],
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)
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# CMOVZ r64, r/m64 (Mod 01: [reg]+disp8)
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in [Symbol => dst_reg, [Symbol => src_reg, Integer => src_disp]] if r64?(dst_reg) && r64?(src_reg) && imm8?(src_disp)
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in [Symbol => dst_reg, Array[Symbol => src_reg, Integer => src_disp]] if r64?(dst_reg) && r64?(src_reg) && imm8?(src_disp)
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# REX.W + 0F 44 /r
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# RM: Operand 1: ModRM:reg (r, w), Operand 2: ModRM:r/m (r)
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insn(
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@ -290,6 +293,16 @@ module RubyVM::MJIT
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def cmp(left, right)
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case [left, right]
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# CMP r/m8, imm8 (Mod 01: [reg]+disp8)
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in [BytePtr[reg: left_reg, disp: left_disp], Integer => right_imm] if r64?(left_reg) && imm8?(left_disp) && imm8?(right_imm)
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# 80 /7 ib
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# MI: Operand 1: ModRM:r/m (r), Operand 2: imm8/16/32
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insn(
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opcode: 0x80,
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mod_rm: ModRM[mod: Mod01, reg: 7, rm: left_reg],
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disp: left_disp,
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imm: imm8(right_imm),
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)
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# CMP r/m32, imm32 (Mod 01: [reg]+disp8)
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in [DwordPtr[reg: left_reg, disp: left_disp], Integer => right_imm] if imm8?(left_disp) && imm32?(right_imm)
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# 81 /7 id
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@ -301,7 +314,7 @@ module RubyVM::MJIT
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imm: imm32(right_imm),
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)
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# CMP r/m64, imm8 (Mod 01: [reg]+disp8)
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in [[Symbol => left_reg, Integer => left_disp], Integer => right_imm] if r64?(left_reg) && imm8?(left_disp) && imm8?(right_imm)
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in [Array[Symbol => left_reg, Integer => left_disp], Integer => right_imm] if r64?(left_reg) && imm8?(left_disp) && imm8?(right_imm)
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# REX.W + 83 /7 ib
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# MI: Operand 1: ModRM:r/m (r), Operand 2: imm8/16/32
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insn(
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@ -321,8 +334,18 @@ module RubyVM::MJIT
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mod_rm: ModRM[mod: Mod11, reg: 7, rm: left_reg],
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imm: imm8(right_imm),
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)
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# CMP r/m64, imm32 (Mod 11: reg)
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in [Symbol => left_reg, Integer => right_imm] if r64?(left_reg) && imm32?(right_imm)
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# REX.W + 81 /7 id
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# MI: Operand 1: ModRM:r/m (r), Operand 2: imm8/16/32
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insn(
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prefix: REX_W,
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opcode: 0x81,
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mod_rm: ModRM[mod: Mod11, reg: 7, rm: left_reg],
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imm: imm32(right_imm),
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)
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# CMP r/m64, r64 (Mod 01: [reg]+disp8)
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in [[Symbol => left_reg, Integer => left_disp], Symbol => right_reg] if r64?(right_reg)
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in [Array[Symbol => left_reg, Integer => left_disp], Symbol => right_reg] if r64?(right_reg)
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# REX.W + 39 /r
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# MR: Operand 1: ModRM:r/m (r), Operand 2: ModRM:reg (r)
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insn(
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@ -393,7 +416,7 @@ module RubyVM::MJIT
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# E9 cd
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insn(opcode: 0xe9, imm: rel32(dst_addr))
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# JMP r/m64 (Mod 01: [reg]+disp8)
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in [Symbol => dst_reg, Integer => dst_disp] if imm8?(dst_disp)
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in Array[Symbol => dst_reg, Integer => dst_disp] if imm8?(dst_disp)
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# FF /4
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insn(opcode: 0xff, mod_rm: ModRM[mod: Mod01, reg: 4, rm: dst_reg], disp: dst_disp)
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# JMP r/m64 (Mod 11: reg)
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@ -456,7 +479,7 @@ module RubyVM::MJIT
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def lea(dst, src)
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case [dst, src]
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# LEA r64,m (Mod 01: [reg]+disp8)
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in [Symbol => dst_reg, [Symbol => src_reg, Integer => src_disp]] if r64?(dst_reg) && r64?(src_reg) && imm8?(src_disp)
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in [Symbol => dst_reg, Array[Symbol => src_reg, Integer => src_disp]] if r64?(dst_reg) && r64?(src_reg) && imm8?(src_disp)
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# REX.W + 8D /r
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# RM: Operand 1: ModRM:reg (w), Operand 2: ModRM:r/m (r)
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insn(
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@ -466,7 +489,7 @@ module RubyVM::MJIT
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disp: imm8(src_disp),
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)
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# LEA r64,m (Mod 10: [reg]+disp32)
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in [Symbol => dst_reg, [Symbol => src_reg, Integer => src_disp]] if r64?(dst_reg) && r64?(src_reg) && imm32?(src_disp)
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in [Symbol => dst_reg, Array[Symbol => src_reg, Integer => src_disp]] if r64?(dst_reg) && r64?(src_reg) && imm32?(src_disp)
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# REX.W + 8D /r
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# RM: Operand 1: ModRM:reg (w), Operand 2: ModRM:r/m (r)
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insn(
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@ -485,7 +508,7 @@ module RubyVM::MJIT
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in Symbol => dst_reg
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case src
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# MOV r64, r/m64 (Mod 00: [reg])
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in [Symbol => src_reg] if r64?(dst_reg) && r64?(src_reg)
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in Array[Symbol => src_reg] if r64?(dst_reg) && r64?(src_reg)
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# REX.W + 8B /r
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# RM: Operand 1: ModRM:reg (w), Operand 2: ModRM:r/m (r)
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insn(
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@ -494,7 +517,7 @@ module RubyVM::MJIT
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mod_rm: ModRM[mod: Mod00, reg: dst_reg, rm: src_reg],
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)
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# MOV r64, r/m64 (Mod 01: [reg]+disp8)
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in [Symbol => src_reg, Integer => src_disp] if r64?(dst_reg) && r64?(src_reg) && imm8?(src_disp)
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in Array[Symbol => src_reg, Integer => src_disp] if r64?(dst_reg) && r64?(src_reg) && imm8?(src_disp)
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# REX.W + 8B /r
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# RM: Operand 1: ModRM:reg (w), Operand 2: ModRM:r/m (r)
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insn(
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@ -504,7 +527,7 @@ module RubyVM::MJIT
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disp: src_disp,
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)
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# MOV r64, r/m64 (Mod 10: [reg]+disp16)
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in [Symbol => src_reg, Integer => src_disp] if r64?(dst_reg) && r64?(src_reg) && imm32?(src_disp)
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in Array[Symbol => src_reg, Integer => src_disp] if r64?(dst_reg) && r64?(src_reg) && imm32?(src_disp)
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# REX.W + 8B /r
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# RM: Operand 1: ModRM:reg (w), Operand 2: ModRM:r/m (r)
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insn(
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@ -523,7 +546,7 @@ module RubyVM::MJIT
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mod_rm: ModRM[mod: Mod11, reg: dst_reg, rm: src_reg],
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)
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# MOV r32 r/m32 (Mod 01: [reg]+disp8)
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in [Symbol => src_reg, Integer => src_disp] if r32?(dst_reg) && imm8?(src_disp)
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in Array[Symbol => src_reg, Integer => src_disp] if r32?(dst_reg) && imm8?(src_disp)
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# 8B /r
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# RM: Operand 1: ModRM:reg (w), Operand 2: ModRM:r/m (r)
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insn(
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@ -563,7 +586,7 @@ module RubyVM::MJIT
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else
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raise NotImplementedError, "mov: not-implemented operands: #{dst.inspect}, #{src.inspect}"
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end
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in [Symbol => dst_reg]
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in Array[Symbol => dst_reg]
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case src
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# MOV r/m64, imm32 (Mod 00: [reg])
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in Integer => src_imm if r64?(dst_reg) && imm32?(src_imm)
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@ -587,7 +610,7 @@ module RubyVM::MJIT
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else
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raise NotImplementedError, "mov: not-implemented operands: #{dst.inspect}, #{src.inspect}"
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end
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in [Symbol => dst_reg, Integer => dst_disp]
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in Array[Symbol => dst_reg, Integer => dst_disp]
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# Optimize encoding when disp is 0
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return mov([dst_reg], src) if dst_disp == 0
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@ -645,7 +668,7 @@ module RubyVM::MJIT
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def or(dst, src)
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case [dst, src]
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# OR r64, r/m64 (Mod 01: [reg]+disp8)
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in [Symbol => dst_reg, [Symbol => src_reg, Integer => src_disp]] if r64?(dst_reg) && r64?(src_reg) && imm8?(src_disp)
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in [Symbol => dst_reg, Array[Symbol => src_reg, Integer => src_disp]] if r64?(dst_reg) && r64?(src_reg) && imm8?(src_disp)
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# REX.W + 0B /r
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# RM: Operand 1: ModRM:reg (r, w), Operand 2: ModRM:r/m (r)
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insn(
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@ -734,7 +757,7 @@ module RubyVM::MJIT
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def test(left, right)
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case [left, right]
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# TEST r/m8*, imm8 (Mod 01: [reg]+disp8)
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in [[Symbol => left_reg, Integer => left_disp], Integer => right_imm] if imm8?(right_imm) && right_imm >= 0
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in [Array[Symbol => left_reg, Integer => left_disp], Integer => right_imm] if imm8?(right_imm) && right_imm >= 0
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# REX + F6 /0 ib
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# MI: Operand 1: ModRM:r/m (r), Operand 2: imm8/16/32
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insn(
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@ -744,7 +767,7 @@ module RubyVM::MJIT
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imm: imm8(right_imm),
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)
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# TEST r/m64, imm32 (Mod 01: [reg]+disp8)
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in [[Symbol => left_reg, Integer => left_disp], Integer => right_imm] if imm32?(right_imm)
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in [Array[Symbol => left_reg, Integer => left_disp], Integer => right_imm] if imm32?(right_imm)
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# REX.W + F7 /0 id
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# MI: Operand 1: ModRM:r/m (r), Operand 2: imm8/16/32
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insn(
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