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ZJIT: Make sure output operands are not VRegs

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Make LIR SSA.
This commit is contained in:
Max Bernstein 2025-08-12 13:06:47 -04:00
parent 549a326f86
commit 3a7e2a4ea5
1 changed files with 5 additions and 1 deletions
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6
zjit/src/backend/lir.rs
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@ -1982,6 +1982,7 @@ impl Assembler {
}
pub fn cpop_into(&mut self, opnd: Opnd) {
assert!(matches!(opnd, Opnd::Reg(_)), "Destination of cpop_into must be a register, got: {opnd:?}");
self.push_insn(Insn::CPopInto(opnd));
}
@ -2135,6 +2136,7 @@ impl Assembler {
}
pub fn lea_into(&mut self, out: Opnd, opnd: Opnd) {
assert!(matches!(out, Opnd::Reg(_)), "Destination of lea_into must be a register, got: {out:?}");
self.push_insn(Insn::Lea { opnd, out });
}
@ -2160,7 +2162,7 @@ impl Assembler {
}
pub fn load_into(&mut self, dest: Opnd, opnd: Opnd) {
assert!(matches!(dest, Opnd::Reg(_) | Opnd::VReg{..}), "Destination of load_into must be a register");
assert!(matches!(dest, Opnd::Reg(_)), "Destination of load_into must be a register, got: {dest:?}");
match (dest, opnd) {
(Opnd::Reg(dest), Opnd::Reg(opnd)) if dest == opnd => {}, // skip if noop
_ => self.push_insn(Insn::LoadInto { dest, opnd }),
@ -2186,6 +2188,7 @@ impl Assembler {
}
pub fn mov(&mut self, dest: Opnd, src: Opnd) {
assert!(!matches!(dest, Opnd::VReg { .. }), "Destination of mov must not be Opnd::VReg, got: {dest:?}");
self.push_insn(Insn::Mov { dest, src });
}
@ -2223,6 +2226,7 @@ impl Assembler {
}
pub fn store(&mut self, dest: Opnd, src: Opnd) {
assert!(!matches!(dest, Opnd::VReg { .. }), "Destination of store must not be Opnd::VReg, got: {dest:?}");
self.push_insn(Insn::Store { dest, src });
}