Xiaolin Zheng
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664e5b1d2e
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8294187: RISC-V: Unify all relocations for the backend into AbstractAssembler::relocate()
Reviewed-by: fjiang, yadongwang, fyang
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2022-09-23 13:15:44 +00:00 |
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Xiaolin Zheng
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a216960d71
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8294087: RISC-V: RVC: Fix a potential alignment issue and add more alignment assertions for the patchable calls/nops
Reviewed-by: shade, fjiang, fyang
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2022-09-22 11:43:47 +00:00 |
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Xiaolin Zheng
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d5bee4a0df
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8294086: RISC-V: Cleanup InstructionMark usages in the backend
Reviewed-by: fjiang, fyang
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2022-09-22 03:48:06 +00:00 |
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Feilong Jiang
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742bc041ea
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8294100: RISC-V: Move rt_call and xxx_move from SharedRuntime to MacroAssembler
Reviewed-by: shade, fyang
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2022-09-22 00:58:31 +00:00 |
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Yanhong Zhu
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84ee1a291c
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8293781: RISC-V: Clarify types of calls
Reviewed-by: fjiang, fyang, yadongwang
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2022-09-20 12:12:35 +00:00 |
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Feilong Jiang
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5feca688df
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8293840: RISC-V: Remove cbuf parameter from far_call/far_jump/trampoline_call
Reviewed-by: fyang
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2022-09-16 11:40:31 +00:00 |
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Fei Yang
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7376c55219
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8293769: RISC-V: Add a second temporary register for BarrierSetAssembler::load_at
Reviewed-by: fjiang, shade
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2022-09-14 23:50:35 +00:00 |
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Feilong Jiang
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68645ebffb
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8293566: RISC-V: Clean up push and pop registers
Reviewed-by: fyang, shade
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2022-09-13 01:07:04 +00:00 |
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Fei Yang
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43e191d64b
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8293524: RISC-V: Use macro-assembler functions as appropriate
Reviewed-by: shade, fjiang
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2022-09-09 00:18:48 +00:00 |
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Fei Yang
|
fc5f97fe37
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8293474: RISC-V: Unify the way of moving function pointer
Reviewed-by: yadongwang, fjiang, shade
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2022-09-08 01:14:08 +00:00 |
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Fei Yang
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5bed9f7675
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8293290: RISC-V: Explicitly pass a third temp register to MacroAssembler::store_heap_oop
Reviewed-by: shade
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2022-09-05 10:02:08 +00:00 |
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Fei Yang
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38e6706315
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8293050: RISC-V: Remove redundant non-null assertions about macro-assembler
Reviewed-by: fjiang, yadongwang, shade
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2022-08-31 12:24:28 +00:00 |
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Axel Boldt-Christmas
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9e3176bd09
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8293035: Cleanup MacroAssembler::movoop code patching logic aarch64 riscv
Reviewed-by: eosterlund, fyang
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2022-08-31 07:42:22 +00:00 |
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Vladimir Ivanov
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6e248279cf
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8292878: x86: Make scratch register usage explicit in assembler code
Reviewed-by: kvn, shade
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2022-08-30 18:45:24 +00:00 |
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Feilong Jiang
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21a736954f
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8292575: riscv: Represent Registers as values
Reviewed-by: yzhu, yadongwang, fyang
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2022-08-30 09:24:37 +00:00 |
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Yadong Wang
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e016363b54
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8293007: riscv: failed to build after JDK-8290025
Reviewed-by: fyang, fjiang, shade
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2022-08-30 01:17:41 +00:00 |
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Aleksey Shipilev
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f57d34242c
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8292867: RISC-V: Simplify weak CAS return value handling
Reviewed-by: yadongwang, fyang
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2022-08-25 16:24:53 +00:00 |
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Yadong Wang
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5a539e8da7
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8291893: riscv: remove fence.i used in user space
Reviewed-by: fyang, vkempik
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2022-08-08 11:47:36 +00:00 |
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Aleksey Shipilev
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8159a1ab70
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8290706: Remove the support for inline contiguous allocations
Reviewed-by: eosterlund, aph, rrich, fyang, thartmann
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2022-07-26 17:19:10 +00:00 |
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Fei Yang
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92067e2003
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8290137: riscv: small refactoring for add_memory_int32/64
Reviewed-by: yadongwang, fjiang, shade
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2022-07-18 13:01:35 +00:00 |
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Coleen Phillimore
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270cf67e5f
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8288752: Split thread implementation files
Reviewed-by: dholmes, rehn, iklam
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2022-06-22 12:49:25 +00:00 |
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Xiaolin Zheng
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b5a646ee6c
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8287425: Remove unnecessary register push for MacroAssembler::check_klass_subtype_slow_path
Co-authored-by: Wei Kuai <kuaiwei.kw@alibaba-inc.com>
Reviewed-by: kvn
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2022-06-02 20:31:26 +00:00 |
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Feilong Jiang
|
0ef3d8551d
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8287552: riscv: Fix comment typo in li64
Co-authored-by: Dingli Zhang <dingli@iscas.ac.cn>
Reviewed-by: fyang
|
2022-06-01 09:29:51 +00:00 |
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Xiaolin Zheng
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447ae00616
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8287418: riscv: Fix correctness issue of MacroAssembler::movptr
Reviewed-by: fjiang, yadongwang, fyang
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2022-05-30 07:45:50 +00:00 |
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Yadong Wang
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94b533a94c
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8285699: riscv: Provide information when hitting a HaltNode
Reviewed-by: fyang
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2022-04-29 03:19:29 +00:00 |
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Xiaolin Zheng
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4bf2c18d6c
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8285435: Show file and line in MacroAssembler::verify_oop for AArch64 and RISC-V platforms (Port from x86)
Reviewed-by: ngasson, fyang
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2022-04-25 23:57:08 +00:00 |
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Xiaolin Zheng
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9d9f4e502f
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8285437: riscv: Fix MachNode size mismatch for MacroAssembler::verify_oops*
Reviewed-by: shade, fyang
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2022-04-24 02:17:03 +00:00 |
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Feilong Jiang
|
b10833bbf3
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8285303: riscv: Incorrect register mask in call_native_base
Co-authored-by: Dingli Zhang <dingli@iscas.ac.cn>
Reviewed-by: fyang, yadongwang
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2022-04-22 23:48:57 +00:00 |
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Magnus Ihse Bursie
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4594696f54
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8284903: Fix typos in hotspot
Reviewed-by: cjplummer, coleenp, kvn, lucy, stefank
|
2022-04-19 19:10:52 +00:00 |
|
Feilong Jiang
|
060a188733
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8283865: riscv: Break down -XX:+UseRVB into seperate options for each bitmanip extension
Reviewed-by: fyang, shade
|
2022-04-02 02:55:50 +00:00 |
|
Xiaolin Zheng
|
b82b009047
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8283737: riscv: MacroAssembler::stop() should emit fixed-length instruction sequence
Reviewed-by: fyang, shade
|
2022-03-30 09:04:55 +00:00 |
|
Fei Yang
|
5905b02c0e
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8276799: Implementation of JEP 422: Linux/RISC-V Port
Co-authored-by: Yadong Wang <yadonn.wang@huawei.com>
Co-authored-by: Yanhong Zhu <zhuyanhong2@huawei.com>
Co-authored-by: Feilong Jiang <jiangfeilong@huawei.com>
Co-authored-by: Kun Wang <wangkun49@huawei.com>
Co-authored-by: Zhuxuan Ni <nizhuxuan@huawei.com>
Co-authored-by: Taiping Guo <guotaiping1@huawei.com>
Co-authored-by: Kang He <hekang6@huawei.com>
Co-authored-by: Aleksey Shipilev <shade@openjdk.org>
Co-authored-by: Xiaolin Zheng <yunyao.zxl@alibaba-inc.com>
Co-authored-by: Kuai Wei <kuaiwei.kw@alibaba-inc.com>
Co-authored-by: Magnus Ihse Bursie <ihse@openjdk.org>
Reviewed-by: ihse, dholmes, rriggs, kvn, shade
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2022-03-24 09:22:46 +00:00 |
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