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56 commits

Author SHA1 Message Date
Axel Boldt-Christmas
c7056737e3 8299089: Instrument global jni handles with tag to make them distinguishable 
Co-authored-by: Stefan Karlsson <stefank@openjdk.org>
Co-authored-by: Martin Doerr <mdoerr@openjdk.org>
Co-authored-by: Leslie Zhai <lzhai@openjdk.org>
Reviewed-by: eosterlund, stefank, ayang
 2023-01-18 09:21:08 +00:00
Xiaolin Zheng
2f4098e1dc 8299168: RISC-V: Fix MachNode size mismatch for MacroAssembler::_verify_oops* 
Reviewed-by: fyang
 2022-12-23 09:22:39 +00:00
Xiaolin Zheng
74f346b33f 8298075: RISC-V: Implement post-call NOPs 
Reviewed-by: fyang, luhenry
 2022-12-08 02:19:35 +00:00
Axel Boldt-Christmas
085f96cb1a 8295258: Add BasicType argument to AccessInternal::decorator_fixup 
Reviewed-by: stefank, eosterlund
 2022-12-07 08:28:20 +00:00
Xiaolin Zheng
f9e0f1d5b3 8297763: Fix missing stub code expansion before align() in shared trampolines 
Reviewed-by: fyang, luhenry
 2022-12-05 12:43:57 +00:00
Fei Yang
c3b285a8ac 8296916: RISC-V: Move some small macro-assembler functions to header file 
Reviewed-by: fjiang, yadongwang, shade
 2022-11-16 12:01:42 +00:00
Yadong Wang
a2cdcdd65d 8296630: Fix SkipIfEqual on AArch64 and RISC-V 
Reviewed-by: ngasson, fyang, luhenry, aph
 2022-11-13 03:07:09 +00:00
Xiaolin Zheng
93fed9b251 8296448: RISC-V: Fix temp usages of heapbase register killed by MacroAssembler::en/decode_klass_not_null 
Reviewed-by: fyang, yadongwang
 2022-11-10 01:30:51 +00:00
Dingli Zhang
1169dc066c 8296447: RISC-V: Make the operands order of vrsub_vx/vrsub_vi consistent with RVV 1.0 spec 
Reviewed-by: luhenry, fyang
 2022-11-08 02:48:19 +00:00
Feilong Jiang
4c80dff2ca 8296435: RISC-V: Small refactoring for increment/decrement 
Reviewed-by: fyang
 2022-11-08 01:12:35 +00:00
Fei Yang
91292d56a9 8286301: Port JEP 425 to RISC-V 
Co-authored-by: Xiaolin Zheng <xlinzheng@openjdk.org>
Reviewed-by: fjiang, xlinzheng, yadongwang, jiefu, rrich
 2022-11-05 02:18:49 +00:00
Dingli Zhang
c116ae75a7 8295967: RISC-V: Support negVI/negVL instructions for Vector API 
Reviewed-by: yadongwang, fyang
 2022-11-04 09:08:26 +00:00
Dingli Zhang
2bd24c4542 8295968: RISC-V: Rename some assembler intrinsic functions for RVV 1.0 
Reviewed-by: fyang
 2022-11-02 12:34:23 +00:00
Ludovic Henry
e0c29307f7 8295282: Use Zicboz/cbo.zero to zero-out memory on RISC-V 
Reviewed-by: yadongwang, vkempik, fyang
 2022-10-25 20:11:48 +00:00
Zixian Cai
5dbd495115 8295457: Make the signatures of write barrier methods consistent 
Reviewed-by: tschatzl, shade
 2022-10-18 15:32:20 +00:00
Aleksey Shipilev
e7375f9c52 8295468: RISC-V: Minimal builds are broken 
Reviewed-by: stuefe, luhenry, fyang
 2022-10-18 15:07:01 +00:00
Axel Boldt-Christmas
6553065cab 8295273: Remove unused argument in [load/store]_sized_value on aarch64 and riscv 
Reviewed-by: fyang, haosun
 2022-10-18 08:58:25 +00:00
Xiaolin Zheng
529cc48f35 8295396: RISC-V: Cleanup useless CompressibleRegions 
Reviewed-by: fyang
 2022-10-18 01:15:49 +00:00
Xiaolin Zheng
9005af3b90 8295110: RISC-V: Mark out relocations as incompressible 
Reviewed-by: fyang, yadongwang
 2022-10-17 05:56:59 +00:00
Fei Yang
3d75e88eb2 8295270: RISC-V: Clean up and refactoring for assembler functions 
Reviewed-by: fjiang, yadongwang, shade
 2022-10-14 07:53:56 +00:00
Xiaolin Zheng
542cc602a7 8294366: RISC-V: Partially mark out incompressible regions 
Reviewed-by: fyang, yadongwang
 2022-10-08 06:41:45 +00:00
Dingli Zhang
7c60e6d2d6 8293770: RISC-V: Reuse runtime call trampolines 
Co-authored-by: zifeihan <caogui@iscas.ac.cn>
Reviewed-by: fyang, shade
 2022-09-30 07:31:57 +00:00
Xiaolin Zheng
1decdcee71 8294492: RISC-V: Use li instead of patchable movptr at non-patchable callsites 
Reviewed-by: fyang
 2022-09-29 07:21:07 +00:00
Fei Yang
d827fd830a 8294430: RISC-V: Small refactoring for movptr_with_offset 
Reviewed-by: fjiang, yadongwang, shade
 2022-09-28 00:22:16 +00:00
Xiaolin Zheng
664e5b1d2e 8294187: RISC-V: Unify all relocations for the backend into AbstractAssembler::relocate() 
Reviewed-by: fjiang, yadongwang, fyang
 2022-09-23 13:15:44 +00:00
Xiaolin Zheng
a216960d71 8294087: RISC-V: RVC: Fix a potential alignment issue and add more alignment assertions for the patchable calls/nops 
Reviewed-by: shade, fjiang, fyang
 2022-09-22 11:43:47 +00:00
Xiaolin Zheng
d5bee4a0df 8294086: RISC-V: Cleanup InstructionMark usages in the backend 
Reviewed-by: fjiang, fyang
 2022-09-22 03:48:06 +00:00
Feilong Jiang
742bc041ea 8294100: RISC-V: Move rt_call and xxx_move from SharedRuntime to MacroAssembler 
Reviewed-by: shade, fyang
 2022-09-22 00:58:31 +00:00
Yanhong Zhu
84ee1a291c 8293781: RISC-V: Clarify types of calls 
Reviewed-by: fjiang, fyang, yadongwang
 2022-09-20 12:12:35 +00:00
Feilong Jiang
5feca688df 8293840: RISC-V: Remove cbuf parameter from far_call/far_jump/trampoline_call 
Reviewed-by: fyang
 2022-09-16 11:40:31 +00:00
Fei Yang
7376c55219 8293769: RISC-V: Add a second temporary register for BarrierSetAssembler::load_at 
Reviewed-by: fjiang, shade
 2022-09-14 23:50:35 +00:00
Feilong Jiang
68645ebffb 8293566: RISC-V: Clean up push and pop registers 
Reviewed-by: fyang, shade
 2022-09-13 01:07:04 +00:00
Fei Yang
43e191d64b 8293524: RISC-V: Use macro-assembler functions as appropriate 
Reviewed-by: shade, fjiang
 2022-09-09 00:18:48 +00:00
Fei Yang
fc5f97fe37 8293474: RISC-V: Unify the way of moving function pointer 
Reviewed-by: yadongwang, fjiang, shade
 2022-09-08 01:14:08 +00:00
Fei Yang
5bed9f7675 8293290: RISC-V: Explicitly pass a third temp register to MacroAssembler::store_heap_oop 
Reviewed-by: shade
 2022-09-05 10:02:08 +00:00
Fei Yang
38e6706315 8293050: RISC-V: Remove redundant non-null assertions about macro-assembler 
Reviewed-by: fjiang, yadongwang, shade
 2022-08-31 12:24:28 +00:00
Axel Boldt-Christmas
9e3176bd09 8293035: Cleanup MacroAssembler::movoop code patching logic aarch64 riscv 
Reviewed-by: eosterlund, fyang
 2022-08-31 07:42:22 +00:00
Vladimir Ivanov
6e248279cf 8292878: x86: Make scratch register usage explicit in assembler code 
Reviewed-by: kvn, shade
 2022-08-30 18:45:24 +00:00
Feilong Jiang
21a736954f 8292575: riscv: Represent Registers as values 
Reviewed-by: yzhu, yadongwang, fyang
 2022-08-30 09:24:37 +00:00
Yadong Wang
e016363b54 8293007: riscv: failed to build after JDK-8290025 
Reviewed-by: fyang, fjiang, shade
 2022-08-30 01:17:41 +00:00
Aleksey Shipilev
f57d34242c 8292867: RISC-V: Simplify weak CAS return value handling 
Reviewed-by: yadongwang, fyang
 2022-08-25 16:24:53 +00:00
Yadong Wang
5a539e8da7 8291893: riscv: remove fence.i used in user space 
Reviewed-by: fyang, vkempik
 2022-08-08 11:47:36 +00:00
Aleksey Shipilev
8159a1ab70 8290706: Remove the support for inline contiguous allocations 
Reviewed-by: eosterlund, aph, rrich, fyang, thartmann
 2022-07-26 17:19:10 +00:00
Fei Yang
92067e2003 8290137: riscv: small refactoring for add_memory_int32/64 
Reviewed-by: yadongwang, fjiang, shade
 2022-07-18 13:01:35 +00:00
Coleen Phillimore
270cf67e5f 8288752: Split thread implementation files 
Reviewed-by: dholmes, rehn, iklam
 2022-06-22 12:49:25 +00:00
Xiaolin Zheng
b5a646ee6c 8287425: Remove unnecessary register push for MacroAssembler::check_klass_subtype_slow_path 
Co-authored-by: Wei Kuai <kuaiwei.kw@alibaba-inc.com>
Reviewed-by: kvn
 2022-06-02 20:31:26 +00:00
Feilong Jiang
0ef3d8551d 8287552: riscv: Fix comment typo in li64 
Co-authored-by: Dingli Zhang <dingli@iscas.ac.cn>
Reviewed-by: fyang
 2022-06-01 09:29:51 +00:00
Xiaolin Zheng
447ae00616 8287418: riscv: Fix correctness issue of MacroAssembler::movptr 
Reviewed-by: fjiang, yadongwang, fyang
 2022-05-30 07:45:50 +00:00
Yadong Wang
94b533a94c 8285699: riscv: Provide information when hitting a HaltNode 
Reviewed-by: fyang
 2022-04-29 03:19:29 +00:00
Xiaolin Zheng
4bf2c18d6c 8285435: Show file and line in MacroAssembler::verify_oop for AArch64 and RISC-V platforms (Port from x86) 
Reviewed-by: ngasson, fyang
 2022-04-25 23:57:08 +00:00